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1//===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the SchedModel for the POWER8 processor.10//11//===----------------------------------------------------------------------===//12 13def P8Model : SchedMachineModel {14 let IssueWidth = 8;15 let LoadLatency = 3;16 let MispredictPenalty = 16;17 let LoopMicroOpBufferSize = 60;18 let MicroOpBufferSize = 64;19 // TODO: Due to limitation of instruction definitions, non-P8 instructions20 // are required to be listed here. Change this after it got fixed.21 let CompleteModel = 0;22 let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,23 PairedVectorMemops, PCRelativeMemops,24 IsISA3_0, IsISA3_1, IsISAFuture];25}26 27let SchedModel = P8Model in {28 // Power8 Pipeline Units:29 30 def P8_LU_LS_FX : ProcResource<6>;31 def P8_LU_LS : ProcResource<4> { let Super = P8_LU_LS_FX; }32 def P8_LS : ProcResource<2> { let Super = P8_LU_LS; }33 def P8_LU : ProcResource<2> { let Super = P8_LU_LS; }34 def P8_FX : ProcResource<2> { let Super = P8_LU_LS_FX; }35 def P8_DFU : ProcResource<1>;36 def P8_BR : ProcResource<1> { let BufferSize = 16; }37 def P8_CY : ProcResource<1>;38 def P8_CRL : ProcResource<1>;39 def P8_VMX : ProcResource<2>;40 def P8_PM : ProcResource<2> {41 // This is workaround for scheduler to respect latency of long permute chain.42 let BufferSize = 1;43 let Super = P8_VMX;44 }45 def P8_XS : ProcResource<2> { let Super = P8_VMX; }46 def P8_VX : ProcResource<2> { let Super = P8_VMX; }47 def P8_FPU : ProcResource<4>;48 // Units for scalar, 2xDouble and 4xSingle49 def P8_FP_Scal : ProcResource<2> { let Super = P8_FPU; }50 def P8_FP_2x64 : ProcResource<2> { let Super = P8_FPU; }51 def P8_FP_4x32 : ProcResource<2> { let Super = P8_FPU; }52 53 // Power8 Dispatch Ports:54 // Two ports to do loads or fixed-point operations.55 // Two ports to do stores, fixed-point loads, or fixed-point operations.56 // Two ports for fixed-point operations.57 // Two issue ports shared by 2 DFP/2 VSX/2 VMX/1 CY/1 DFP operations.58 // One for branch operations.59 // One for condition register operations.60 61 // TODO: Model dispatch of cracked instructions.62 63 // Six ports in total are available for fixed-point operations.64 def P8_PORT_ALLFX : ProcResource<6>;65 // Four ports in total are available for fixed-point load operations.66 def P8_PORT_FXLD : ProcResource<4> { let Super = P8_PORT_ALLFX; }67 // Two ports to do loads or fixed-point operations.68 def P8_PORT_LD_FX : ProcResource<2> { let Super = P8_PORT_FXLD; }69 // Two ports to do stores, fixed-point loads, or fixed-point operations.70 def P8_PORT_ST_FXLD_FX : ProcResource<2> { let Super = P8_PORT_FXLD; }71 // Two issue ports shared by two floating-point, two VSX, two VMX, one crypto,72 // and one DFP operations.73 def P8_PORT_VMX_FP : ProcResource<2>;74 // One port for branch operation.75 def P8_PORT_BR : ProcResource<1>;76 // One port for condition register operation.77 def P8_PORT_CR : ProcResource<1>;78 79 def P8_ISSUE_FX : SchedWriteRes<[P8_PORT_ALLFX]>;80 def P8_ISSUE_FXLD : SchedWriteRes<[P8_PORT_FXLD]>;81 def P8_ISSUE_LD : SchedWriteRes<[P8_PORT_LD_FX]>;82 def P8_ISSUE_ST : SchedWriteRes<[P8_PORT_ST_FXLD_FX]>;83 def P8_ISSUE_VSX : SchedWriteRes<[P8_PORT_VMX_FP]>;84 def P8_ISSUE_BR : SchedWriteRes<[P8_PORT_BR]>;85 def P8_ISSUE_CR : SchedWriteRes<[P8_PORT_CR]>;86 87 // Power8 Instruction Latency & Port Groups:88 89 def P8_LS_LU_NONE : SchedWriteRes<[P8_LU, P8_LS]>;90 def P8_LS_FP_NONE : SchedWriteRes<[P8_LS, P8_FPU]>;91 def P8_LU_or_LS_3C : SchedWriteRes<[P8_LU_LS]> { let Latency = 3; }92 def P8_LS_FX_3C : SchedWriteRes<[P8_LS, P8_FX]> { let Latency = 3; }93 def P8_LU_or_LS_or_FX_2C : SchedWriteRes<[P8_LU_LS_FX]> { let Latency = 2; }94 def P8_LU_or_LS_FX_3C : SchedWriteRes<[P8_LU_LS, P8_FX]> { let Latency = 3; }95 def P8_FX_NONE : SchedWriteRes<[P8_FX]>;96 def P8_FX_1C : SchedWriteRes<[P8_FX]> { let Latency = 1; }97 def P8_FX_2C : SchedWriteRes<[P8_FX]> { let Latency = 2; }98 def P8_FX_3C : SchedWriteRes<[P8_FX]> { let Latency = 3; }99 def P8_FX_5C : SchedWriteRes<[P8_FX]> { let Latency = 5; }100 def P8_FX_10C : SchedWriteRes<[P8_FX]> { let Latency = 10; }101 def P8_FX_23C : SchedWriteRes<[P8_FX]> { let Latency = 23; }102 def P8_FX_15C : SchedWriteRes<[P8_FX]> { let Latency = 15; }103 def P8_FX_41C : SchedWriteRes<[P8_FX]> { let Latency = 41; }104 def P8_BR_2C : SchedWriteRes<[P8_BR]> { let Latency = 2; }105 def P8_CR_NONE : SchedWriteRes<[P8_CRL]>;106 def P8_CR_3C : SchedWriteRes<[P8_CRL]> { let Latency = 3; }107 def P8_CR_5C : SchedWriteRes<[P8_CRL]> { let Latency = 5; }108 def P8_LU_5C : SchedWriteRes<[P8_LU]> { let Latency = 5; }109 def P8_LU_FX_5C : SchedWriteRes<[P8_LU, P8_FX]> { let Latency = 5; }110 def P8_LS_FP_FX_2C : SchedWriteRes<[P8_LS, P8_FPU, P8_FX]> { let Latency = 2; }111 def P8_LS_FP_FX_3C : SchedWriteRes<[P8_LS, P8_FPU, P8_FX]> { let Latency = 3; }112 def P8_LS_3C : SchedWriteRes<[P8_LS]> { let Latency = 3; }113 def P8_FP_3C : SchedWriteRes<[P8_FPU]> { let Latency = 3; }114 def P8_FP_Scal_6C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 6; }115 def P8_FP_4x32_6C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 6; }116 def P8_FP_2x64_6C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 6; }117 def P8_FP_26C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 26; }118 def P8_FP_28C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 28; }119 def P8_FP_31C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 31; }120 def P8_FP_Scal_32C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 32; }121 def P8_FP_2x64_32C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 32; }122 def P8_FP_4x32_32C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 32; }123 def P8_FP_Scal_43C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 43; }124 def P8_FP_2x64_43C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 43; }125 def P8_XS_2C : SchedWriteRes<[P8_XS]> { let Latency = 2; }126 def P8_PM_2C : SchedWriteRes<[P8_PM]> { let Latency = 2; }127 def P8_XS_4C : SchedWriteRes<[P8_XS]> { let Latency = 4; }128 def P8_VX_7C : SchedWriteRes<[P8_VX]> { let Latency = 7; }129 def P8_XS_9C : SchedWriteRes<[P8_XS]> { let Latency = 9; }130 def P8_CY_6C : SchedWriteRes<[P8_CY]> { let Latency = 6; }131 def P8_DFU_13C : SchedWriteRes<[P8_DFU]> { let Latency = 13; }132 def P8_DFU_15C : SchedWriteRes<[P8_DFU]> { let Latency = 15; }133 def P8_DFU_17C : SchedWriteRes<[P8_DFU]> { let Latency = 17; }134 def P8_DFU_25C : SchedWriteRes<[P8_DFU]> { let Latency = 25; }135 def P8_DFU_32C : SchedWriteRes<[P8_DFU]> { let Latency = 32; }136 def P8_DFU_34C : SchedWriteRes<[P8_DFU]> { let Latency = 34; }137 def P8_DFU_40C : SchedWriteRes<[P8_DFU]> { let Latency = 40; }138 def P8_DFU_90C : SchedWriteRes<[P8_DFU]> { let Latency = 90; }139 def P8_DFU_96C : SchedWriteRes<[P8_DFU]> { let Latency = 96; }140 def P8_DFU_172C : SchedWriteRes<[P8_DFU]> { let Latency = 172; }141 // Direct move instructions142 def P8_DM_5C : SchedWriteRes<[]> { let Latency = 5; }143 144 // Instructions of CR pipeline145 146 def : InstRW<[P8_CR_NONE, P8_ISSUE_CR], (instrs MFCR, MFCR8)>;147 def : InstRW<[P8_CR_3C, P8_ISSUE_CR], (instrs MFOCRF, MFOCRF8)>;148 def : InstRW<[P8_CR_5C, P8_ISSUE_CR], (instrs MFLR, MFLR8, MFCTR, MFCTR8)>;149 150 // Instructions of CY pipeline151 152 def : InstRW<[P8_CY_6C, P8_ISSUE_VSX], (instrs153 VCIPHER, VCIPHERLAST, VNCIPHER, VNCIPHERLAST, VPMSUMB, VPMSUMD, VPMSUMH, VPMSUMW, VSBOX)>;154 155 // Instructions of FPU pipeline156 157 def : InstRW<[P8_FP_26C, P8_ISSUE_VSX], (instrs (instregex "^FDIVS(_rec)?$"), XSDIVSP)>;158 def : InstRW<[P8_FP_28C, P8_ISSUE_VSX], (instrs XVDIVSP)>;159 def : InstRW<[P8_FP_31C, P8_ISSUE_VSX], (instregex "^FSQRTS(_rec)?$")>;160 def : InstRW<[P8_FP_Scal_32C, P8_ISSUE_VSX], (instrs FDIV, FDIV_rec, XSDIVDP)>;161 def : InstRW<[P8_FP_2x64_32C, P8_ISSUE_VSX], (instrs XVDIVDP)>;162 def : InstRW<[P8_FP_4x32_32C, P8_ISSUE_VSX], (instrs XVSQRTSP)>;163 def : InstRW<[P8_FP_Scal_43C, P8_ISSUE_VSX], (instrs FSQRT, FSQRT_rec, XSSQRTDP)>;164 def : InstRW<[P8_FP_2x64_43C, P8_ISSUE_VSX], (instrs XVSQRTDP)>;165 166 def : InstRW<[P8_FP_3C, P8_ISSUE_VSX], (instrs167 MTFSFI_rec, MTFSF_rec, MTFSFI, MTFSFIb, MTFSF, MTFSFb, MTFSB0, MTFSB1)>;168 169 def : InstRW<[P8_FP_Scal_6C, P8_ISSUE_VSX], (instrs170 (instregex "^F(N)?M(ADD|SUB)(S)?(_rec)?$"),171 (instregex "^XS(N)?M(ADD|SUB)(A|M)(D|S)P$"),172 (instregex "^FC(F|T)I(D|W)(U)?(S|Z)?(_rec)?$"),173 (instregex "^(F|XS)(ABS|CPSGN|ADD|MUL|NABS|RE|NEG|SUB|SEL|RSQRTE)(D|S)?(P)?(s)?(_rec)?$"),174 (instregex "^FRI(M|N|P|Z)(D|S)(_rec)?$"),175 (instregex "^XSCVDP(S|U)X(W|D)S(s)?$"),176 (instregex "^XSCV(S|U)XD(D|S)P$"),177 (instregex "^XSCV(D|S)P(S|D)P(N)?$"),178 (instregex "^XSRDPI(C|M|P|Z)?$"),179 FMR, FRSP, FMR_rec, FRSP_rec, XSRSP)>;180 181 def : InstRW<[P8_FP_4x32_6C, P8_ISSUE_VSX], (instrs182 (instregex "^XV(N)?M(ADD|SUB)(A|M)SP$"),183 (instregex "^VRFI(M|N|P|Z)$"),184 XVRSQRTESP, XVSUBSP, VADDFP, VEXPTEFP, VLOGEFP, VMADDFP, VNMSUBFP, VREFP,185 VRSQRTEFP, VSUBFP, XVCVSXWSP, XVCVUXWSP, XVMULSP, XVNABSSP, XVNEGSP, XVRESP,186 XVCVDPSP, XVCVSXDSP, XVCVUXDSP, XVABSSP, XVADDSP, XVCPSGNSP)>;187 188 def : InstRW<[P8_FP_2x64_6C, P8_ISSUE_VSX], (instrs189 (instregex "^XVR(D|S)PI(C|M|P|Z)?$"),190 (instregex "^XVCV(S|U)X(D|W)DP$"),191 (instregex "^XVCV(D|W|S)P(S|U)X(D|W)S$"),192 (instregex "^XV(N)?(M)?(RSQRTE|CPSGN|SUB|ADD|ABS|UL|NEG|RE)(A|M)?DP$"),193 XVCVSPDP)>;194 195 // Instructions of FX, LU or LS pipeline196 197 def : InstRW<[P8_FX_NONE, P8_ISSUE_FX], (instrs TDI, TWI, TD, TW, MTCRF, MTCRF8, MTOCRF, MTOCRF8)>;198 def : InstRW<[P8_FX_1C, P8_ISSUE_FX], (instregex "^RLWIMI(8)?$")>;199 // TODO: Pipeline of logical instructions might be LS or FX200 def : InstRW<[P8_FX_2C, P8_ISSUE_FX], (instrs201 (instregex "^(N|X)?(EQV|AND|OR)(I)?(S|C)?(8)?(_rec)?$"),202 (instregex "^EXTS(B|H|W)(8)?(_32)?(_64)?(_rec)?$"),203 (instregex "^RL(D|W)(I)?(NM|C)(L|R)?(8)?(_32)?(_64)?(_rec)?$"),204 (instregex "^S(L|R)(A)?(W|D)(I)?(8)?(_rec|_32)?$"),205 (instregex "^(ADD|SUBF)(M|Z)?(C|E)?(4|8)?O(_rec)?$"),206 (instregex "^(ADD|SUBF)(M|Z)?E(8)?_rec$"),207 (instregex "^(ADD|SUBF|NEG)(4|8)?_rec$"),208 NOP, ADDG6S, ADDG6S8, ADDZE, ADDZE8, ADDIC_rec, NEGO_rec, ADDC, ADDC8, SUBFC, SUBFC8,209 ADDC_rec, ADDC8_rec, SUBFC_rec, SUBFC8_rec, COPY, NEG8O_rec,210 RLDIMI, RLDIMI_rec, RLWIMI8_rec, RLWIMI_rec)>;211 212 def : InstRW<[P8_FX_3C], (instregex "^(POP)?CNT(LZ)?(B|W|D)(8)?(_rec)?$")>;213 def : InstRW<[P8_FX_5C, P8_ISSUE_FX], (instrs214 (instregex "^MUL(H|L)(I|W|D)(8)?(U|O)?(_rec)?$"),215 CMPDI,CMPWI,CMPD,CMPW,CMPLDI,CMPLWI,CMPLD,CMPLW,216 ISEL, ISEL8, MTLR, MTLR8, MTCTR, MTCTR8, MTCTR8loop, MTCTRloop)>;217 218 def : InstRW<[P8_FX_10C, P8_ISSUE_VSX], (instregex "^MFTB(8)?$")>;219 def : InstRW<[P8_FX_15C, P8_ISSUE_FX], (instregex "^DIVW(U)?$")>;220 221 def : InstRW<[P8_FX_23C, P8_ISSUE_FX], (instregex "^DIV(D|WE)(U)?$")>;222 def : InstRW<[P8_FX_41C], (instrs223 (instregex "^DIV(D|W)(E)?(U)?O(_rec)?$"),224 (instregex "^DIV(D|W)(E)?(U)?_rec$"),225 DIVDE, DIVDEU)>;226 227 def : InstRW<[P8_LS_3C, P8_ISSUE_FX], (instrs MFSR, MFSRIN)>;228 229 def : InstRW<[P8_LU_5C, P8_ISSUE_LD], (instrs230 LFS, LFSX, LFD, LFDX, LFDXTLS, LFDXTLS_, LXVD2X, LXVW4X, LXVDSX, LVEBX, LVEHX, LVEWX,231 LVX, LVXL, LXSDX, LFIWAX, LFIWZX, LFSXTLS, LFSXTLS_, LXVB16X, LXVD2X, LXSIWZX,232 DFLOADf64, XFLOADf64, LIWZX)>;233 234 def : InstRW<[P8_LS_FX_3C, P8_ISSUE_FXLD], (instrs LQ)>;235 def : InstRW<[P8_LU_FX_5C, P8_ISSUE_LD], (instregex "^LF(D|S)U(X)?$")>;236 237 def : InstRW<[P8_LS_FP_NONE, P8_ISSUE_ST], (instrs238 STXSDX, STXVD2X, STXVW4X, STFIWX, STFS, STFSX, STFD, STFDX,239 STFDEPX, STFDXTLS, STFDXTLS_, STFSXTLS, STFSXTLS_, STXSIWX, STXSSP, STXSSPX)>;240 241 def : InstRW<[P8_LS_FP_FX_2C, P8_ISSUE_ST], (instrs STVEBX, STVEHX, STVEWX, STVX, STVXL)>;242 def : InstRW<[P8_LS_FP_FX_3C, P8_ISSUE_ST], (instregex "^STF(D|S)U(X)?$")>;243 244 def : InstRW<[P8_LS_LU_NONE, P8_ISSUE_ST], (instrs245 (instregex "^ST(B|H|W|D)(U)?(X)?(8|TLS)?(_)?(32)?$"),246 STBCIX, STBCX, STBEPX, STDBRX, STDCIX, STDCX, STHBRX, STHCIX, STHCX, STHEPX,247 STMW, STSWI, STWBRX, STWCIX, STWCX, STWEPX)>;248 249 def : InstRW<[P8_LU_or_LS_FX_3C, P8_ISSUE_FXLD],250 (instregex "^L(B|H|W|D)(A|Z)?(U)?(X)?(8|TLS)?(_)?(32)?$")>;251 252 def : InstRW<[P8_LU_or_LS_3C, P8_ISSUE_FXLD], (instrs253 LBARX, LBARXL, LBEPX, LBZCIX, LDARX, LDARXL, LDBRX, LDCIX, LFDEPX, LHARX, LHARXL, LHBRX, LXSIWAX,254 LHBRX8, LHEPX, LHZCIX, LMW, LSWI, LVSL, LVSR, LWARX, LWARXL, LWBRX, LWBRX8, LWEPX, LWZCIX)>;255 256 def : InstRW<[P8_LU_or_LS_or_FX_2C, P8_ISSUE_FX], (instrs257 (instregex "^ADDI(C)?(dtprel|tlsgd|toc)?(L)?(ADDR)?(32|8)?$"),258 (instregex "^ADDIS(dtprel|tlsgd|toc|gotTprel)?(HA)?(32|8)?$"),259 (instregex "^LI(S)?(8)?$"),260 (instregex "^ADD(M)?(E)?(4|8)?(TLS)?(_)?$"),261 (instregex "^SUBF(M|Z)?(E)?(IC)?(4|8)?$"),262 (instregex "^NEG(8)?(O)?$"))>;263 264 // Instructions of PM pipeline265 266 def : InstRW<[P8_PM_2C, P8_ISSUE_VSX], (instrs267 (instregex "^VPK(S|U)(H|W|D)(S|U)(M|S)$"),268 (instregex "^VUPK(H|L)(P|S)(H|B|W|X)$"),269 (instregex "^VSPLT(IS)?(B|H|W)(s)?$"),270 (instregex "^(XX|V)MRG(E|O|H|L)(B|H|W)$"),271 XXPERMDI, XXPERMDIs, XXSEL, XXSLDWI, XXSLDWIs, XXSPLTW, XXSPLTWs, VPERMXOR,272 VPKPX, VPERM, VBPERMQ, VGBBD, VSEL, VSL, VSLDOI, VSLO, VSR, VSRO)>;273 274 def : InstRW<[P8_XS_2C, P8_ISSUE_VSX], (instrs275 (instregex "^V(ADD|SUB)(S|U)(B|H|W|D)(M|S)$"),276 (instregex "^X(S|V)(MAX|MIN)(D|S)P$"),277 (instregex "^V(S)?(R)?(L)?(A)?(B|D|H|W)$"),278 (instregex "^VAVG(S|U)(B|H|W)$"),279 (instregex "^VM(AX|IN)(S|U)(B|H|W|D)$"),280 (instregex "^(XX|V)(L)?(N)?(X)?(AND|OR|EQV)(C)?$"),281 (instregex "^(X)?VCMP(EQ|GT|GE|B)(F|S|U)?(B|H|W|D|P|S)(P)?(_rec)?$"),282 (instregex "^VCLZ(B|H|W|D)$"),283 (instregex "^VPOPCNT(B|H|W)$"),284 XXLORf, XXLXORdpz, XXLXORspz, XXLXORz, VEQV, VMAXFP, VMINFP,285 VSHASIGMAD, VSHASIGMAW, VSUBCUW, VADDCUW, MFVSCR, MTVSCR)>;286 287 def : InstRW<[P8_XS_4C, P8_ISSUE_VSX], (instrs288 (instregex "^V(ADD|SUB)(E)?(C)?UQ(M)?$"),289 VPOPCNTD)>;290 291 def : InstRW<[P8_XS_9C, P8_ISSUE_CR], (instrs292 (instregex "^(F|XS)CMP(O|U)(D|S)(P)?$"),293 (instregex "^(F|XS|XV)T(DIV|SQRT)((D|S)P)?$"))>;294 295 // Instructions of VX pipeline296 297 def : InstRW<[P8_VX_7C, P8_ISSUE_VSX], (instrs298 (instregex "^V(M)?SUM(2|4)?(M|S|U)(B|H|W)(M|S)$"),299 (instregex "^VMUL(E|O)?(S|U)(B|H|W)(M)?$"),300 VMHADDSHS, VMHRADDSHS, VMLADDUHM)>;301 302 // Instructions of BR pipeline303 304 def : InstRW<[P8_BR_2C, P8_ISSUE_BR], (instrs305 (instregex "^(g)?B(C)?(C)?(CTR)?(L)?(A)?(R)?(L)?(8)?(_LD|_LWZ)?(always|into_toc|at)?(_RM)?(n)?$"),306 (instregex "^BD(N)?Z(L)?(R|A)?(L)?(m|p|8)?$"),307 (instregex "^BL(R|A)?(8)?(_NOP)?(_TLS)?(_)?(RM)?$"))>;308 309 // Instructions of DFP pipeline310 // DFP operations also use float/vector/crypto issue ports.311 def : InstRW<[P8_DFU_13C, P8_ISSUE_VSX], (instrs312 (instregex "^DTST(D|S)(C|F|G)(Q)?$"),313 (instregex "^D(Q|X)EX(Q)?(_rec)?$"),314 (instregex "^D(ADD|SUB|IEX|QUA|RRND|RINTX|RINTN|CTDP|DEDPD|ENBCD)(_rec)?$"),315 (instregex "^DSC(L|R)I(_rec)?$"),316 BCDADD_rec, BCDSUB_rec, DCMPO, DCMPU, DTSTEX, DQUAI)>;317 318 def : InstRW<[P8_DFU_15C, P8_ISSUE_VSX], (instrs319 (instregex "^DRINT(N|X)Q(_rec)?$"),320 DCMPOQ, DCMPUQ, DRRNDQ, DRRNDQ_rec, DIEXQ, DIEXQ_rec, DQUAIQ, DQUAIQ_rec,321 DTSTEXQ, DDEDPDQ, DDEDPDQ_rec, DENBCDQ, DENBCDQ_rec, DSCLIQ, DSCLIQ_rec,322 DSCRIQ, DSCRIQ_rec, DCTQPQ, DCTQPQ_rec)>;323 324 def : InstRW<[P8_DFU_17C, P8_ISSUE_VSX], (instregex "^D(ADD|SUB|QUA)Q(_rec)?$")>;325 def : InstRW<[P8_DFU_25C, P8_ISSUE_VSX], (instrs DRSP, DRSP_rec, DCTFIX, DCTFIX_rec)>;326 def : InstRW<[P8_DFU_32C, P8_ISSUE_VSX], (instrs DCFFIX, DCFFIX_rec)>;327 def : InstRW<[P8_DFU_34C, P8_ISSUE_VSX], (instrs DCFFIXQ, DCFFIXQ_rec)>;328 def : InstRW<[P8_DFU_40C, P8_ISSUE_VSX], (instrs DMUL, DMUL_rec)>;329 def : InstRW<[P8_DFU_90C, P8_ISSUE_VSX], (instrs DMULQ, DMULQ_rec)>;330 def : InstRW<[P8_DFU_96C, P8_ISSUE_VSX], (instrs DDIV, DDIV_rec)>;331 def : InstRW<[P8_DFU_172C, P8_ISSUE_VSX], (instrs DDIVQ, DDIVQ_rec)>;332 333 // Direct move instructions334 335 def : InstRW<[P8_DM_5C, P8_ISSUE_VSX], (instrs336 MFVRD, MFVSRD, MFVRWZ, MFVSRWZ, MTVRD, MTVSRD, MTVRWA, MTVSRWA, MTVRWZ, MTVSRWZ)>;337}338