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1add_llvm_component_group(RISCV)2 3set(LLVM_TARGET_DEFINITIONS RISCV.td)4 5tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)6tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)7tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)8tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)9tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)10tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler11 --specialize-decoders-per-bitwidth)12tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)13tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)14tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)15tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)16tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)17tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)18tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)19tablegen(LLVM RISCVGenExegesis.inc -gen-exegesis)20tablegen(LLVM RISCVGenSDNodeInfo.inc -gen-sd-node-info)21 22set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)23tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)24tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner25 -combiners="RISCVO0PreLegalizerCombiner")26tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner27 -combiners="RISCVPreLegalizerCombiner")28tablegen(LLVM RISCVGenPostLegalizeGICombiner.inc -gen-global-isel-combiner29 -combiners="RISCVPostLegalizerCombiner")30 31add_public_tablegen_target(RISCVCommonTableGen)32 33add_llvm_target(RISCVCodeGen34 RISCVAsmPrinter.cpp35 RISCVCallingConv.cpp36 RISCVCodeGenPrepare.cpp37 RISCVConstantPoolValue.cpp38 RISCVDeadRegisterDefinitions.cpp39 RISCVExpandAtomicPseudoInsts.cpp40 RISCVExpandPseudoInsts.cpp41 RISCVFoldMemOffset.cpp42 RISCVFrameLowering.cpp43 RISCVGatherScatterLowering.cpp44 RISCVIndirectBranchTracking.cpp45 RISCVInsertReadWriteCSR.cpp46 RISCVInsertVSETVLI.cpp47 RISCVInsertWriteVXRM.cpp48 RISCVInstrInfo.cpp49 RISCVInterleavedAccess.cpp50 RISCVISelDAGToDAG.cpp51 RISCVISelLowering.cpp52 RISCVLandingPadSetup.cpp53 RISCVLateBranchOpt.cpp54 RISCVLoadStoreOptimizer.cpp55 RISCVMachineFunctionInfo.cpp56 RISCVMakeCompressible.cpp57 RISCVMergeBaseOffset.cpp58 RISCVMoveMerger.cpp59 RISCVOptWInstrs.cpp60 RISCVPostRAExpandPseudoInsts.cpp61 RISCVPromoteConstant.cpp62 RISCVPushPopOptimizer.cpp63 RISCVRedundantCopyElimination.cpp64 RISCVRegisterInfo.cpp65 RISCVSelectionDAGInfo.cpp66 RISCVSubtarget.cpp67 RISCVTargetMachine.cpp68 RISCVTargetObjectFile.cpp69 RISCVTargetTransformInfo.cpp70 RISCVVectorMaskDAGMutation.cpp71 RISCVVectorPeephole.cpp72 RISCVVLOptimizer.cpp73 RISCVVMV0Elimination.cpp74 RISCVZacasABIFix.cpp75 RISCVZilsdOptimizer.cpp76 GISel/RISCVCallLowering.cpp77 GISel/RISCVInstructionSelector.cpp78 GISel/RISCVLegalizerInfo.cpp79 GISel/RISCVPostLegalizerCombiner.cpp80 GISel/RISCVO0PreLegalizerCombiner.cpp81 GISel/RISCVPreLegalizerCombiner.cpp82 GISel/RISCVRegisterBankInfo.cpp83 84 LINK_COMPONENTS85 Analysis86 AsmPrinter87 CodeGen88 CodeGenTypes89 Core90 GlobalISel91 IPO92 MC93 Passes94 RISCVDesc95 RISCVInfo96 Scalar97 SelectionDAG98 Support99 Target100 TargetParser101 TransformUtils102 Vectorize103 104 ADD_TO_COMPONENT105 RISCV106 )107 108add_subdirectory(AsmParser)109add_subdirectory(Disassembler)110add_subdirectory(MCTargetDesc)111add_subdirectory(MCA)112add_subdirectory(TargetInfo)113