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1//===-- RISCVRegisterBankInfo.h ---------------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8/// \file9/// This file declares the targeting of the RegisterBankInfo class for RISC-V.10/// \todo This should be generated by TableGen.11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H15 16#include "llvm/CodeGen/RegisterBankInfo.h"17 18#define GET_REGBANK_DECLARATIONS19#include "RISCVGenRegisterBank.inc"20 21namespace llvm {22 23class TargetRegisterInfo;24 25class RISCVGenRegisterBankInfo : public RegisterBankInfo {26protected:27#define GET_TARGET_REGBANK_CLASS28#include "RISCVGenRegisterBank.inc"29};30 31/// This class provides the information for the target register banks.32class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {33public:34 RISCVRegisterBankInfo(unsigned HwMode);35 36 const InstructionMapping &37 getInstrMapping(const MachineInstr &MI) const override;38 39private:40 /// \returns true if \p MI only uses and defines FPRs.41 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,42 const TargetRegisterInfo &TRI) const;43 44 /// \returns true if \p MI only uses FPRs.45 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,46 const TargetRegisterInfo &TRI) const;47 48 /// \returns true if any use of \p Def only user FPRs.49 bool anyUseOnlyUseFP(Register Def, const MachineRegisterInfo &MRI,50 const TargetRegisterInfo &TRI) const;51 52 /// \returns true if \p MI only defines FPRs.53 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,54 const TargetRegisterInfo &TRI) const;55};56} // end namespace llvm57#endif58