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1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains small standalone enum definitions for the RISC-V target10// useful for the compiler back-end and the MC libraries.11//12//===----------------------------------------------------------------------===//13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H15 16#include "MCTargetDesc/RISCVMCTargetDesc.h"17#include "llvm/ADT/APFloat.h"18#include "llvm/ADT/APInt.h"19#include "llvm/ADT/StringRef.h"20#include "llvm/ADT/StringSwitch.h"21#include "llvm/MC/MCInstrDesc.h"22#include "llvm/TargetParser/RISCVISAInfo.h"23#include "llvm/TargetParser/RISCVTargetParser.h"24#include "llvm/TargetParser/SubtargetFeature.h"25 26namespace llvm {27 28// RISCVII - This namespace holds all of the target specific flags that29// instruction info tracks. All definitions must match RISCVInstrFormats.td.30namespace RISCVII {31enum {32 InstFormatPseudo = 0,33 InstFormatR = 1,34 InstFormatR4 = 2,35 InstFormatI = 3,36 InstFormatS = 4,37 InstFormatB = 5,38 InstFormatU = 6,39 InstFormatJ = 7,40 InstFormatCR = 8,41 InstFormatCI = 9,42 InstFormatCSS = 10,43 InstFormatCIW = 11,44 InstFormatCL = 12,45 InstFormatCS = 13,46 InstFormatCA = 14,47 InstFormatCB = 15,48 InstFormatCJ = 16,49 InstFormatCU = 17,50 InstFormatCLB = 18,51 InstFormatCLH = 19,52 InstFormatCSB = 20,53 InstFormatCSH = 21,54 InstFormatQC_EAI = 22,55 InstFormatQC_EI = 23,56 InstFormatQC_EB = 24,57 InstFormatQC_EJ = 25,58 InstFormatQC_ES = 26,59 InstFormatNDS_BRANCH_10 = 27,60 InstFormatOther = 31,61 62 InstFormatMask = 31,63 InstFormatShift = 0,64 65 ConstraintShift = InstFormatShift + 5,66 VS2Constraint = 0b001 << ConstraintShift,67 VS1Constraint = 0b010 << ConstraintShift,68 VMConstraint = 0b100 << ConstraintShift,69 ConstraintMask = 0b111 << ConstraintShift,70 71 VLMulShift = ConstraintShift + 3,72 VLMulMask = 0b111 << VLMulShift,73 74 // Is this a _TIED vector pseudo instruction. For these instructions we75 // shouldn't skip the tied operand when converting to MC instructions.76 IsTiedPseudoShift = VLMulShift + 3,77 IsTiedPseudoMask = 1 << IsTiedPseudoShift,78 79 // Does this instruction have a SEW operand. It will be the last explicit80 // operand unless there is a vector policy operand. Used by RVV Pseudos.81 HasSEWOpShift = IsTiedPseudoShift + 1,82 HasSEWOpMask = 1 << HasSEWOpShift,83 84 // Does this instruction have a VL operand. It will be the second to last85 // explicit operand unless there is a vector policy operand. Used by RVV86 // Pseudos.87 HasVLOpShift = HasSEWOpShift + 1,88 HasVLOpMask = 1 << HasVLOpShift,89 90 // Does this instruction have a vector policy operand. It will be the last91 // explicit operand. Used by RVV Pseudos.92 HasVecPolicyOpShift = HasVLOpShift + 1,93 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,94 95 // Is this instruction a vector widening reduction instruction. Used by RVV96 // Pseudos.97 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,98 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,99 100 // Does this instruction care about mask policy. If it is not, the mask policy101 // could be either agnostic or undisturbed. For example, unmasked, store, and102 // reduction operations result would not be affected by mask policy, so103 // compiler has free to select either one.104 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,105 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,106 107 // Indicates that the result can be considered sign extended from bit 31. Some108 // instructions with this flag aren't W instructions, but are either sign109 // extended from a smaller size, always outputs a small integer, or put zeros110 // in bits 63:31. Used by the SExtWRemoval pass.111 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,112 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,113 114 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,115 HasRoundModeOpMask = 1 << HasRoundModeOpShift,116 117 UsesVXRMShift = HasRoundModeOpShift + 1,118 UsesVXRMMask = 1 << UsesVXRMShift,119 120 // Indicates whether these instructions can partially overlap between source121 // registers and destination registers according to the vector spec.122 // 0 -> not a vector pseudo123 // 1 -> default value for vector pseudos. not widening or narrowing.124 // 2 -> narrowing case125 // 3 -> widening case126 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,127 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,128 129 ElementsDependOnVLShift = TargetOverlapConstraintTypeShift + 2,130 ElementsDependOnVLMask = 1ULL << ElementsDependOnVLShift,131 132 ElementsDependOnMaskShift = ElementsDependOnVLShift + 1,133 ElementsDependOnMaskMask = 1ULL << ElementsDependOnMaskShift,134 135 // Indicates the EEW of a vector instruction's destination operand.136 // 0 -> 1137 // 1 -> SEW138 // 2 -> SEW * 2139 // 3 -> SEW * 4140 DestEEWShift = ElementsDependOnMaskShift + 1,141 DestEEWMask = 3ULL << DestEEWShift,142 143 ReadsPastVLShift = DestEEWShift + 2,144 ReadsPastVLMask = 1ULL << ReadsPastVLShift,145 146 // 0 -> Don't care about altfmt bit in VTYPE.147 // 1 -> Is not altfmt.148 // 2 -> Is altfmt(BF16).149 AltFmtTypeShift = ReadsPastVLShift + 1,150 AltFmtTypeMask = 3ULL << AltFmtTypeShift,151 152 // XSfmmbase153 HasTWidenOpShift = AltFmtTypeShift + 2,154 HasTWidenOpMask = 1ULL << HasTWidenOpShift,155 156 HasTMOpShift = HasTWidenOpShift + 1,157 HasTMOpMask = 1ULL << HasTMOpShift,158 159 HasTKOpShift = HasTMOpShift + 1,160 HasTKOpMask = 1ULL << HasTKOpShift,161};162 163// Helper functions to read TSFlags.164/// \returns the format of the instruction.165static inline unsigned getFormat(uint64_t TSFlags) {166 return (TSFlags & InstFormatMask) >> InstFormatShift;167}168/// \returns the LMUL for the instruction.169static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {170 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);171}172/// \returns true if this a _TIED pseudo.173static inline bool isTiedPseudo(uint64_t TSFlags) {174 return TSFlags & IsTiedPseudoMask;175}176/// \returns true if there is a SEW operand for the instruction.177static inline bool hasSEWOp(uint64_t TSFlags) {178 return TSFlags & HasSEWOpMask;179}180/// \returns true if there is a VL operand for the instruction.181static inline bool hasVLOp(uint64_t TSFlags) {182 return TSFlags & HasVLOpMask;183}184/// \returns true if there is a vector policy operand for this instruction.185static inline bool hasVecPolicyOp(uint64_t TSFlags) {186 return TSFlags & HasVecPolicyOpMask;187}188/// \returns true if it is a vector widening reduction instruction.189static inline bool isRVVWideningReduction(uint64_t TSFlags) {190 return TSFlags & IsRVVWideningReductionMask;191}192/// \returns true if mask policy is valid for the instruction.193static inline bool usesMaskPolicy(uint64_t TSFlags) {194 return TSFlags & UsesMaskPolicyMask;195}196 197/// \returns true if there is a rounding mode operand for this instruction198static inline bool hasRoundModeOp(uint64_t TSFlags) {199 return TSFlags & HasRoundModeOpMask;200}201 202enum class AltFmtType { DontCare, NotAltFmt, AltFmt };203static inline AltFmtType getAltFmtType(uint64_t TSFlags) {204 return static_cast<AltFmtType>((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift);205}206 207/// \returns true if this instruction uses vxrm208static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }209 210/// \returns true if the elements in the body are affected by VL,211/// e.g. vslide1down.vx/vredsum.vs/viota.m212static inline bool elementsDependOnVL(uint64_t TSFlags) {213 return TSFlags & ElementsDependOnVLMask;214}215 216/// \returns true if the elements in the body are affected by the mask,217/// e.g. vredsum.vs/viota.m218static inline bool elementsDependOnMask(uint64_t TSFlags) {219 return TSFlags & ElementsDependOnMaskMask;220}221 222/// \returns true if the instruction may read elements past VL, e.g.223/// vslidedown/vrgather224static inline bool readsPastVL(uint64_t TSFlags) {225 return TSFlags & ReadsPastVLMask;226}227 228// XSfmmbase229static inline bool hasTWidenOp(uint64_t TSFlags) {230 return TSFlags & HasTWidenOpMask;231}232 233static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; }234 235static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; }236 237static inline unsigned getTNOpNum(const MCInstrDesc &Desc) {238 const uint64_t TSFlags = Desc.TSFlags;239 assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags));240 unsigned Offset = 3;241 if (hasTKOp(TSFlags))242 Offset = 4;243 return Desc.getNumOperands() - Offset;244}245 246static inline unsigned getTMOpNum(const MCInstrDesc &Desc) {247 const uint64_t TSFlags = Desc.TSFlags;248 assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags));249 if (hasTKOp(TSFlags))250 return Desc.getNumOperands() - 5;251 // vtzero.t252 return Desc.getNumOperands() - 4;253}254 255static inline unsigned getTKOpNum(const MCInstrDesc &Desc) {256 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;257 assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags));258 return Desc.getNumOperands() - 3;259}260 261static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {262 const uint64_t TSFlags = Desc.TSFlags;263 // This method is only called if we expect to have a VL operand, and all264 // instructions with VL also have SEW.265 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));266 // In Xsfmmbase, TN is an alias for VL, so here we use the same TSFlags bit.267 if (hasTWidenOp(TSFlags))268 return getTNOpNum(Desc);269 unsigned Offset = 2;270 if (hasVecPolicyOp(TSFlags))271 Offset = 3;272 return Desc.getNumOperands() - Offset;273}274 275static inline MCRegister276getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {277 // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.278 // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.279 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;280}281 282static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {283 const uint64_t TSFlags = Desc.TSFlags;284 assert(hasSEWOp(TSFlags));285 unsigned Offset = 1;286 if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags))287 Offset = 2;288 return Desc.getNumOperands() - Offset;289}290 291static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {292 assert(hasVecPolicyOp(Desc.TSFlags));293 return Desc.getNumOperands() - 1;294}295 296/// \returns the index to the rounding mode immediate value if any, otherwise297/// returns -1.298static inline int getFRMOpNum(const MCInstrDesc &Desc) {299 const uint64_t TSFlags = Desc.TSFlags;300 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))301 return -1;302 303 if (hasTWidenOp(TSFlags) && hasTMOp(TSFlags))304 return getTMOpNum(Desc) - 1;305 306 // The operand order307 // --------------------------------------308 // | n-1 (if any) | n-2 | n-3 | n-4 |309 // | policy | sew | vl | frm |310 // --------------------------------------311 return getVLOpNum(Desc) - 1;312}313 314/// \returns the index to the rounding mode immediate value if any, otherwise315/// returns -1.316static inline int getVXRMOpNum(const MCInstrDesc &Desc) {317 const uint64_t TSFlags = Desc.TSFlags;318 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))319 return -1;320 // The operand order321 // --------------------------------------322 // | n-1 (if any) | n-2 | n-3 | n-4 |323 // | policy | sew | vl | vxrm |324 // --------------------------------------325 return getVLOpNum(Desc) - 1;326}327 328// Is the first def operand tied to the first use operand. This is true for329// vector pseudo instructions that have a merge operand for tail/mask330// undisturbed. It's also true for vector FMA instructions where one of the331// operands is also the destination register.332static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {333 return Desc.getNumDefs() < Desc.getNumOperands() &&334 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;335}336 337// RISC-V Specific Machine Operand Flags338enum {339 MO_None = 0,340 MO_CALL = 1,341 MO_LO = 3,342 MO_HI = 4,343 MO_PCREL_LO = 5,344 MO_PCREL_HI = 6,345 MO_GOT_HI = 7,346 MO_TPREL_LO = 8,347 MO_TPREL_HI = 9,348 MO_TPREL_ADD = 10,349 MO_TLS_GOT_HI = 11,350 MO_TLS_GD_HI = 12,351 MO_TLSDESC_HI = 13,352 MO_TLSDESC_LOAD_LO = 14,353 MO_TLSDESC_ADD_LO = 15,354 MO_TLSDESC_CALL = 16,355 356 // Used to differentiate between target-specific "direct" flags and "bitmask"357 // flags. A machine operand can only have one "direct" flag, but can have358 // multiple "bitmask" flags.359 MO_DIRECT_FLAG_MASK = 31360};361} // namespace RISCVII362 363namespace RISCVOp {364enum OperandType : unsigned {365 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,366 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,367 OPERAND_UIMM2,368 OPERAND_UIMM2_LSB0,369 OPERAND_UIMM3,370 OPERAND_UIMM4,371 OPERAND_UIMM5,372 OPERAND_UIMM5_NONZERO,373 OPERAND_UIMM5_GT3,374 OPERAND_UIMM5_PLUS1,375 OPERAND_UIMM5_GE6_PLUS1,376 OPERAND_UIMM5_LSB0,377 OPERAND_UIMM5_SLIST,378 OPERAND_UIMM6,379 OPERAND_UIMM6_LSB0,380 OPERAND_UIMM7,381 OPERAND_UIMM7_LSB00,382 OPERAND_UIMM7_LSB000,383 OPERAND_UIMM8_LSB00,384 OPERAND_UIMM8,385 OPERAND_UIMM8_LSB000,386 OPERAND_UIMM8_GE32,387 OPERAND_UIMM9_LSB000,388 OPERAND_UIMM9,389 OPERAND_UIMM10,390 OPERAND_UIMM10_LSB00_NONZERO,391 OPERAND_UIMM11,392 OPERAND_UIMM12,393 OPERAND_UIMM14_LSB00,394 OPERAND_UIMM16,395 OPERAND_UIMM16_NONZERO,396 OPERAND_UIMM20,397 OPERAND_UIMMLOG2XLEN,398 OPERAND_UIMMLOG2XLEN_NONZERO,399 OPERAND_UIMM32,400 OPERAND_UIMM48,401 OPERAND_UIMM64,402 OPERAND_THREE,403 OPERAND_FOUR,404 OPERAND_IMM5_ZIBI,405 OPERAND_SIMM5,406 OPERAND_SIMM5_NONZERO,407 OPERAND_SIMM5_PLUS1,408 OPERAND_SIMM6,409 OPERAND_SIMM6_NONZERO,410 OPERAND_SIMM8_UNSIGNED,411 OPERAND_SIMM10,412 OPERAND_SIMM10_LSB0000_NONZERO,413 OPERAND_SIMM10_UNSIGNED,414 OPERAND_SIMM11,415 OPERAND_SIMM12,416 OPERAND_SIMM12_LSB00000,417 OPERAND_SIMM16,418 OPERAND_SIMM16_NONZERO,419 OPERAND_SIMM20_LI,420 OPERAND_SIMM26,421 OPERAND_BARE_SIMM32,422 OPERAND_CLUI_IMM,423 OPERAND_VTYPEI10,424 OPERAND_VTYPEI11,425 OPERAND_RVKRNUM,426 OPERAND_RVKRNUM_0_7,427 OPERAND_RVKRNUM_1_10,428 OPERAND_RVKRNUM_2_14,429 OPERAND_RLIST,430 OPERAND_RLIST_S0,431 OPERAND_STACKADJ,432 // Operand is a 3-bit rounding mode, '111' indicates FRM register.433 // Represents 'frm' argument passing to floating-point operations.434 OPERAND_FRMARG,435 // Operand is a 3-bit rounding mode where only RTZ is valid.436 OPERAND_RTZARG,437 // Condition code used by select and short forward branch pseudos.438 OPERAND_COND_CODE,439 // Vector policy operand.440 OPERAND_VEC_POLICY,441 // Vector SEW operand. Stores in log2(SEW).442 OPERAND_SEW,443 // Special SEW for mask only instructions. Always 0.444 OPERAND_SEW_MASK,445 // Vector rounding mode for VXRM or FRM.446 OPERAND_VEC_RM,447 // Vtype operand for XSfmm extension.448 OPERAND_XSFMM_VTYPE,449 OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_VTYPE,450 // Operand is either a register or uimm5, this is used by V extension pseudo451 // instructions to represent a value that be passed as AVL to either vsetvli452 // or vsetivli.453 OPERAND_AVL,454};455} // namespace RISCVOp456 457// Describes the predecessor/successor bits used in the FENCE instruction.458namespace RISCVFenceField {459enum FenceField {460 I = 8,461 O = 4,462 R = 2,463 W = 1464};465}466 467// Describes the supported floating point rounding mode encodings.468namespace RISCVFPRndMode {469enum RoundingMode {470 RNE = 0,471 RTZ = 1,472 RDN = 2,473 RUP = 3,474 RMM = 4,475 DYN = 7,476 Invalid477};478 479inline static StringRef roundingModeToString(RoundingMode RndMode) {480 switch (RndMode) {481 default:482 llvm_unreachable("Unknown floating point rounding mode");483 case RISCVFPRndMode::RNE:484 return "rne";485 case RISCVFPRndMode::RTZ:486 return "rtz";487 case RISCVFPRndMode::RDN:488 return "rdn";489 case RISCVFPRndMode::RUP:490 return "rup";491 case RISCVFPRndMode::RMM:492 return "rmm";493 case RISCVFPRndMode::DYN:494 return "dyn";495 }496}497 498inline static RoundingMode stringToRoundingMode(StringRef Str) {499 return StringSwitch<RoundingMode>(Str)500 .Case("rne", RISCVFPRndMode::RNE)501 .Case("rtz", RISCVFPRndMode::RTZ)502 .Case("rdn", RISCVFPRndMode::RDN)503 .Case("rup", RISCVFPRndMode::RUP)504 .Case("rmm", RISCVFPRndMode::RMM)505 .Case("dyn", RISCVFPRndMode::DYN)506 .Default(RISCVFPRndMode::Invalid);507}508 509inline static bool isValidRoundingMode(unsigned Mode) {510 switch (Mode) {511 default:512 return false;513 case RISCVFPRndMode::RNE:514 case RISCVFPRndMode::RTZ:515 case RISCVFPRndMode::RDN:516 case RISCVFPRndMode::RUP:517 case RISCVFPRndMode::RMM:518 case RISCVFPRndMode::DYN:519 return true;520 }521}522} // namespace RISCVFPRndMode523 524namespace RISCVVXRndMode {525enum RoundingMode {526 RNU = 0,527 RNE = 1,528 RDN = 2,529 ROD = 3,530 Invalid531};532 533inline static StringRef roundingModeToString(RoundingMode RndMode) {534 switch (RndMode) {535 default:536 llvm_unreachable("Unknown vector fixed-point rounding mode");537 case RISCVVXRndMode::RNU:538 return "rnu";539 case RISCVVXRndMode::RNE:540 return "rne";541 case RISCVVXRndMode::RDN:542 return "rdn";543 case RISCVVXRndMode::ROD:544 return "rod";545 }546}547 548inline static RoundingMode stringToRoundingMode(StringRef Str) {549 return StringSwitch<RoundingMode>(Str)550 .Case("rnu", RISCVVXRndMode::RNU)551 .Case("rne", RISCVVXRndMode::RNE)552 .Case("rdn", RISCVVXRndMode::RDN)553 .Case("rod", RISCVVXRndMode::ROD)554 .Default(RISCVVXRndMode::Invalid);555}556 557inline static bool isValidRoundingMode(unsigned Mode) {558 switch (Mode) {559 default:560 return false;561 case RISCVVXRndMode::RNU:562 case RISCVVXRndMode::RNE:563 case RISCVVXRndMode::RDN:564 case RISCVVXRndMode::ROD:565 return true;566 }567}568} // namespace RISCVVXRndMode569 570namespace RISCVExceptFlags {571enum ExceptionFlag {572 NX = 0x01, // Inexact573 UF = 0x02, // Underflow574 OF = 0x04, // Overflow575 DZ = 0x08, // Divide by zero576 NV = 0x10, // Invalid operation577 ALL = 0x1F // Mask for all accrued exception flags578};579}580 581//===----------------------------------------------------------------------===//582// Floating-point Immediates583//584 585namespace RISCVLoadFPImm {586float getFPImm(unsigned Imm);587 588/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point589/// immediate value. If the value cannot be represented as a 5-bit binary590/// encoding, then return -1.591int getLoadFPImm(APFloat FPImm);592} // namespace RISCVLoadFPImm593 594namespace RISCVSysReg {595struct SysReg {596 const char Name[32];597 unsigned Encoding;598 // FIXME: add these additional fields when needed.599 // Privilege Access: Read, Write, Read-Only.600 // unsigned ReadWrite;601 // Privilege Mode: User, System or Machine.602 // unsigned Mode;603 // Check field name.604 // unsigned Extra;605 // Register number without the privilege bits.606 // unsigned Number;607 FeatureBitset FeaturesRequired;608 bool IsRV32Only;609 bool IsAltName;610 bool IsDeprecatedName;611 612 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {613 // Not in 32-bit mode.614 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])615 return false;616 // No required feature associated with the system register.617 if (FeaturesRequired.none())618 return true;619 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;620 }621};622 623#define GET_SysRegEncodings_DECL624#define GET_SysRegsList_DECL625#include "RISCVGenSearchableTables.inc"626} // end namespace RISCVSysReg627 628namespace RISCVInsnOpcode {629struct RISCVOpcode {630 char Name[10];631 uint8_t Value;632};633 634#define GET_RISCVOpcodesList_DECL635#include "RISCVGenSearchableTables.inc"636} // end namespace RISCVInsnOpcode637 638namespace RISCVABI {639 640enum ABI {641 ABI_ILP32,642 ABI_ILP32F,643 ABI_ILP32D,644 ABI_ILP32E,645 ABI_LP64,646 ABI_LP64F,647 ABI_LP64D,648 ABI_LP64E,649 ABI_Unknown650};651 652// Returns the target ABI, or else a StringError if the requested ABIName is653// not supported for the given TT and FeatureBits combination.654ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,655 StringRef ABIName);656 657ABI getTargetABI(StringRef ABIName);658 659// Returns the register used to hold the stack pointer after realignment.660MCRegister getBPReg();661 662// Returns the register holding shadow call stack pointer.663MCRegister getSCSPReg();664 665} // namespace RISCVABI666 667namespace RISCVFeatures {668 669// Validates if the given combination of features are valid for the target670// triple. Exits with report_fatal_error if not.671void validate(const Triple &TT, const FeatureBitset &FeatureBits);672 673llvm::Expected<std::unique_ptr<RISCVISAInfo>>674parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);675 676} // namespace RISCVFeatures677 678namespace RISCVRVC {679bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);680bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);681} // namespace RISCVRVC682 683namespace RISCVZC {684enum RLISTENCODE {685 RA = 4,686 RA_S0,687 RA_S0_S1,688 RA_S0_S2,689 RA_S0_S3,690 RA_S0_S4,691 RA_S0_S5,692 RA_S0_S6,693 RA_S0_S7,694 RA_S0_S8,695 RA_S0_S9,696 // note - to include s10, s11 must also be included697 RA_S0_S11,698 INVALID_RLIST,699};700 701inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {702 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");703 switch (EndReg.id()) {704 case RISCV::X1:705 return RLISTENCODE::RA;706 case RISCV::X8:707 return RLISTENCODE::RA_S0;708 case RISCV::X9:709 return RLISTENCODE::RA_S0_S1;710 case RISCV::X18:711 return RLISTENCODE::RA_S0_S2;712 case RISCV::X19:713 return RLISTENCODE::RA_S0_S3;714 case RISCV::X20:715 return RLISTENCODE::RA_S0_S4;716 case RISCV::X21:717 return RLISTENCODE::RA_S0_S5;718 case RISCV::X22:719 return RLISTENCODE::RA_S0_S6;720 case RISCV::X23:721 return RLISTENCODE::RA_S0_S7;722 case RISCV::X24:723 return RLISTENCODE::RA_S0_S8;724 case RISCV::X25:725 return RLISTENCODE::RA_S0_S9;726 case RISCV::X27:727 return RLISTENCODE::RA_S0_S11;728 default:729 llvm_unreachable("Undefined input.");730 }731}732 733inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {734 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&735 "Unexpected number of registers");736 if (NumRegs == 13)737 return RLISTENCODE::RA_S0_S11;738 739 return RLISTENCODE::RA + (NumRegs - 1);740}741 742inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {743 assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&744 "Invalid Rlist");745 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;746 // s10 and s11 are saved together.747 if (RlistVal == RLISTENCODE::RA_S0_S11)748 ++NumRegs;749 750 unsigned RegSize = IsRV64 ? 8 : 4;751 return alignTo(NumRegs * RegSize, 16);752}753 754void printRegList(unsigned RlistEncode, raw_ostream &OS);755} // namespace RISCVZC756 757namespace RISCVVInversePseudosTable {758struct PseudoInfo {759 uint16_t Pseudo;760 uint16_t BaseInstr;761 uint8_t VLMul;762 uint8_t SEW;763};764 765#define GET_RISCVVInversePseudosTable_DECL766#include "RISCVGenSearchableTables.inc"767} // namespace RISCVVInversePseudosTable768 769namespace RISCV {770struct VLSEGPseudo {771 uint16_t NF : 4;772 uint16_t Masked : 1;773 uint16_t Strided : 1;774 uint16_t FF : 1;775 uint16_t Log2SEW : 3;776 uint16_t LMUL : 3;777 uint16_t Pseudo;778};779 780struct VLXSEGPseudo {781 uint16_t NF : 4;782 uint16_t Masked : 1;783 uint16_t Ordered : 1;784 uint16_t Log2SEW : 3;785 uint16_t LMUL : 3;786 uint16_t IndexLMUL : 3;787 uint16_t Pseudo;788};789 790struct VSSEGPseudo {791 uint16_t NF : 4;792 uint16_t Masked : 1;793 uint16_t Strided : 1;794 uint16_t Log2SEW : 3;795 uint16_t LMUL : 3;796 uint16_t Pseudo;797};798 799struct VSXSEGPseudo {800 uint16_t NF : 4;801 uint16_t Masked : 1;802 uint16_t Ordered : 1;803 uint16_t Log2SEW : 3;804 uint16_t LMUL : 3;805 uint16_t IndexLMUL : 3;806 uint16_t Pseudo;807};808 809struct VLEPseudo {810 uint16_t Masked : 1;811 uint16_t Strided : 1;812 uint16_t FF : 1;813 uint16_t Log2SEW : 3;814 uint16_t LMUL : 3;815 uint16_t Pseudo;816};817 818struct VSEPseudo {819 uint16_t Masked : 1;820 uint16_t Strided : 1;821 uint16_t Log2SEW : 3;822 uint16_t LMUL : 3;823 uint16_t Pseudo;824};825 826struct VLX_VSXPseudo {827 uint16_t Masked : 1;828 uint16_t Ordered : 1;829 uint16_t Log2SEW : 3;830 uint16_t LMUL : 3;831 uint16_t IndexLMUL : 3;832 uint16_t Pseudo;833};834 835struct NDSVLNPseudo {836 uint16_t Masked : 1;837 uint16_t Unsigned : 1;838 uint16_t Log2SEW : 3;839 uint16_t LMUL : 3;840 uint16_t Pseudo;841};842 843#define GET_RISCVVSSEGTable_DECL844#define GET_RISCVVLSEGTable_DECL845#define GET_RISCVVLXSEGTable_DECL846#define GET_RISCVVSXSEGTable_DECL847#define GET_RISCVVLETable_DECL848#define GET_RISCVVSETable_DECL849#define GET_RISCVVLXTable_DECL850#define GET_RISCVVSXTable_DECL851#define GET_RISCVNDSVLNTable_DECL852#include "RISCVGenSearchableTables.inc"853} // namespace RISCV854 855} // namespace llvm856 857#endif858