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1//===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries -------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H10#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H11 12#include "llvm/BinaryFormat/ELF.h"13#include "llvm/MC/MCFixup.h"14 15#undef RISCV16 17namespace llvm::RISCV {18enum Fixups {19 // 20-bit fixup corresponding to %hi(foo) for instructions like lui20 fixup_riscv_hi20 = FirstTargetFixupKind,21 // 12-bit fixup corresponding to %lo(foo) for instructions like addi22 fixup_riscv_lo12_i,23 // 12-bit fixup corresponding to foo-bar for instructions like addi24 fixup_riscv_12_i,25 // 12-bit fixup corresponding to %lo(foo) for the S-type store instructions26 fixup_riscv_lo12_s,27 // 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc28 fixup_riscv_pcrel_hi20,29 // 12-bit fixup corresponding to %pcrel_lo(foo) for instructions like addi30 fixup_riscv_pcrel_lo12_i,31 // 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store32 // instructions33 fixup_riscv_pcrel_lo12_s,34 // 20-bit fixup for symbol references in the jal instruction35 fixup_riscv_jal,36 // 12-bit fixup for symbol references in the branch instructions37 fixup_riscv_branch,38 // 11-bit fixup for symbol references in the compressed jump instruction39 fixup_riscv_rvc_jump,40 // 8-bit fixup for symbol references in the compressed branch instruction41 fixup_riscv_rvc_branch,42 // 6-bit fixup for symbol references in instructions like c.li43 fixup_riscv_rvc_imm,44 // Fixup representing a legacy no-pic function call attached to the auipc45 // instruction in a pair composed of adjacent auipc+jalr instructions.46 fixup_riscv_call,47 // Fixup representing a function call attached to the auipc instruction in a48 // pair composed of adjacent auipc+jalr instructions.49 fixup_riscv_call_plt,50 51 // Qualcomm specific fixups52 // 12-bit fixup for symbol references in the 48-bit Xqcibi branch immediate53 // instructions54 fixup_riscv_qc_e_branch,55 // 32-bit fixup for symbol references in the 48-bit qc.e.li instruction56 fixup_riscv_qc_e_32,57 // 20-bit fixup for symbol references in the 32-bit qc.li instruction58 fixup_riscv_qc_abs20_u,59 // 32-bit fixup for symbol references in the 48-bit qc.j/qc.jal instructions60 fixup_riscv_qc_e_call_plt,61 62 // Andes specific fixups63 // 10-bit fixup for symbol references in the xandesperf branch instruction64 fixup_riscv_nds_branch_10,65 66 // Used as a sentinel, must be the last67 fixup_riscv_invalid,68 NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind69};70} // end namespace llvm::RISCV71 72#endif73