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1//===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides RISC-V specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H15 16#include "llvm/MC/MCTargetOptions.h"17#include "llvm/Support/DataTypes.h"18#include <memory>19 20namespace llvm {21class MCAsmBackend;22class MCCodeEmitter;23class MCContext;24class MCInstrInfo;25class MCObjectTargetWriter;26class MCRegisterInfo;27class MCSubtargetInfo;28class Target;29 30MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,31 MCContext &Ctx);32 33MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,34 const MCRegisterInfo &MRI,35 const MCTargetOptions &Options);36 37std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,38 bool Is64Bit);39} // namespace llvm40 41// Defines symbolic names for RISC-V registers.42#define GET_REGINFO_ENUM43#include "RISCVGenRegisterInfo.inc"44 45// Defines symbolic names for RISC-V instructions.46#define GET_INSTRINFO_ENUM47#define GET_INSTRINFO_MC_HELPER_DECLS48#include "RISCVGenInstrInfo.inc"49 50#define GET_SUBTARGETINFO_ENUM51#include "RISCVGenSubtargetInfo.inc"52 53#endif54