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1//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H10#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H11 12#include "llvm/ADT/SmallVector.h"13#include "llvm/MC/MCRegister.h"14#include "llvm/MC/MCSubtargetInfo.h"15#include <cstdint>16 17namespace llvm {18class APInt;19 20namespace RISCVMatInt {21 22enum OpndKind {23 RegImm, // ADDI/ADDIW/XORI/SLLI/SRLI/SLLI_UW/RORI/BSETI/BCLRI/TH_SRRI24 Imm, // LUI/QC_LI/QC_E_LI/PLI_B/PLI_H/PLI_W25 RegReg, // SH1ADD/SH2ADD/SH3ADD/PACK26 RegX0, // ADD_UW27};28 29class Inst {30 unsigned Opc;31 int32_t Imm; // The largest value we need to store is 32 bits for QC_E_LI.32 33public:34 Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {35 assert(I == Imm && "truncated");36 }37 38 unsigned getOpcode() const { return Opc; }39 int64_t getImm() const { return Imm; }40 41 OpndKind getOpndKind() const;42};43using InstSeq = SmallVector<Inst, 8>;44 45// Helper to generate an instruction sequence that will materialise the given46// immediate value into a register. A sequence of instructions represented by a47// simple struct is produced rather than directly emitting the instructions in48// order to allow this helper to be used from both the MC layer and during49// instruction selection.50InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI);51 52// Helper to generate the generateInstSeq instruction sequence using MCInsts53void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,54 MCRegister DestReg, SmallVectorImpl<MCInst> &Insts);55 56// Helper to generate an instruction sequence that can materialize the given57// immediate value into a register using an additional temporary register. This58// handles cases where the constant can be generated by (ADD (SLLI X, C), X) or59// (ADD_UW (SLLI X, C) X). The sequence to generate X is returned. ShiftAmt is60// provides the SLLI and AddOpc indicates ADD or ADD_UW.61InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,62 unsigned &ShiftAmt, unsigned &AddOpc);63 64// Helper to estimate the number of instructions required to materialise the65// given immediate value into a register. This estimate does not account for66// `Val` possibly fitting into an immediate, and so may over-estimate.67//68// This will attempt to produce instructions to materialise `Val` as an69// `Size`-bit immediate.70//71// If CompressionCost is true it will use a different cost calculation if RVC is72// enabled. This should be used to compare two different sequences to determine73// which is more compressible.74//75// If FreeZeroes is true, it will be assumed free to materialize any76// XLen-sized chunks that are 0. This is appropriate to use in instances when77// the zero register can be used, e.g. when estimating the cost of78// materializing a value used by a particular operation.79int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,80 bool CompressionCost = false, bool FreeZeroes = false);81} // namespace RISCVMatInt82} // namespace llvm83#endif84