232 lines · cpp
1//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides RISC-V specific target streamer methods.10//11//===----------------------------------------------------------------------===//12 13#include "RISCVTargetStreamer.h"14#include "RISCVBaseInfo.h"15#include "RISCVMCTargetDesc.h"16#include "llvm/BinaryFormat/ELF.h"17#include "llvm/MC/MCContext.h"18#include "llvm/MC/MCExpr.h"19#include "llvm/MC/MCSectionELF.h"20#include "llvm/MC/MCStreamer.h"21#include "llvm/MC/MCSymbol.h"22#include "llvm/Support/Alignment.h"23#include "llvm/Support/CommandLine.h"24#include "llvm/Support/ErrorHandling.h"25#include "llvm/Support/FormattedStream.h"26#include "llvm/Support/RISCVAttributes.h"27#include "llvm/TargetParser/RISCVISAInfo.h"28 29using namespace llvm;30 31// This option controls whether or not we emit ELF attributes for ABI features,32// like RISC-V atomics or X3 usage.33static cl::opt<bool> RiscvAbiAttr(34 "riscv-abi-attributes",35 cl::desc("Enable emitting RISC-V ELF attributes for ABI features"),36 cl::Hidden);37 38RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}39 40void RISCVTargetStreamer::finish() { finishAttributeSection(); }41void RISCVTargetStreamer::reset() {}42 43void RISCVTargetStreamer::emitDirectiveOptionArch(44 ArrayRef<RISCVOptionArchArg> Args) {}45void RISCVTargetStreamer::emitDirectiveOptionExact() {}46void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}47void RISCVTargetStreamer::emitDirectiveOptionPIC() {}48void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}49void RISCVTargetStreamer::emitDirectiveOptionPop() {}50void RISCVTargetStreamer::emitDirectiveOptionPush() {}51void RISCVTargetStreamer::emitDirectiveOptionRelax() {}52void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}53void RISCVTargetStreamer::emitDirectiveOptionRVC() {}54void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}55void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}56void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}57void RISCVTargetStreamer::finishAttributeSection() {}58void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,59 StringRef String) {}60void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,61 unsigned IntValue,62 StringRef StringValue) {}63 64void RISCVTargetStreamer::emitNoteGnuPropertySection(65 const uint32_t Feature1And) {66 MCStreamer &OutStreamer = getStreamer();67 MCContext &Ctx = OutStreamer.getContext();68 69 const Triple &Triple = Ctx.getTargetTriple();70 Align NoteAlign;71 uint64_t DescSize;72 if (Triple.isArch64Bit()) {73 NoteAlign = Align(8);74 DescSize = 16;75 } else {76 assert(Triple.isArch32Bit());77 NoteAlign = Align(4);78 DescSize = 12;79 }80 81 assert(Ctx.getObjectFileType() == MCContext::Environment::IsELF);82 MCSection *const NoteSection =83 Ctx.getELFSection(".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);84 OutStreamer.pushSection();85 OutStreamer.switchSection(NoteSection);86 87 // Emit the note header88 OutStreamer.emitValueToAlignment(NoteAlign);89 OutStreamer.emitIntValue(4, 4); // n_namsz90 OutStreamer.emitIntValue(DescSize, 4); // n_descsz91 OutStreamer.emitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4); // n_type92 OutStreamer.emitBytes(StringRef("GNU", 4)); // n_name93 94 // Emit n_desc field95 96 // Emit the feature_1_and property97 OutStreamer.emitIntValue(ELF::GNU_PROPERTY_RISCV_FEATURE_1_AND, 4); // pr_type98 OutStreamer.emitIntValue(4, 4); // pr_datasz99 OutStreamer.emitIntValue(Feature1And, 4); // pr_data100 OutStreamer.emitValueToAlignment(NoteAlign); // pr_padding101 102 OutStreamer.popSection();103}104 105void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {106 assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");107 TargetABI = ABI;108}109 110void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {111 HasRVC = STI.hasFeature(RISCV::FeatureStdExtZca);112 HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso);113}114 115void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,116 bool EmitStackAlign) {117 if (EmitStackAlign) {118 unsigned StackAlign;119 if (TargetABI == RISCVABI::ABI_ILP32E)120 StackAlign = 4;121 else if (TargetABI == RISCVABI::ABI_LP64E)122 StackAlign = 8;123 else124 StackAlign = 16;125 emitAttribute(RISCVAttrs::STACK_ALIGN, StackAlign);126 }127 128 auto ParseResult = RISCVFeatures::parseFeatureBits(129 STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());130 if (!ParseResult) {131 report_fatal_error(ParseResult.takeError());132 } else {133 auto &ISAInfo = *ParseResult;134 emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());135 }136 137 if (RiscvAbiAttr && STI.hasFeature(RISCV::FeatureStdExtA)) {138 unsigned AtomicABITag;139 if (STI.hasFeature(RISCV::FeatureStdExtZalasr))140 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A7);141 else if (STI.hasFeature(RISCV::FeatureNoTrailingSeqCstFence))142 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6C);143 else144 AtomicABITag = static_cast<unsigned>(RISCVAttrs::RISCVAtomicAbiTag::A6S);145 emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag);146 }147}148 149// This part is for ascii assembly output150RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,151 formatted_raw_ostream &OS)152 : RISCVTargetStreamer(S), OS(OS) {}153 154void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {155 OS << "\t.option\tpush\n";156}157 158void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {159 OS << "\t.option\tpop\n";160}161 162void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {163 OS << "\t.option\tpic\n";164}165 166void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {167 OS << "\t.option\tnopic\n";168}169 170void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {171 OS << "\t.option\trvc\n";172}173 174void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {175 OS << "\t.option\tnorvc\n";176}177 178void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {179 OS << "\t.option\texact\n";180}181 182void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {183 OS << "\t.option\tnoexact\n";184}185 186void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {187 OS << "\t.option\trelax\n";188}189 190void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {191 OS << "\t.option\tnorelax\n";192}193 194void RISCVTargetAsmStreamer::emitDirectiveOptionArch(195 ArrayRef<RISCVOptionArchArg> Args) {196 OS << "\t.option\tarch";197 for (const auto &Arg : Args) {198 OS << ", ";199 switch (Arg.Type) {200 case RISCVOptionArchArgType::Full:201 break;202 case RISCVOptionArchArgType::Plus:203 OS << "+";204 break;205 case RISCVOptionArchArgType::Minus:206 OS << "-";207 break;208 }209 OS << Arg.Value;210 }211 OS << "\n";212}213 214void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {215 OS << "\t.variant_cc\t" << Symbol.getName() << "\n";216}217 218void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {219 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";220}221 222void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,223 StringRef String) {224 OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";225}226 227void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,228 unsigned IntValue,229 StringRef StringValue) {}230 231void RISCVTargetAsmStreamer::finishAttributeSection() {}232