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1//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9include "llvm/Target/Target.td"10 11//===----------------------------------------------------------------------===//12// RISC-V subtarget features and instruction predicates.13//===----------------------------------------------------------------------===//14 15include "RISCVFeatures.td"16 17//===----------------------------------------------------------------------===//18// RISC-V profiles supported.19//===----------------------------------------------------------------------===//20 21include "RISCVProfiles.td"22 23//===----------------------------------------------------------------------===//24// Named operands for CSR instructions.25//===----------------------------------------------------------------------===//26 27include "RISCVSystemOperands.td"28 29//===----------------------------------------------------------------------===//30// Registers, calling conventions, instruction descriptions.31//===----------------------------------------------------------------------===//32 33include "RISCVRegisterInfo.td"34include "RISCVSchedule.td"35include "RISCVCallingConv.td"36include "RISCVInstrInfo.td"37include "GISel/RISCVRegisterBanks.td"38 39//===----------------------------------------------------------------------===//40// Instruction predicates41//===----------------------------------------------------------------------===//42 43include "RISCVInstrPredicates.td"44 45//===----------------------------------------------------------------------===//46// RISC-V macro fusions.47//===----------------------------------------------------------------------===//48 49include "RISCVMacroFusion.td"50 51//===----------------------------------------------------------------------===//52// RISC-V Scheduling Models53//===----------------------------------------------------------------------===//54include "RISCVSchedAndes45.td"55include "RISCVSchedGenericOOO.td"56include "RISCVSchedMIPSP8700.td"57include "RISCVSchedRocket.td"58include "RISCVSchedSiFive7.td"59include "RISCVSchedSiFiveP400.td"60include "RISCVSchedSiFiveP500.td"61include "RISCVSchedSiFiveP600.td"62include "RISCVSchedSiFiveP800.td"63include "RISCVSchedSpacemitX60.td"64include "RISCVSchedSyntacoreSCR1.td"65include "RISCVSchedSyntacoreSCR345.td"66include "RISCVSchedSyntacoreSCR7.td"67include "RISCVSchedTTAscalonD8.td"68include "RISCVSchedXiangShanNanHu.td"69 70//===----------------------------------------------------------------------===//71// RISC-V processors supported.72//===----------------------------------------------------------------------===//73 74include "RISCVProcessors.td"75 76//===----------------------------------------------------------------------===//77// Pfm Counters78//===----------------------------------------------------------------------===//79 80include "RISCVPfmCounters.td"81 82//===----------------------------------------------------------------------===//83// Define the RISC-V target.84//===----------------------------------------------------------------------===//85 86def RISCVInstrInfo : InstrInfo {87 let guessInstructionProperties = 0;88}89 90def RISCVAsmParser : AsmParser {91 let ShouldEmitMatchRegisterAltName = 1;92 let AllowDuplicateRegisterNames = 1;93}94 95def RISCVAsmWriter : AsmWriter {96 int PassSubtarget = 1;97}98 99defm : RemapAllTargetPseudoPointerOperands<GPR>;100 101def RISCV : Target {102 let InstructionSet = RISCVInstrInfo;103 let AssemblyParsers = [RISCVAsmParser];104 let AssemblyWriters = [RISCVAsmWriter];105 let AllowRegisterRenaming = 1;106}107