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1//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This describes the calling conventions for the RISC-V architecture.10//11//===----------------------------------------------------------------------===//12 13// The RISC-V calling convention is handled with custom code in14// RISCVISelLowering.cpp (CC_RISCV).15 16def CSR_ILP32E_LP64E : CalleeSavedRegs<(add X1, X8, X9)>;17 18def CSR_ILP32_LP6419 : CalleeSavedRegs<(add CSR_ILP32E_LP64E, (sequence "X%u", 18, 27))>;20 21def CSR_ILP32F_LP64F22 : CalleeSavedRegs<(add CSR_ILP32_LP64,23 F8_F, F9_F, (sequence "F%u_F", 18, 27))>;24 25def CSR_ILP32D_LP64D26 : CalleeSavedRegs<(add CSR_ILP32_LP64,27 F8_D, F9_D, (sequence "F%u_D", 18, 27))>;28 29defvar CSR_V = (add (sequence "V%u", 1, 7), (sequence "V%u", 24, 31),30 V2M2, V4M2, V6M2, V24M2, V26M2, V28M2, V30M2,31 V4M4, V24M4, V28M4, V24M8);32 33def CSR_ILP32_LP64_V34 : CalleeSavedRegs<(add CSR_ILP32_LP64, CSR_V)>;35 36def CSR_ILP32F_LP64F_V37 : CalleeSavedRegs<(add CSR_ILP32F_LP64F, CSR_V)>;38 39def CSR_ILP32D_LP64D_V40 : CalleeSavedRegs<(add CSR_ILP32D_LP64D, CSR_V)>;41 42// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()43def CSR_NoRegs : CalleeSavedRegs<(add)>;44 45def CSR_IPRA : CalleeSavedRegs<(add X1)>;46 47// Interrupt handler needs to save/restore all registers that are used,48// both Caller and Callee saved registers.49def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>;50 51// Same as CSR_Interrupt, but including all 32-bit FP registers.52def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,53 (sequence "F%u_F", 0, 31))>;54 55// Same as CSR_Interrupt, but including all 64-bit FP registers.56def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,57 (sequence "F%u_D", 0, 31))>;58 59defvar VREGS = (add (sequence "V%u", 0, 31),60 (sequence "V%uM2", 0, 31, 2),61 (sequence "V%uM4", 0, 31, 4),62 (sequence "V%uM8", 0, 31, 8));63 64// Same as CSR_Interrupt, but including all vector registers.65def CSR_XLEN_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, VREGS)>;66 67// Same as CSR_Interrupt, but including all 32-bit FP registers and all vector68// registers.69def CSR_XLEN_F32_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F32_Interrupt, VREGS)>;70 71// Same as CSR_Interrupt, but including all 64-bit FP registers and all vector72// registers.73def CSR_XLEN_F64_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F64_Interrupt, VREGS)>;74 75// Same as CSR_Interrupt, but excluding X16-X31.76def CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt,77 (sequence "X%u", 16, 31))>;78 79// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31.80def CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt,81 (sequence "X%u", 16, 31))>;82 83// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31.84def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt,85 (sequence "X%u", 16, 31))>;86 87// Same as CSR_XLEN_V_Interrupt, but excluding X16-X31.88def CSR_XLEN_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_V_Interrupt,89 (sequence "X%u", 16, 31))>;90 91// Same as CSR_XLEN_F32_V_Interrupt, but excluding X16-X31.92def CSR_XLEN_F32_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_V_Interrupt,93 (sequence "X%u", 16, 31))>;94 95// Same as CSR_XLEN_F64_V_Interrupt, but excluding X16-X31.96def CSR_XLEN_F64_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_V_Interrupt,97 (sequence "X%u", 16, 31))>;98 99def CSR_RT_MostRegs : CalleeSavedRegs<(sub CSR_Interrupt, X6, X7, X28)>;100def CSR_RT_MostRegs_RVE : CalleeSavedRegs<(sub CSR_RT_MostRegs,101 (sequence "X%u", 16, 31))>;102