117 lines · cpp
1//===- RISCVDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===---------------------------------------------------------------------===//8//9// This pass rewrites Rd to x0 for instrs whose return values are unused.10//11//===---------------------------------------------------------------------===//12 13#include "RISCV.h"14#include "RISCVSubtarget.h"15#include "llvm/ADT/Statistic.h"16#include "llvm/CodeGen/LiveDebugVariables.h"17#include "llvm/CodeGen/LiveIntervals.h"18#include "llvm/CodeGen/LiveStacks.h"19#include "llvm/CodeGen/MachineFunctionPass.h"20 21using namespace llvm;22#define DEBUG_TYPE "riscv-dead-defs"23#define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"24 25STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");26 27namespace {28class RISCVDeadRegisterDefinitions : public MachineFunctionPass {29public:30 static char ID;31 32 RISCVDeadRegisterDefinitions() : MachineFunctionPass(ID) {}33 bool runOnMachineFunction(MachineFunction &MF) override;34 void getAnalysisUsage(AnalysisUsage &AU) const override {35 AU.setPreservesCFG();36 AU.addRequired<LiveIntervalsWrapperPass>();37 AU.addPreserved<LiveIntervalsWrapperPass>();38 AU.addRequired<LiveIntervalsWrapperPass>();39 AU.addPreserved<SlotIndexesWrapperPass>();40 AU.addPreserved<LiveDebugVariablesWrapperLegacy>();41 AU.addPreserved<LiveStacksWrapperLegacy>();42 MachineFunctionPass::getAnalysisUsage(AU);43 }44 45 StringRef getPassName() const override { return RISCV_DEAD_REG_DEF_NAME; }46};47} // end anonymous namespace48 49char RISCVDeadRegisterDefinitions::ID = 0;50INITIALIZE_PASS(RISCVDeadRegisterDefinitions, DEBUG_TYPE,51 RISCV_DEAD_REG_DEF_NAME, false, false)52 53FunctionPass *llvm::createRISCVDeadRegisterDefinitionsPass() {54 return new RISCVDeadRegisterDefinitions();55}56 57bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {58 if (skipFunction(MF.getFunction()))59 return false;60 61 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();62 LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();63 LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n");64 65 bool MadeChange = false;66 for (MachineBasicBlock &MBB : MF) {67 for (MachineInstr &MI : MBB) {68 // We only handle non-computational instructions since some NOP encodings69 // are reserved for HINT instructions.70 const MCInstrDesc &Desc = MI.getDesc();71 if (!Desc.mayLoad() && !Desc.mayStore() &&72 !Desc.hasUnmodeledSideEffects() &&73 MI.getOpcode() != RISCV::PseudoVSETVLI &&74 MI.getOpcode() != RISCV::PseudoVSETIVLI)75 continue;76 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {77 MachineOperand &MO = MI.getOperand(I);78 if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())79 continue;80 // Be careful not to change the register if it's a tied operand.81 if (MI.isRegTiedToUseOperand(I)) {82 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");83 continue;84 }85 Register Reg = MO.getReg();86 if (!Reg.isVirtual() || !MO.isDead())87 continue;88 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";89 MI.print(dbgs()));90 Register X0Reg;91 const TargetRegisterClass *RC = TII->getRegClass(Desc, I);92 if (RC && RC->contains(RISCV::X0)) {93 X0Reg = RISCV::X0;94 } else if (RC && RC->contains(RISCV::X0_W)) {95 X0Reg = RISCV::X0_W;96 } else if (RC && RC->contains(RISCV::X0_H)) {97 X0Reg = RISCV::X0_H;98 } else if (RC && RC->contains(RISCV::X0_Pair)) {99 X0Reg = RISCV::X0_Pair;100 } else {101 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");102 continue;103 }104 assert(LIS.hasInterval(Reg));105 LIS.removeInterval(Reg);106 MO.setReg(X0Reg);107 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ";108 MI.print(dbgs()));109 ++NumDeadDefsReplaced;110 MadeChange = true;111 }112 }113 }114 115 return MadeChange;116}117