1970 lines · plain
1//===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// RISC-V subtarget features and instruction predicates.11//===----------------------------------------------------------------------===//12 13// Subclass of SubtargetFeature to be used when the feature is also a RISC-V14// extension. Extensions have a version and may be experimental.15// NOTE: The extension name must start with16// - "FeatureStdExt" for standard extensions17// - "FeatureVendor" for vendor-specific extensions18//19// major - Major version of extension.20// minor - Minor version of extension.21// desc - Description of extension.22// implies - Extensions or features implied by this extension.23// fieldname - name of field to create in RISCVSubtarget. By default replaces24// uses the record name by replacing Feature with Has.25// value - Value to assign to the field in RISCVSubtarget when this26// extension is enabled. Usually "true", but can be changed.27// IsExperimental28// - Indicates whether the extension is experimental29class RISCVExtension<int major, int minor, string desc,30 list<SubtargetFeature> implies = [],31 string fieldname = !subst("Feature", "Has", NAME),32 string value = "true", bit IsExperimental = false>33 : SubtargetFeature<"", fieldname, value, "", implies> {34 defvar extName = !subst("FeatureVendor", "", !subst("FeatureStdExt", "", NAME));35 36 // Name - Name of the extension in lower case.37 let Name = !if(IsExperimental, "experimental-", "") # !tolower(extName);38 39 // Desc - Description of extension with its name.40 let Desc = "'" # extName # "' (" # desc # ")";41 42 // MajorVersion - The major version for this extension.43 int MajorVersion = major;44 45 // MinorVersion - The minor version for this extension.46 int MinorVersion = minor;47 48 // Experimental - Does extension require -menable-experimental-extensions.49 bit Experimental = false;50}51 52// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value53// from __riscv_feature_bits based on the groupID and bitmask.54// groupID - groupID of extension55// bitPos - bit position of extension bitmask56class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {57 int GroupID = groupID;58 int BitPos = bitPos;59}60 61// Version of RISCVExtension to be used for Experimental extensions. This62// sets the Experimental flag and prepends experimental- to the -mattr name.63class RISCVExperimentalExtension<int major, int minor, string desc,64 list<RISCVExtension> implies = [],65 string fieldname = !subst("Feature", "Has", NAME),66 string value = "true">67 : RISCVExtension<major, minor, desc, implies, fieldname, value, true> {68 let Experimental = true;69}70 71// Integer Extensions72 73def FeatureStdExtI74 : RISCVExtension<2, 1, "Base Integer Instruction Set">,75 RISCVExtensionBitmask<0, 8>;76 77def FeatureStdExtE78 : RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">,79 RISCVExtensionBitmask<0, 4>;80 81def FeatureStdExtZibi82 : RISCVExperimentalExtension<0, 1, "Branch with Immediate">;83def HasStdExtZibi : Predicate<"Subtarget->hasStdExtZibi()">,84 AssemblerPredicate<(all_of FeatureStdExtZibi),85 "'Zibi' (Branch with Immediate)">;86 87def FeatureStdExtZic64b88 : RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;89 90def FeatureStdExtZicbom91 : RISCVExtension<1, 0, "Cache-Block Management Instructions">;92def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,93 AssemblerPredicate<(all_of FeatureStdExtZicbom),94 "'Zicbom' (Cache-Block Management Instructions)">;95 96def FeatureStdExtZicbop97 : RISCVExtension<1, 0, "Cache-Block Prefetch Instructions">;98def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,99 AssemblerPredicate<(all_of FeatureStdExtZicbop),100 "'Zicbop' (Cache-Block Prefetch Instructions)">;101 102def FeatureStdExtZicboz103 : RISCVExtension<1, 0, "Cache-Block Zero Instructions">,104 RISCVExtensionBitmask<0, 37>;105def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,106 AssemblerPredicate<(all_of FeatureStdExtZicboz),107 "'Zicboz' (Cache-Block Zero Instructions)">;108 109def FeatureStdExtZiccamoa110 : RISCVExtension<1, 0, "Main Memory Supports All Atomics in A">;111 112def FeatureStdExtZiccamoc113 : RISCVExtension<1, 0, "Main Memory Supports Atomics in Zacas">;114 115def FeatureStdExtZiccif116 : RISCVExtension<1, 0,117 "Main Memory Supports Instruction Fetch with Atomicity Requirement">;118 119def FeatureStdExtZicclsm120 : RISCVExtension<1, 0, "Main Memory Supports Misaligned Loads/Stores">;121 122def FeatureStdExtZiccrse123 : RISCVExtension<1, 0,124 "Main Memory Supports Forward Progress on LR/SC Sequences">;125 126def FeatureStdExtZicsr127 : RISCVExtension<2, 0, "CSRs">;128def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,129 AssemblerPredicate<(all_of FeatureStdExtZicsr),130 "'Zicsr' (CSRs)">;131 132def FeatureStdExtZicntr133 : RISCVExtension<2, 0, "Base Counters and Timers",134 [FeatureStdExtZicsr]>;135 136def FeatureStdExtZicond137 : RISCVExtension<1, 0, "Integer Conditional Operations">,138 RISCVExtensionBitmask<0, 38>;139def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,140 AssemblerPredicate<(all_of FeatureStdExtZicond),141 "(Integer Conditional Operations)">;142 143def FeatureStdExtZifencei144 : RISCVExtension<2, 0, "fence.i">;145def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,146 AssemblerPredicate<(all_of FeatureStdExtZifencei),147 "'Zifencei' (fence.i)">;148 149def FeatureStdExtZihintpause150 : RISCVExtension<2, 0, "Pause Hint">,151 RISCVExtensionBitmask<0, 40>;152def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,153 AssemblerPredicate<(all_of FeatureStdExtZihintpause),154 "'Zihintpause' (Pause Hint)">;155 156def FeatureStdExtZihintntl157 : RISCVExtension<1, 0, "Non-Temporal Locality Hints">,158 RISCVExtensionBitmask<0, 39>;159def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,160 AssemblerPredicate<(all_of FeatureStdExtZihintntl),161 "'Zihintntl' (Non-Temporal Locality Hints)">;162 163def FeatureStdExtZihpm164 : RISCVExtension<2, 0, "Hardware Performance Counters",165 [FeatureStdExtZicsr]>;166 167def FeatureStdExtZimop : RISCVExtension<1, 0, "May-Be-Operations">,168 RISCVExtensionBitmask<1, 1>;169def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,170 AssemblerPredicate<(all_of FeatureStdExtZimop),171 "'Zimop' (May-Be-Operations)">;172 173def FeatureStdExtZicfilp174 : RISCVExperimentalExtension<1, 0, "Landing pad",175 [FeatureStdExtZicsr]>;176def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,177 AssemblerPredicate<(all_of FeatureStdExtZicfilp),178 "'Zicfilp' (Landing pad)">;179def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,180 AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>;181 182def FeatureStdExtZicfiss183 : RISCVExperimentalExtension<1, 0, "Shadow stack",184 [FeatureStdExtZicsr, FeatureStdExtZimop]>;185def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,186 AssemblerPredicate<(all_of FeatureStdExtZicfiss),187 "'Zicfiss' (Shadow stack)">;188 189def FeatureStdExtZilsd190 : RISCVExtension<1, 0,191 "Load/Store Pair Instructions">,192 RISCVExtensionBitmask<1, 8>;193def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">,194 AssemblerPredicate<(all_of FeatureStdExtZilsd),195 "'Zilsd' (Load/Store pair instructions)">;196 197def FeatureZilsd4ByteAlign198 : SubtargetFeature<"zilsd-4byte-align", "AllowZilsd4ByteAlign", "true",199 "Allow 4-byte alignment for Zilsd LD/SD instructions">;200 201// Multiply Extensions202 203def FeatureStdExtZmmul204 : RISCVExtension<1, 0, "Integer Multiplication">;205def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,206 AssemblerPredicate<(all_of FeatureStdExtZmmul),207 "'Zmmul' (Integer Multiplication)">;208 209def FeatureStdExtM210 : RISCVExtension<2, 0, "Integer Multiplication and Division",211 [FeatureStdExtZmmul]>,212 RISCVExtensionBitmask<0, 12>;213def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,214 AssemblerPredicate<(all_of FeatureStdExtM),215 "'M' (Integer Multiplication and Division)">;216 217// Atomic Extensions218 219def FeatureStdExtZaamo220 : RISCVExtension<1, 0, "Atomic Memory Operations">;221def HasStdExtZaamo222 : Predicate<"Subtarget->hasStdExtZaamo()">,223 AssemblerPredicate<(any_of FeatureStdExtZaamo),224 "'Zaamo' (Atomic Memory Operations)">;225def NoStdExtZaamo : Predicate<"!Subtarget->hasStdExtZaamo()">;226 227def FeatureStdExtZalrsc228 : RISCVExtension<1, 0, "Load-Reserved/Store-Conditional">;229def HasStdExtZalrsc230 : Predicate<"Subtarget->hasStdExtZalrsc()">,231 AssemblerPredicate<(any_of FeatureStdExtZalrsc),232 "'Zalrsc' (Load-Reserved/Store-Conditional)">;233 234def FeatureStdExtA235 : RISCVExtension<2, 1, "Atomic Instructions",236 [FeatureStdExtZaamo, FeatureStdExtZalrsc]>,237 RISCVExtensionBitmask<0, 0>;238def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,239 AssemblerPredicate<(all_of FeatureStdExtA),240 "'A' (Atomic Instructions)">;241 242def FeatureStdExtZtso243 : RISCVExtension<1, 0, "Memory Model - Total Store Order">,244 RISCVExtensionBitmask<0, 47>;245def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,246 AssemblerPredicate<(all_of FeatureStdExtZtso),247 "'Ztso' (Memory Model - Total Store Order)">;248def NoStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;249 250def FeatureStdExtZa64rs251 : RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes">;252 253def FeatureStdExtZa128rs254 : RISCVExtension<1, 0, "Reservation Set Size of at Most 128 Bytes">;255 256def FeatureStdExtZabha257 : RISCVExtension<1, 0, "Byte and Halfword Atomic Memory Operations",258 [FeatureStdExtZaamo]>;259def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,260 AssemblerPredicate<(all_of FeatureStdExtZabha),261 "'Zabha' (Byte and Halfword Atomic Memory Operations)">;262 263def FeatureStdExtZacas264 : RISCVExtension<1, 0, "Atomic Compare-And-Swap Instructions",265 [FeatureStdExtZaamo]>,266 RISCVExtensionBitmask<0, 26>;267def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,268 AssemblerPredicate<(all_of FeatureStdExtZacas),269 "'Zacas' (Atomic Compare-And-Swap Instructions)">;270def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;271 272def FeatureStdExtZalasr273 : RISCVExperimentalExtension<0, 9, "Load-Acquire and Store-Release Instructions">;274def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,275 AssemblerPredicate<(all_of FeatureStdExtZalasr),276 "'Zalasr' (Load-Acquire and Store-Release Instructions)">;277 278def FeatureStdExtZama16b279 : RISCVExtension<1, 0, "Atomic 16-byte misaligned loads, stores and AMOs">;280 281def FeatureStdExtZawrs : RISCVExtension<1, 0, "Wait on Reservation Set">,282 RISCVExtensionBitmask<1, 7>;283def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,284 AssemblerPredicate<(all_of FeatureStdExtZawrs),285 "'Zawrs' (Wait on Reservation Set)">;286 287// Floating Point Extensions288 289def FeatureStdExtF290 : RISCVExtension<2, 2, "Single-Precision Floating-Point",291 [FeatureStdExtZicsr]>,292 RISCVExtensionBitmask<0, 5>;293def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,294 AssemblerPredicate<(all_of FeatureStdExtF),295 "'F' (Single-Precision Floating-Point)">;296 297def FeatureStdExtD298 : RISCVExtension<2, 2, "Double-Precision Floating-Point",299 [FeatureStdExtF]>,300 RISCVExtensionBitmask<0, 3>;301def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,302 AssemblerPredicate<(all_of FeatureStdExtD),303 "'D' (Double-Precision Floating-Point)">;304 305def FeatureStdExtQ306 : RISCVExtension<2, 2, "Quad-Precision Floating-Point", [FeatureStdExtD]>,307 RISCVExtensionBitmask<0, 16>;308def HasStdExtQ : Predicate<"Subtarget->hasStdExtQ()">,309 AssemblerPredicate<(all_of FeatureStdExtQ),310 "'Q' (Quad-Precision Floating-Point)">;311 312def FeatureStdExtZfhmin313 : RISCVExtension<1, 0, "Half-Precision Floating-Point Minimal",314 [FeatureStdExtF]>,315 RISCVExtensionBitmask<0, 36>;316def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,317 AssemblerPredicate<(all_of FeatureStdExtZfhmin),318 "'Zfh' (Half-Precision Floating-Point) or "319 "'Zfhmin' (Half-Precision Floating-Point Minimal)">;320 321def FeatureStdExtZfh322 : RISCVExtension<1, 0, "Half-Precision Floating-Point",323 [FeatureStdExtZfhmin]>,324 RISCVExtensionBitmask<0, 35>;325def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,326 AssemblerPredicate<(all_of FeatureStdExtZfh),327 "'Zfh' (Half-Precision Floating-Point)">;328def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;329 330def FeatureStdExtZfbfmin331 : RISCVExtension<1, 0, "Scalar BF16 Converts", [FeatureStdExtF]>;332def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,333 AssemblerPredicate<(all_of FeatureStdExtZfbfmin),334 "'Zfbfmin' (Scalar BF16 Converts)">;335 336def HasHalfFPLoadStoreMove337 : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,338 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,339 FeatureStdExtZfbfmin),340 "'Zfh' (Half-Precision Floating-Point) or "341 "'Zfhmin' (Half-Precision Floating-Point Minimal) or "342 "'Zfbfmin' (Scalar BF16 Converts)">;343 344def FeatureStdExtZfa345 : RISCVExtension<1, 0, "Additional Floating-Point", [FeatureStdExtF]>,346 RISCVExtensionBitmask<0, 34>;347def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,348 AssemblerPredicate<(all_of FeatureStdExtZfa),349 "'Zfa' (Additional Floating-Point)">;350def NoStdExtZfa : Predicate<"!Subtarget->hasStdExtZfa()">;351 352def FeatureStdExtZfinx353 : RISCVExtension<1, 0, "Float in Integer", [FeatureStdExtZicsr]>;354def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,355 AssemblerPredicate<(all_of FeatureStdExtZfinx),356 "'Zfinx' (Float in Integer)">;357def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,358 AssemblerPredicate<(any_of FeatureStdExtF,359 FeatureStdExtZfinx),360 "'F' (Single-Precision Floating-Point) or "361 "'Zfinx' (Float in Integer)">;362 363def FeatureStdExtZdinx364 : RISCVExtension<1, 0, "Double in Integer", [FeatureStdExtZfinx]>;365def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,366 AssemblerPredicate<(all_of FeatureStdExtZdinx),367 "'Zdinx' (Double in Integer)">;368 369def FeatureStdExtZhinxmin370 : RISCVExtension<1, 0, "Half Float in Integer Minimal",371 [FeatureStdExtZfinx]>;372def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,373 AssemblerPredicate<(all_of FeatureStdExtZhinxmin),374 "'Zhinx' (Half Float in Integer) or "375 "'Zhinxmin' (Half Float in Integer Minimal)">;376 377def FeatureStdExtZhinx378 : RISCVExtension<1, 0, "Half Float in Integer", [FeatureStdExtZhinxmin]>;379def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,380 AssemblerPredicate<(all_of FeatureStdExtZhinx),381 "'Zhinx' (Half Float in Integer)">;382def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;383 384// Compressed Extensions385def FeatureStdExtZca386 : RISCVExtension<1, 0,387 "part of the C extension, excluding compressed "388 "floating point loads/stores">,389 RISCVExtensionBitmask<1, 2>;390// FIXME: Update this message - Zca always implies C.391def HasStdExtZca392 : Predicate<"Subtarget->hasStdExtZca()">,393 AssemblerPredicate<(any_of FeatureStdExtZca),394 "'C' (Compressed Instructions) or "395 "'Zca' (part of the C extension, excluding "396 "compressed floating point loads/stores)">;397 398def FeatureStdExtC399 : RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,400 RISCVExtensionBitmask<0, 2>;401def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,402 AssemblerPredicate<(all_of FeatureStdExtC),403 "'C' (Compressed Instructions)">;404 405def FeatureStdExtZcb406 : RISCVExtension<1, 0, "Compressed basic bit manipulation instructions",407 [FeatureStdExtZca]>,408 RISCVExtensionBitmask<1, 3>;409def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,410 AssemblerPredicate<(all_of FeatureStdExtZcb),411 "'Zcb' (Compressed basic bit manipulation instructions)">;412 413def FeatureStdExtZcd414 : RISCVExtension<1, 0,415 "Compressed Double-Precision Floating-Point Instructions",416 [FeatureStdExtD, FeatureStdExtZca]>,417 RISCVExtensionBitmask<1, 4>;418 419def HasStdExtCOrZcd420 : Predicate<"Subtarget->hasStdExtCOrZcd()">,421 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),422 "'C' (Compressed Instructions) or "423 "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;424 425def FeatureStdExtZcf426 : RISCVExtension<1, 0,427 "Compressed Single-Precision Floating-Point Instructions",428 [FeatureStdExtF, FeatureStdExtZca]>,429 RISCVExtensionBitmask<1, 5>;430 431def FeatureStdExtZclsd432 : RISCVExtension<1, 0,433 "Compressed Load/Store Pair Instructions",434 [FeatureStdExtZilsd, FeatureStdExtZca]>,435 RISCVExtensionBitmask<1, 9>;436def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd()">,437 AssemblerPredicate<(all_of FeatureStdExtZclsd),438 "'Zclsd' (Compressed Load/Store pair instructions)">;439 440def FeatureStdExtZcmp441 : RISCVExtension<1, 0,442 "sequenced instructions for code-size reduction",443 [FeatureStdExtZca]>,444 RISCVExtensionBitmask<1, 10>;445def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,446 AssemblerPredicate<(all_of FeatureStdExtZcmp),447 "'Zcmp' (sequenced instructions for code-size reduction)">;448 449def FeatureStdExtZcmt450 : RISCVExtension<1, 0,451 "table jump instructions for code-size reduction",452 [FeatureStdExtZca, FeatureStdExtZicsr]>;453def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,454 AssemblerPredicate<(all_of FeatureStdExtZcmt),455 "'Zcmt' (table jump instructions for code-size reduction)">;456 457def FeatureStdExtZce458 : RISCVExtension<1, 0,459 "Compressed extensions for microcontrollers",460 [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,461 FeatureStdExtZcmt]>;462 463def HasStdExtCOrZcfOrZce464 : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() ||"465 "Subtarget->hasStdExtZce()">,466 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,467 FeatureStdExtZce),468 "'C' (Compressed Instructions) or "469 "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;470 471def FeatureStdExtZcmop472 : RISCVExtension<1, 0, "Compressed May-Be-Operations",473 [FeatureStdExtZca]>,474 RISCVExtensionBitmask<1, 6>;475def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,476 AssemblerPredicate<(all_of FeatureStdExtZcmop),477 "'Zcmop' (Compressed May-Be-Operations)">;478 479// Bitmanip Extensions480 481def FeatureStdExtZba482 : RISCVExtension<1, 0, "Address Generation Instructions">,483 RISCVExtensionBitmask<0, 27>;484def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,485 AssemblerPredicate<(all_of FeatureStdExtZba),486 "'Zba' (Address Generation Instructions)">;487def NoStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;488 489def FeatureStdExtZbb490 : RISCVExtension<1, 0, "Basic Bit-Manipulation">,491 RISCVExtensionBitmask<0, 28>;492def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,493 AssemblerPredicate<(all_of FeatureStdExtZbb),494 "'Zbb' (Basic Bit-Manipulation)">;495def NoStdExtZbb : Predicate<"!Subtarget->hasStdExtZbb()">,496 AssemblerPredicate<(all_of (not FeatureStdExtZbb))>;497 498def FeatureStdExtZbc499 : RISCVExtension<1, 0, "Carry-Less Multiplication">,500 RISCVExtensionBitmask<0, 29>;501def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,502 AssemblerPredicate<(all_of FeatureStdExtZbc),503 "'Zbc' (Carry-Less Multiplication)">;504 505def FeatureStdExtZbs506 : RISCVExtension<1, 0, "Single-Bit Instructions">,507 RISCVExtensionBitmask<0, 33>;508def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,509 AssemblerPredicate<(all_of FeatureStdExtZbs),510 "'Zbs' (Single-Bit Instructions)">;511 512// Bitmanip Extensions for Cryptography Extensions513 514def FeatureStdExtB515 : RISCVExtension<1, 0, "the collection of the Zba, Zbb, Zbs extensions",516 [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>,517 RISCVExtensionBitmask<0, 1>;518 519def FeatureStdExtZbkb520 : RISCVExtension<1, 0, "Bitmanip instructions for Cryptography">,521 RISCVExtensionBitmask<0, 30>;522def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,523 AssemblerPredicate<(all_of FeatureStdExtZbkb),524 "'Zbkb' (Bitmanip instructions for Cryptography)">;525def NoStdExtZbkb : Predicate<"!Subtarget->hasStdExtZbkb()">,526 AssemblerPredicate<(all_of (not FeatureStdExtZbkb))>;527 528def FeatureStdExtZbkx529 : RISCVExtension<1, 0, "Crossbar permutation instructions">,530 RISCVExtensionBitmask<0, 32>;531def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,532 AssemblerPredicate<(all_of FeatureStdExtZbkx),533 "'Zbkx' (Crossbar permutation instructions)">;534 535def HasStdExtZbbOrZbkb536 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,537 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),538 "'Zbb' (Basic Bit-Manipulation) or "539 "'Zbkb' (Bitmanip instructions for Cryptography)">;540 541// The Carry-less multiply subextension for cryptography is a subset of basic542// carry-less multiply subextension. The former should be enabled if the latter543// is enabled.544def FeatureStdExtZbkc545 : RISCVExtension<1, 0,546 "Carry-less multiply instructions for Cryptography">,547 RISCVExtensionBitmask<0, 31>;548def HasStdExtZbkc549 : Predicate<"Subtarget->hasStdExtZbkc()">,550 AssemblerPredicate<(all_of FeatureStdExtZbkc),551 "'Zbkc' (Carry-less multiply instructions for Cryptography)">;552 553def HasStdExtZbcOrZbkc554 : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,555 AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),556 "'Zbc' (Carry-Less Multiplication) or "557 "'Zbkc' (Carry-less multiply instructions "558 "for Cryptography)">;559 560// Cryptography Extensions561 562def FeatureStdExtZknd563 : RISCVExtension<1, 0, "NIST Suite: AES Decryption">,564 RISCVExtensionBitmask<0, 41>;565def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,566 AssemblerPredicate<(all_of FeatureStdExtZknd),567 "'Zknd' (NIST Suite: AES Decryption)">;568 569def FeatureStdExtZkne570 : RISCVExtension<1, 0, "NIST Suite: AES Encryption">,571 RISCVExtensionBitmask<0, 42>;572def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,573 AssemblerPredicate<(all_of FeatureStdExtZkne),574 "'Zkne' (NIST Suite: AES Encryption)">;575 576// Some instructions belong to both Zknd and Zkne subextensions.577// They should be enabled if either has been specified.578def HasStdExtZkndOrZkne579 : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,580 AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),581 "'Zknd' (NIST Suite: AES Decryption) or "582 "'Zkne' (NIST Suite: AES Encryption)">;583 584def FeatureStdExtZknh585 : RISCVExtension<1, 0, "NIST Suite: Hash Function Instructions">,586 RISCVExtensionBitmask<0, 43>;587def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,588 AssemblerPredicate<(all_of FeatureStdExtZknh),589 "'Zknh' (NIST Suite: Hash Function Instructions)">;590 591def FeatureStdExtZksed592 : RISCVExtension<1, 0, "ShangMi Suite: SM4 Block Cipher Instructions">,593 RISCVExtensionBitmask<0, 44>;594def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,595 AssemblerPredicate<(all_of FeatureStdExtZksed),596 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;597 598def FeatureStdExtZksh599 : RISCVExtension<1, 0, "ShangMi Suite: SM3 Hash Function Instructions">,600 RISCVExtensionBitmask<0, 45>;601def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,602 AssemblerPredicate<(all_of FeatureStdExtZksh),603 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;604 605def FeatureStdExtZkr606 : RISCVExtension<1, 0, "Entropy Source Extension">;607def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,608 AssemblerPredicate<(all_of FeatureStdExtZkr),609 "'Zkr' (Entropy Source Extension)">;610 611def FeatureStdExtZkn612 : RISCVExtension<1, 0, "NIST Algorithm Suite",613 [FeatureStdExtZbkb,614 FeatureStdExtZbkc,615 FeatureStdExtZbkx,616 FeatureStdExtZkne,617 FeatureStdExtZknd,618 FeatureStdExtZknh]>;619 620def FeatureStdExtZks621 : RISCVExtension<1, 0, "ShangMi Algorithm Suite",622 [FeatureStdExtZbkb,623 FeatureStdExtZbkc,624 FeatureStdExtZbkx,625 FeatureStdExtZksed,626 FeatureStdExtZksh]>;627 628def FeatureStdExtZkt629 : RISCVExtension<1, 0, "Data Independent Execution Latency">,630 RISCVExtensionBitmask<0, 46>;631 632def FeatureStdExtZk633 : RISCVExtension<1, 0, "Standard scalar cryptography extension",634 [FeatureStdExtZkn,635 FeatureStdExtZkr,636 FeatureStdExtZkt]>;637 638// Vector Extensions639 640def FeatureStdExtZvl32b : RISCVExtension<1, 0,641 "Minimum Vector Length 32", [],642 "ZvlLen", "32">;643 644foreach i = { 6-16 } in {645 defvar I = !shl(1, i);646 def FeatureStdExtZvl#I#b :647 RISCVExtension<1, 0, "Minimum Vector Length "#I,648 [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],649 "ZvlLen", !cast<string>(I)>;650}651 652def FeatureStdExtZve32x653 : RISCVExtension<1, 0,654 "Vector Extensions for Embedded Processors "655 "with maximal 32 EEW",656 [FeatureStdExtZicsr, FeatureStdExtZvl32b]>,657 RISCVExtensionBitmask<0, 60>;658 659 660def FeatureStdExtZve32f661 : RISCVExtension<1, 0,662 "Vector Extensions for Embedded Processors "663 "with maximal 32 EEW and F extension",664 [FeatureStdExtZve32x, FeatureStdExtF]>,665 RISCVExtensionBitmask<0, 61>;666 667def FeatureStdExtZve64x668 : RISCVExtension<1, 0,669 "Vector Extensions for Embedded Processors "670 "with maximal 64 EEW",671 [FeatureStdExtZve32x, FeatureStdExtZvl64b]>,672 RISCVExtensionBitmask<0, 62>;673 674def FeatureStdExtZve64f675 : RISCVExtension<1, 0,676 "Vector Extensions for Embedded Processors "677 "with maximal 64 EEW and F extension",678 [FeatureStdExtZve32f, FeatureStdExtZve64x]>,679 RISCVExtensionBitmask<0, 63>;680 681def FeatureStdExtZve64d682 : RISCVExtension<1, 0,683 "Vector Extensions for Embedded Processors "684 "with maximal 64 EEW, F and D extension",685 [FeatureStdExtZve64f, FeatureStdExtD]>,686 RISCVExtensionBitmask<1, 0>;687 688def FeatureStdExtV689 : RISCVExtension<1, 0,690 "Vector Extension for Application Processors",691 [FeatureStdExtZvl128b, FeatureStdExtZve64d]>,692 RISCVExtensionBitmask<0, 21>;693 694def FeatureStdExtZvfbfa695 : RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support",696 [FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;697def HasStdExtZvfbfa : Predicate<"Subtarget->hasStdExtZvfbfa()">,698 AssemblerPredicate<(all_of FeatureStdExtZvfbfa),699 "'Zvfbfa' (Additional BF16 vector compute support)">;700 701def FeatureStdExtZvfbfmin702 : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>;703def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,704 AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),705 "'Zvfbfmin' (Vector BF16 Converts)">;706 707def FeatureStdExtZvfbfwma708 : RISCVExtension<1, 0, "Vector BF16 widening mul-add",709 [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;710def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,711 AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),712 "'Zvfbfwma' (Vector BF16 widening mul-add)">;713 714def FeatureStdExtZvfhmin715 : RISCVExtension<1, 0,716 "Vector Half-Precision Floating-Point Minimal",717 [FeatureStdExtZve32f]>,718 RISCVExtensionBitmask<0, 51>;719 720def FeatureStdExtZvfh721 : RISCVExtension<1, 0, "Vector Half-Precision Floating-Point",722 [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>,723 RISCVExtensionBitmask<0, 50>;724 725def HasStdExtZfhOrZvfh726 : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,727 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),728 "'Zfh' (Half-Precision Floating-Point) or "729 "'Zvfh' (Vector Half-Precision Floating-Point)">;730 731def FeatureStdExtZvfofp8min732 : RISCVExperimentalExtension<0, 2,733 "Vector OFP8 Converts", [FeatureStdExtZve32f]>;734def HasStdExtZvfofp8min735 : Predicate<"Subtarget->hasStdExtZvfofp8min()">,736 AssemblerPredicate<(all_of FeatureStdExtZvfofp8min),737 "'Zvfofp8min' (Vector OFP8 Converts)">;738 739def HasStdExtZvfbfminOrZvfofp8min740 : Predicate<"Subtarget->hasStdExtZvfbfmin() ||"741 "Subtarget->hasStdExtZvfofp8min()">,742 AssemblerPredicate<(any_of FeatureStdExtZvfbfmin,743 FeatureStdExtZvfofp8min),744 "'Zvfbfmin' (Vector BF16 Converts) or "745 "'Zvfofp8min' (Vector OFP8 Converts)">;746 747// Vector Cryptography and Bitmanip Extensions748 749def FeatureStdExtZvkb750 : RISCVExtension<1, 0, "Vector Bit-manipulation used in Cryptography",751 [FeatureStdExtZve32x]>,752 RISCVExtensionBitmask<0, 52>;753def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,754 AssemblerPredicate<(all_of FeatureStdExtZvkb),755 "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;756 757def FeatureStdExtZvbb758 : RISCVExtension<1, 0, "Vector basic bit-manipulation instructions",759 [FeatureStdExtZvkb]>,760 RISCVExtensionBitmask<0, 48>;761def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,762 AssemblerPredicate<(all_of FeatureStdExtZvbb),763 "'Zvbb' (Vector basic bit-manipulation instructions)">;764 765def FeatureStdExtZvbc766 : RISCVExtension<1, 0, "Vector Carryless Multiplication",767 [FeatureStdExtZve64x]>,768 RISCVExtensionBitmask<0, 49>;769def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,770 AssemblerPredicate<(all_of FeatureStdExtZvbc),771 "'Zvbc' (Vector Carryless Multiplication)">;772 773def FeatureStdExtZvbc32e774 : RISCVExperimentalExtension<0, 7,775 "Vector Carryless Multiplication with 32-bits elements",776 [FeatureStdExtZve32x]>;777 778def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">,779 AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e),780 "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)">;781 782def FeatureStdExtZvkg783 : RISCVExtension<1, 0, "Vector GCM instructions for Cryptography",784 [FeatureStdExtZve32x]>,785 RISCVExtensionBitmask<0, 53>;786def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,787 AssemblerPredicate<(all_of FeatureStdExtZvkg),788 "'Zvkg' (Vector GCM instructions for Cryptography)">;789 790def FeatureStdExtZvkgs791 : RISCVExperimentalExtension<0, 7,792 "Vector-Scalar GCM instructions for Cryptography",793 [FeatureStdExtZvkg]>;794def HasStdExtZvkgs : Predicate<"Subtarget->hasStdExtZvkgs()">,795 AssemblerPredicate<(all_of FeatureStdExtZvkgs),796 "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)">;797 798def FeatureStdExtZvkned799 : RISCVExtension<1, 0,800 "Vector AES Encryption & Decryption (Single Round)",801 [FeatureStdExtZve32x]>,802 RISCVExtensionBitmask<0, 54>;803def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,804 AssemblerPredicate<(all_of FeatureStdExtZvkned),805 "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;806 807def FeatureStdExtZvknha808 : RISCVExtension<1, 0, "Vector SHA-2 (SHA-256 only)",809 [FeatureStdExtZve32x]>,810 RISCVExtensionBitmask<0, 55>;811def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,812 AssemblerPredicate<(all_of FeatureStdExtZvknha),813 "'Zvknha' (Vector SHA-2 (SHA-256 only))">;814 815def FeatureStdExtZvknhb816 : RISCVExtension<1, 0, "Vector SHA-2 (SHA-256 and SHA-512)",817 [FeatureStdExtZve64x]>,818 RISCVExtensionBitmask<0, 56>;819def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,820 AssemblerPredicate<(all_of FeatureStdExtZvknhb),821 "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;822 823def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">,824 AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb),825 "'Zvknha' or 'Zvknhb' (Vector SHA-2)">;826 827def FeatureStdExtZvksed828 : RISCVExtension<1, 0, "SM4 Block Cipher Instructions",829 [FeatureStdExtZve32x]>,830 RISCVExtensionBitmask<0, 57>;831def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,832 AssemblerPredicate<(all_of FeatureStdExtZvksed),833 "'Zvksed' (SM4 Block Cipher Instructions)">;834 835def FeatureStdExtZvksh836 : RISCVExtension<1, 0, "SM3 Hash Function Instructions",837 [FeatureStdExtZve32x]>,838 RISCVExtensionBitmask<0, 58>;839def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,840 AssemblerPredicate<(all_of FeatureStdExtZvksh),841 "'Zvksh' (SM3 Hash Function Instructions)">;842 843def FeatureStdExtZvkt844 : RISCVExtension<1, 0, "Vector Data-Independent Execution Latency">,845 RISCVExtensionBitmask<0, 59>;846 847// Zvk short-hand extensions848 849def FeatureStdExtZvkn850 : RISCVExtension<1, 0,851 "shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'",852 [FeatureStdExtZvkned, FeatureStdExtZvknhb,853 FeatureStdExtZvkb, FeatureStdExtZvkt]>;854 855def FeatureStdExtZvknc856 : RISCVExtension<1, 0, "shorthand for 'Zvknc' and 'Zvbc'",857 [FeatureStdExtZvkn, FeatureStdExtZvbc]>;858 859def FeatureStdExtZvkng860 : RISCVExtension<1, 0, "shorthand for 'Zvkn' and 'Zvkg'",861 [FeatureStdExtZvkn, FeatureStdExtZvkg]>;862 863def FeatureStdExtZvks864 : RISCVExtension<1, 0,865 "shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'",866 [FeatureStdExtZvksed, FeatureStdExtZvksh,867 FeatureStdExtZvkb, FeatureStdExtZvkt]>;868 869def FeatureStdExtZvksc870 : RISCVExtension<1, 0, "shorthand for 'Zvks' and 'Zvbc'",871 [FeatureStdExtZvks, FeatureStdExtZvbc]>;872 873def FeatureStdExtZvksg874 : RISCVExtension<1, 0, "shorthand for 'Zvks' and 'Zvkg'",875 [FeatureStdExtZvks, FeatureStdExtZvkg]>;876 877// Vector quad widening dot product878 879def FeatureStdExtZvqdotq880 : RISCVExperimentalExtension<0, 0, "Vector quad widening 4D Dot Product",881 [FeatureStdExtZve32x]>;882def HasStdExtZvqdotq : Predicate<"Subtarget->hasStdExtZvqdotq()">,883 AssemblerPredicate<(all_of FeatureStdExtZvqdotq),884 "'Zvqdotq' (Vector quad widening 4D Dot Product)">;885 886// Vector instruction predicates887 888def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,889 AssemblerPredicate<890 (any_of FeatureStdExtZve32x),891 "'V' (Vector Extension for Application Processors), 'Zve32x' "892 "(Vector Extensions for Embedded Processors)">;893def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,894 AssemblerPredicate<895 (any_of FeatureStdExtZve64x),896 "'V' (Vector Extension for Application Processors) or 'Zve64x' "897 "(Vector Extensions for Embedded Processors)">;898def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,899 AssemblerPredicate<900 (any_of FeatureStdExtZve32f),901 "'V' (Vector Extension for Application Processors), 'Zve32f' "902 "(Vector Extensions for Embedded Processors)">;903 904def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,905 AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),906 "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "907 "'Zvfh' (Vector Half-Precision Floating-Point)">;908 909def HasVInstructionsBF16Minimal : Predicate<"Subtarget->hasVInstructionsBF16Minimal()">;910def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;911def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;912 913def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;914 915// Hypervisor Extensions916 917def FeatureStdExtH : RISCVExtension<1, 0, "Hypervisor">,918 RISCVExtensionBitmask<0, 7>;919def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,920 AssemblerPredicate<(all_of FeatureStdExtH),921 "'H' (Hypervisor)">;922 923// Supervisor extensions924 925def FeatureStdExtSdext : RISCVExtension<1, 0, "External debugger">;926 927def FeatureStdExtSdtrig : RISCVExtension<1, 0, "Debugger triggers">;928 929def FeatureStdExtShgatpa930 : RISCVExtension<1, 0,931 "SvNNx4 mode supported for all modes supported by satp, as well as Bare">;932def FeatureStdExtShvsatpa933 : RISCVExtension<1, 0,934 "vsatp supports all modes supported by satp">;935 936def FeatureStdExtShlcofideleg937 : RISCVExtension<1, 0,938 "Delegating LCOFI Interrupts to VS-mode">;939 940def FeatureStdExtSmaia941 : RISCVExtension<1, 0,942 "Advanced Interrupt Architecture Machine Level">;943def FeatureStdExtSsaia944 : RISCVExtension<1, 0,945 "Advanced Interrupt Architecture Supervisor Level">;946 947def FeatureStdExtSmcntrpmf948 : RISCVExtension<1, 0, "Cycle and Instret Privilege Mode Filtering">;949 950def FeatureStdExtSmcsrind951 : RISCVExtension<1, 0, "Indirect CSR Access Machine Level">;952def FeatureStdExtSscsrind953 : RISCVExtension<1, 0, "Indirect CSR Access Supervisor Level">;954 955def FeatureStdExtSmdbltrp956 : RISCVExtension<1, 0, "Double Trap Machine Level", [FeatureStdExtZicsr]>;957def FeatureStdExtSsdbltrp958 : RISCVExtension<1, 0, "Double Trap Supervisor Level", [FeatureStdExtZicsr]>;959 960def FeatureStdExtSmepmp961 : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;962 963def FeatureStdExtSmpmpmt964 : RISCVExperimentalExtension<0, 6, "PMP-based Memory Types Extension">;965 966def FeatureStdExtSmrnmi967 : RISCVExtension<1, 0, "Resumable Non-Maskable Interrupts">;968def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">,969 AssemblerPredicate<(all_of FeatureStdExtSmrnmi),970 "'Smrnmi' (Resumable Non-Maskable Interrupts)">;971 972def FeatureStdExtSmcdeleg973 : RISCVExtension<1, 0, "Counter Delegation Machine Level">;974def FeatureStdExtSsccfg975 : RISCVExtension<1, 0, "Counter Configuration Supervisor Level">;976 977def FeatureStdExtSsccptr978 : RISCVExtension<1, 0, "Main memory supports page table reads">;979 980def FeatureStdExtSscofpmf981 : RISCVExtension<1, 0, "Count Overflow and Mode-Based Filtering">;982 983def FeatureStdExtShcounterenw984 : RISCVExtension<1, 0,985 "Support writeable hcounteren enable "986 "bit for any hpmcounter that is not read-only zero">;987def FeatureStdExtSscounterenw988 : RISCVExtension<1, 0,989 "Support writeable scounteren enable "990 "bit for any hpmcounter that is not read-only zero">;991 992def FeatureStdExtSmstateen993 : RISCVExtension<1, 0,994 "Machine-mode view of the state-enable extension">;995def FeatureStdExtSsstateen996 : RISCVExtension<1, 0,997 "Supervisor-mode view of the state-enable extension">;998 999def FeatureStdExtSsstrict1000 : RISCVExtension<1, 0,1001 "No non-conforming extensions are present">;1002 1003def FeatureStdExtSstc1004 : RISCVExtension<1, 0, "Supervisor-mode timer interrupts">;1005 1006def FeatureStdExtSsqosid1007 : RISCVExtension<1, 0, "Quality-of-Service (QoS) Identifiers">;1008 1009def FeatureStdExtShtvala1010 : RISCVExtension<1, 0, "htval provides all needed values">;1011def FeatureStdExtShvstvala1012 : RISCVExtension<1, 0, "vstval provides all needed values">;1013def FeatureStdExtSstvala1014 : RISCVExtension<1, 0, "stval provides all needed values">;1015 1016def FeatureStdExtShvstvecd1017 : RISCVExtension<1, 0, "vstvec supports Direct mode">;1018def FeatureStdExtSstvecd1019 : RISCVExtension<1, 0, "stvec supports Direct mode">;1020 1021def FeatureStdExtSsu64xl1022 : RISCVExtension<1, 0, "UXLEN=64 supported">;1023 1024def FeatureStdExtSvade1025 : RISCVExtension<1, 0, "Raise exceptions on improper A/D bits">;1026 1027def FeatureStdExtSvadu1028 : RISCVExtension<1, 0, "Hardware A/D updates">;1029 1030def FeatureStdExtSvbare1031 : RISCVExtension<1, 0, "satp mode Bare supported">;1032 1033def FeatureStdExtSvinval1034 : RISCVExtension<1, 0,1035 "Fine-Grained Address-Translation Cache Invalidation">;1036def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,1037 AssemblerPredicate<(all_of FeatureStdExtSvinval),1038 "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;1039 1040def FeatureStdExtSvnapot1041 : RISCVExtension<1, 0, "NAPOT Translation Contiguity">;1042 1043def FeatureStdExtSvpbmt1044 : RISCVExtension<1, 0, "Page-Based Memory Types">;1045 1046def FeatureStdExtSvvptc1047 : RISCVExtension<1, 0,1048 "Obviating Memory-Management Instructions after Marking PTEs Valid">;1049 1050def FeatureStdExtSha1051 : RISCVExtension<1, 0, "Augmented Hypervisor",1052 [FeatureStdExtH, FeatureStdExtSsstateen, FeatureStdExtShcounterenw,1053 FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd,1054 FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>;1055 1056def FeatureStdExtSvukte1057 : RISCVExperimentalExtension<0, 3,1058 "Address-Independent Latency of User-Mode Faults to Supervisor Addresses">;1059 1060// Pointer Masking extensions1061 1062// A supervisor-level extension that provides pointer masking for the next lower1063// privilege mode (U-mode), and for VS- and VU-modes if the H extension is1064// present.1065def FeatureStdExtSsnpm1066 : RISCVExtension<1, 0,1067 "Supervisor-level Pointer Masking for next lower privilege mode">;1068 1069// A machine-level extension that provides pointer masking for the next lower1070// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).1071def FeatureStdExtSmnpm1072 : RISCVExtension<1, 0,1073 "Machine-level Pointer Masking for next lower privilege mode">;1074 1075// A machine-level extension that provides pointer masking for M-mode.1076def FeatureStdExtSmmpm1077 : RISCVExtension<1, 0,1078 "Machine-level Pointer Masking for M-mode">;1079 1080// An extension that indicates that there is pointer-masking support available1081// in supervisor mode, with some facility provided in the supervisor execution1082// environment to control pointer masking.1083def FeatureStdExtSspm1084 : RISCVExtension<1, 0,1085 "Indicates Supervisor-mode Pointer Masking">;1086 1087// An extension that indicates that there is pointer-masking support available1088// in user mode, with some facility provided in the application execution1089// environment to control pointer masking.1090def FeatureStdExtSupm1091 : RISCVExtension<1, 0,1092 "Indicates User-mode Pointer Masking">;1093 1094def FeatureStdExtSmctr1095 : RISCVExtension<1, 0,1096 "Control Transfer Records Machine Level",1097 [FeatureStdExtSscsrind]>;1098def FeatureStdExtSsctr1099 : RISCVExtension<1, 0,1100 "Control Transfer Records Supervisor Level",1101 [FeatureStdExtSscsrind]>;1102def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,1103 AssemblerPredicate<(any_of FeatureStdExtSmctr, FeatureStdExtSsctr),1104 "'Smctr' (Control Transfer Records Machine Level) or "1105 "'Ssctr' (Control Transfer Records Supervisor Level)">;1106 1107// Packed SIMD Extensions1108def FeatureStdExtP1109 : RISCVExperimentalExtension<0, 15,1110 "'Base P' (Packed SIMD)">;1111def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,1112 AssemblerPredicate<(all_of FeatureStdExtP),1113 "'Base P' (Packed SIMD)">;1114 1115def HasStdExtZbaOrP1116 : Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">,1117 AssemblerPredicate<(any_of FeatureStdExtZba, FeatureStdExtP),1118 "'Zba' (Address Generation Instructions) or "1119 "'Base P' (Packed-SIMD)">;1120 1121def HasStdExtZbbOrP1122 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtP()">,1123 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtP),1124 "'Zbb' (Basic Bit-Manipulation) or "1125 "'Base P' (Packed-SIMD)">;1126 1127def HasStdExtZbkbOrP1128 : Predicate<"Subtarget->hasStdExtZbkb() || Subtarget->hasStdExtP()">,1129 AssemblerPredicate<(any_of FeatureStdExtZbkb, FeatureStdExtP),1130 "'Zbkb' (Bitmanip instructions for Cryptography) or "1131 "'Base P' (Packed-SIMD)">;1132 1133def HasStdExtZbbOrZbkbOrP1134 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb() || "1135 "Subtarget->hasStdExtP()">,1136 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb, FeatureStdExtP),1137 "'Zbb' (Basic Bit-Manipulation) or "1138 "'Zbkb' (Bitmanip instructions for Cryptography) or "1139 "'Base P' (Packed-SIMD)">;1140 1141//===----------------------------------------------------------------------===//1142// Vendor extensions1143//===----------------------------------------------------------------------===//1144 1145// Ventana Extensions1146 1147def FeatureVendorXVentanaCondOps1148 : RISCVExtension<1, 0, "Ventana Conditional Ops">;1149def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,1150 AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),1151 "'XVentanaCondOps' (Ventana Conditional Ops)">;1152 1153// T-Head Extensions1154 1155def FeatureVendorXTHeadBa1156 : RISCVExtension<1, 0,1157 "T-Head address calculation instructions">;1158def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,1159 AssemblerPredicate<(all_of FeatureVendorXTHeadBa),1160 "'XTHeadBa' (T-Head address calculation instructions)">;1161 1162def FeatureVendorXTHeadBb1163 : RISCVExtension<1, 0,1164 "T-Head basic bit-manipulation instructions">;1165def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,1166 AssemblerPredicate<(all_of FeatureVendorXTHeadBb),1167 "'XTHeadBb' (T-Head basic bit-manipulation instructions)">;1168 1169def FeatureVendorXTHeadBs1170 : RISCVExtension<1, 0,1171 "T-Head single-bit instructions">;1172def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,1173 AssemblerPredicate<(all_of FeatureVendorXTHeadBs),1174 "'XTHeadBs' (T-Head single-bit instructions)">;1175 1176def FeatureVendorXTHeadCondMov1177 : RISCVExtension<1, 0,1178 "T-Head conditional move instructions">;1179def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,1180 AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),1181 "'XTHeadCondMov' (T-Head conditional move instructions)">;1182 1183def FeatureVendorXTHeadCmo1184 : RISCVExtension<1, 0,1185 "T-Head cache management instructions">;1186def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,1187 AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),1188 "'XTHeadCmo' (T-Head cache management instructions)">;1189 1190def FeatureVendorXTHeadFMemIdx1191 : RISCVExtension<1, 0,1192 "T-Head FP Indexed Memory Operations">;1193def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,1194 AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),1195 "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">;1196 1197def FeatureVendorXTHeadMac1198 : RISCVExtension<1, 0,1199 "T-Head Multiply-Accumulate Instructions">;1200def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,1201 AssemblerPredicate<(all_of FeatureVendorXTHeadMac),1202 "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)">;1203 1204def FeatureVendorXTHeadMemIdx1205 : RISCVExtension<1, 0,1206 "T-Head Indexed Memory Operations">;1207def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,1208 AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),1209 "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">;1210 1211def FeatureVendorXTHeadMemPair1212 : RISCVExtension<1, 0,1213 "T-Head two-GPR Memory Operations">;1214def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,1215 AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),1216 "'XTHeadMemPair' (T-Head two-GPR Memory Operations)">;1217 1218def FeatureVendorXTHeadSync1219 : RISCVExtension<1, 0,1220 "T-Head multicore synchronization instructions">;1221def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,1222 AssemblerPredicate<(all_of FeatureVendorXTHeadSync),1223 "'XTHeadSync' (T-Head multicore synchronization instructions)">;1224 1225def FeatureVendorXTHeadVdot1226 : RISCVExtension<1, 0,1227 "T-Head Vector Extensions for Dot",1228 [FeatureStdExtV]>;1229def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,1230 AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),1231 "'XTHeadVdot' (T-Head Vector Extensions for Dot)">;1232 1233// SiFive Extensions1234 1235def FeatureVendorXSfvcp1236 : RISCVExtension<1, 0,1237 "SiFive Custom Vector Coprocessor Interface Instructions",1238 [FeatureStdExtZve32x]>;1239def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,1240 AssemblerPredicate<(all_of FeatureVendorXSfvcp),1241 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;1242 1243def FeatureVendorXSfmmbase1244 : RISCVExtension<0, 6,1245 "All non arithmetic instructions for all TEWs and sf.vtzero",1246 [FeatureStdExtZve32x]>;1247def HasVendorXSfmmbase : Predicate<"Subtarget->hasVendorXSfmmbase()">,1248 AssemblerPredicate<(all_of FeatureVendorXSfmmbase),1249 "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)">;1250 1251def FeatureVendorXSfmm32a8f1252 : RISCVExtension<0, 6,1253 "TEW=32-bit accumulation, operands - float: fp8",1254 [FeatureVendorXSfmmbase, FeatureStdExtZve32f]>;1255def HasVendorXSfmm32a8f : Predicate<"Subtarget->hasVendorXSfmm32a8f()">,1256 AssemblerPredicate<(all_of FeatureVendorXSfmm32a8f),1257 "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)">;1258 1259def FeatureVendorXSfmm32a16f1260 : RISCVExtension<0, 6,1261 "TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)",1262 [FeatureVendorXSfmmbase, FeatureStdExtZve32f]>;1263 1264def FeatureVendorXSfmm32a32f1265 : RISCVExtension<0, 6,1266 "TEW=32-bit accumulation, operands - float: 32b",1267 [FeatureVendorXSfmmbase, FeatureStdExtZve32f]>;1268 1269def FeatureVendorXSfmm32a8i1270 : RISCVExtension<0, 6,1271 "TEW=32-bit accumulation, operands - int: 8b",1272 [FeatureVendorXSfmmbase]>;1273def HasVendorXSfmm32a8i : Predicate<"Subtarget->hasVendorXSfmm32a8i()">,1274 AssemblerPredicate<(all_of FeatureVendorXSfmm32a8i),1275 "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)">;1276 1277def FeatureVendorXSfmm64a64f1278 : RISCVExtension<0, 6,1279 "TEW=64-bit accumulation, operands - float: fp64",1280 [FeatureVendorXSfmmbase, FeatureStdExtZve64d]>;1281def HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f1282 : Predicate<"Subtarget->hasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f()">,1283 AssemblerPredicate<(any_of FeatureVendorXSfmm32a16f,1284 FeatureVendorXSfmm32a32f,1285 FeatureVendorXSfmm64a64f),1286 "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)), or "1287 "'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b), or "1288 "'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)">;1289 1290def FeatureVendorXSfmm16t1291 : RISCVExtension<0, 6,1292 "TE=16 configuration",1293 [FeatureVendorXSfmmbase, FeatureStdExtZvl64b], "XSfmmTE", "16">;1294 1295def FeatureVendorXSfmm32t1296 : RISCVExtension<0, 6,1297 "TE=32 configuration",1298 [FeatureVendorXSfmmbase, FeatureStdExtZvl128b], "XSfmmTE", "32">;1299 1300def FeatureVendorXSfmm64t1301 : RISCVExtension<0, 6,1302 "TE=64 configuration",1303 [FeatureVendorXSfmmbase, FeatureStdExtZvl256b], "XSfmmTE", "64">;1304 1305def FeatureVendorXSfmm128t1306 : RISCVExtension<0, 6,1307 "TE=128 configuration",1308 [FeatureVendorXSfmmbase, FeatureStdExtZvl512b], "XSfmmTE", "128">;1309 1310def FeatureVendorXSfvqmaccdod1311 : RISCVExtension<1, 0,1312 "SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)",1313 [FeatureStdExtZve32x, FeatureStdExtZvl128b]>;1314def HasVendorXSfvqmaccdod1315 : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">,1316 AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod),1317 "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;1318 1319def FeatureVendorXSfvqmaccqoq1320 : RISCVExtension<1, 0,1321 "SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)",1322 [FeatureStdExtZve32x, FeatureStdExtZvl256b]>;1323def HasVendorXSfvqmaccqoq1324 : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">,1325 AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq),1326 "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">;1327 1328def FeatureVendorXSfvfwmaccqqq1329 : RISCVExtension<1, 0,1330 "SiFive Matrix Multiply Accumulate Instruction (4-by-4)",1331 [FeatureStdExtZvfbfmin, FeatureStdExtZvl128b]>;1332def HasVendorXSfvfwmaccqqq1333 : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">,1334 AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq),1335 "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))">;1336 1337def FeatureVendorXSfvfnrclipxfqf1338 : RISCVExtension<1, 0,1339 "SiFive FP32-to-int8 Ranged Clip Instructions",1340 [FeatureStdExtZve32f]>;1341def HasVendorXSfvfnrclipxfqf1342 : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">,1343 AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),1344 "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;1345 1346// Note: XSfvfbfexp16e depends on either Zvfbfmin _or_ Zvfbfa, which cannot be expressed here in1347// TableGen. Instead, we check that in RISCVISAInfo.1348def FeatureVendorXSfvfbfexp16e1349 : RISCVExtension<0, 5,1350 "SiFive Vector Floating-Point Exponential Function Instruction, BFloat16">;1351def HasVendorXSfvfbfexp16e : Predicate<"Subtarget->hasVendorXSfvfbfexp16e()">;1352 1353def FeatureVendorXSfvfexp16e1354 : RISCVExtension<0, 5,1355 "SiFive Vector Floating-Point Exponential Function Instruction, Half Precision",1356 [FeatureStdExtZvfh]>;1357def HasVendorXSfvfexp16e : Predicate<"Subtarget->hasVendorXSfvfexp16e()">;1358 1359def FeatureVendorXSfvfexp32e1360 : RISCVExtension<0, 5,1361 "SiFive Vector Floating-Point Exponential Function Instruction, Single Precision",1362 [FeatureStdExtZve32f]>;1363def HasVendorXSfvfexp32e : Predicate<"Subtarget->hasVendorXSfvfexp32e()">;1364 1365def HasVendorXSfvfexpAnyFloat : Predicate<"Subtarget->hasVendorXSfvfexp16e() || Subtarget->hasVendorXSfvfexp32e()">;1366def HasVendorXSfvfexpAny : Predicate<"Subtarget->hasVendorXSfvfbfexp16e() || Subtarget->hasVendorXSfvfexp16e() || Subtarget->hasVendorXSfvfexp32e()">,1367 AssemblerPredicate<(any_of FeatureVendorXSfvfbfexp16e, FeatureVendorXSfvfexp16e, FeatureVendorXSfvfexp32e),1368 "'Xsfvfbfexp16e', 'Xsfvfexp16e', or 'Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction)">;1369 1370def FeatureVendorXSfvfexpa1371 : RISCVExtension<0, 2,1372 "SiFive Vector Floating-Point Exponential Approximation Instruction",1373 [FeatureStdExtZve32f]>;1374def HasVendorXSfvfexpa : Predicate<"Subtarget->hasVendorXSfvfexpa()">,1375 AssemblerPredicate<(all_of FeatureVendorXSfvfexpa),1376 "'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)">;1377 1378def FeatureVendorXSfvfexpa64e1379 : RISCVExtension<0, 2,1380 "SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision",1381 [FeatureVendorXSfvfexpa, FeatureStdExtZve64d]>;1382def HasVendorXSfvfexpa64e : Predicate<"Subtarget->hasVendorXSfvfexpa64e()">;1383 1384def FeatureVendorXSiFivecdiscarddlone1385 : RISCVExtension<1, 0,1386 "SiFive sf.cdiscard.d.l1 Instruction", []>;1387def HasVendorXSiFivecdiscarddlone1388 : Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,1389 AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),1390 "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;1391 1392def FeatureVendorXSiFivecflushdlone1393 : RISCVExtension<1, 0,1394 "SiFive sf.cflush.d.l1 Instruction", []>;1395def HasVendorXSiFivecflushdlone1396 : Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,1397 AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),1398 "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;1399 1400def FeatureVendorXSfcease1401 : RISCVExtension<1, 0,1402 "SiFive sf.cease Instruction", []>;1403def HasVendorXSfcease1404 : Predicate<"Subtarget->hasVendorXSfcease()">,1405 AssemblerPredicate<(all_of FeatureVendorXSfcease),1406 "'XSfcease' (SiFive sf.cease Instruction)">;1407 1408def FeatureVendorXSfmclic1409 : RISCVExperimentalExtension<0, 1,1410 "SiFive CLIC Machine-mode CSRs">;1411 1412def FeatureVendorXSfsclic1413 : RISCVExperimentalExtension<0, 1,1414 "SiFive CLIC Supervisor-mode CSRs">;1415 1416// Core-V Extensions1417 1418def FeatureVendorXCVelw1419 : RISCVExtension<1, 0, "CORE-V Event Load Word">;1420def HasVendorXCVelw1421 : Predicate<"Subtarget->hasVendorXCVelw()">,1422 AssemblerPredicate<(any_of FeatureVendorXCVelw),1423 "'XCVelw' (CORE-V Event Load Word)">;1424 1425def FeatureVendorXCVbitmanip1426 : RISCVExtension<1, 0, "CORE-V Bit Manipulation">;1427def HasVendorXCVbitmanip1428 : Predicate<"Subtarget->hasVendorXCVbitmanip()">,1429 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),1430 "'XCVbitmanip' (CORE-V Bit Manipulation)">;1431 1432def FeatureVendorXCVmac1433 : RISCVExtension<1, 0, "CORE-V Multiply-Accumulate">;1434def HasVendorXCVmac1435 : Predicate<"Subtarget->hasVendorXCVmac()">,1436 AssemblerPredicate<(all_of FeatureVendorXCVmac),1437 "'XCVmac' (CORE-V Multiply-Accumulate)">;1438 1439def FeatureVendorXCVmem1440 : RISCVExtension<1, 0, "CORE-V Post-incrementing Load & Store">;1441def HasVendorXCVmem1442 : Predicate<"Subtarget->hasVendorXCVmem()">,1443 AssemblerPredicate<(any_of FeatureVendorXCVmem),1444 "'XCVmem' (CORE-V Post-incrementing Load & Store)">;1445 1446def FeatureVendorXCValu1447 : RISCVExtension<1, 0, "CORE-V ALU Operations">;1448def HasVendorXCValu1449 : Predicate<"Subtarget->hasVendorXCValu()">,1450 AssemblerPredicate<(all_of FeatureVendorXCValu),1451 "'XCValu' (CORE-V ALU Operations)">;1452 1453def FeatureVendorXCVsimd1454 : RISCVExtension<1, 0, "CORE-V SIMD ALU">;1455def HasVendorXCVsimd1456 : Predicate<"Subtarget->hasVendorXCVsimd()">,1457 AssemblerPredicate<(any_of FeatureVendorXCVsimd),1458 "'XCVsimd' (CORE-V SIMD ALU)">;1459 1460def FeatureVendorXCVbi1461 : RISCVExtension<1, 0, "CORE-V Immediate Branching">;1462def HasVendorXCVbi1463 : Predicate<"Subtarget->hasVendorXCVbi()">,1464 AssemblerPredicate<(all_of FeatureVendorXCVbi),1465 "'XCVbi' (CORE-V Immediate Branching)">;1466// MIPS Extensions1467 1468def FeatureVendorXMIPSCMov1469 : RISCVExtension<1, 0, "MIPS conditional move instruction (mips.ccmov)">;1470def HasVendorXMIPSCMov1471 : Predicate<"Subtarget->hasVendorXMIPSCMov()">,1472 AssemblerPredicate<(all_of FeatureVendorXMIPSCMov),1473 "'Xmipscmov' ('mips.ccmov' instruction)">;1474def UseMIPSCCMovInsn : Predicate<"Subtarget->useMIPSCCMovInsn()">;1475 1476def FeatureVendorXMIPSLSP1477 : RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;1478def HasVendorXMIPSLSP1479 : Predicate<"Subtarget->hasVendorXMIPSLSP()">,1480 AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),1481 "'Xmipslsp' (load and store pair instructions)">;1482 1483def FeatureVendorXMIPSCBOP : RISCVExtension<1, 0, "MIPS Software Prefetch">;1484def HasVendorXMIPSCBOP1485 : Predicate<"Subtarget->hasVendorXMIPSCBOP()">,1486 AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP),1487 "'Xmipscbop' (MIPS hardware prefetch)">;1488def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;1489 1490def FeatureVendorXMIPSEXECTL : RISCVExtension<1, 0, "MIPS execution control">;1491def HasVendorXMIPSEXECTL1492 : Predicate<"Subtarget->hasVendorXMIPSEXECTL()">,1493 AssemblerPredicate<(all_of FeatureVendorXMIPSEXECTL),1494 "'Xmipsexectl' (MIPS execution control)">;1495 1496// WCH / Nanjing Qinheng Microelectronics Extension(s)1497 1498def FeatureVendorXwchc1499 : RISCVExtension<2, 2,1500 "WCH/QingKe additional compressed opcodes",1501 [FeatureStdExtZca]>;1502def HasVendorXwchc1503 : Predicate<"Subtarget->hasVendorXwchc()">,1504 AssemblerPredicate<(all_of FeatureVendorXwchc),1505 "'Xwchc' (WCH/QingKe additional compressed opcodes)">;1506 1507// Qualcomm Extensions1508 1509def FeatureVendorXqccmp1510 : RISCVExperimentalExtension<0, 3,1511 "Qualcomm 16-bit Push/Pop and Double Moves",1512 [FeatureStdExtZca]>;1513def HasVendorXqccmp1514 : Predicate<"Subtarget->hasVendorXqccmp()">,1515 AssemblerPredicate<(all_of FeatureVendorXqccmp),1516 "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;1517 1518def FeatureVendorXqcia1519 : RISCVExperimentalExtension<0, 7, "Qualcomm uC Arithmetic Extension">;1520def HasVendorXqcia1521 : Predicate<"Subtarget->hasVendorXqcia()">,1522 AssemblerPredicate<(all_of FeatureVendorXqcia),1523 "'Xqcia' (Qualcomm uC Arithmetic Extension)">;1524 1525def FeatureVendorXqciac1526 : RISCVExperimentalExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension",1527 [FeatureStdExtZca]>;1528def HasVendorXqciac1529 : Predicate<"Subtarget->hasVendorXqciac()">,1530 AssemblerPredicate<(all_of FeatureVendorXqciac),1531 "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">;1532 1533def FeatureVendorXqcibi1534 : RISCVExperimentalExtension<0, 2, "Qualcomm uC Branch Immediate Extension",1535 [FeatureStdExtZca]>;1536def HasVendorXqcibi1537 : Predicate<"Subtarget->hasVendorXqcibi()">,1538 AssemblerPredicate<(all_of FeatureVendorXqcibi),1539 "'Xqcibi' (Qualcomm uC Branch Immediate Extension)">;1540 1541def FeatureVendorXqcibm1542 : RISCVExperimentalExtension<0, 8, "Qualcomm uC Bit Manipulation Extension",1543 [FeatureStdExtZca]>;1544def HasVendorXqcibm1545 : Predicate<"Subtarget->hasVendorXqcibm()">,1546 AssemblerPredicate<(all_of FeatureVendorXqcibm),1547 "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)">;1548 1549def FeatureVendorXqcicli1550 : RISCVExperimentalExtension<0, 3,1551 "Qualcomm uC Conditional Load Immediate Extension">;1552def HasVendorXqcicli1553 : Predicate<"Subtarget->hasVendorXqcicli()">,1554 AssemblerPredicate<(all_of FeatureVendorXqcicli),1555 "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">;1556 1557def FeatureVendorXqcicm1558 : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension",1559 [FeatureStdExtZca]>;1560def HasVendorXqcicm1561 : Predicate<"Subtarget->hasVendorXqcicm()">,1562 AssemblerPredicate<(all_of FeatureVendorXqcicm),1563 "'Xqcicm' (Qualcomm uC Conditional Move Extension)">;1564def NoVendorXqcicm1565 : Predicate<"!Subtarget->hasVendorXqcicm()">;1566 1567def FeatureVendorXqcics1568 : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">;1569def HasVendorXqcics1570 : Predicate<"Subtarget->hasVendorXqcics()">,1571 AssemblerPredicate<(all_of FeatureVendorXqcics),1572 "'Xqcics' (Qualcomm uC Conditional Select Extension)">;1573def NoVendorXqcics1574 : Predicate<"!Subtarget->hasVendorXqcics()">;1575 1576def FeatureVendorXqcicsr1577 : RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">;1578def HasVendorXqcicsr1579 : Predicate<"Subtarget->hasVendorXqcicsr()">,1580 AssemblerPredicate<(all_of FeatureVendorXqcicsr),1581 "'Xqcicsr' (Qualcomm uC CSR Extension)">;1582 1583def FeatureVendorXqciint1584 : RISCVExperimentalExtension<0, 10, "Qualcomm uC Interrupts Extension",1585 [FeatureStdExtZca]>;1586def HasVendorXqciint1587 : Predicate<"Subtarget->hasVendorXqciint()">,1588 AssemblerPredicate<(all_of FeatureVendorXqciint),1589 "'Xqciint' (Qualcomm uC Interrupts Extension)">;1590 1591def FeatureVendorXqciio1592 : RISCVExperimentalExtension<0, 1, "Qualcomm uC External Input Output Extension">;1593def HasVendorXqciio1594 : Predicate<"Subtarget->hasVendorXqciio()">,1595 AssemblerPredicate<(all_of FeatureVendorXqciio),1596 "'Xqciio' (Qualcomm uC External Input Output Extension)">;1597 1598def FeatureVendorXqcilb1599 : RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension",1600 [FeatureStdExtZca]>;1601def HasVendorXqcilb1602 : Predicate<"Subtarget->hasVendorXqcilb()">,1603 AssemblerPredicate<(all_of FeatureVendorXqcilb),1604 "'Xqcilb' (Qualcomm uC Long Branch Extension)">;1605 1606def FeatureVendorXqcili1607 : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",1608 [FeatureStdExtZca]>;1609def HasVendorXqcili1610 : Predicate<"Subtarget->hasVendorXqcili()">,1611 AssemblerPredicate<(all_of FeatureVendorXqcili),1612 "'Xqcili' (Qualcomm uC Load Large Immediate Extension)">;1613 1614def FeatureVendorXqcilia1615 : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",1616 [FeatureStdExtZca]>;1617def HasVendorXqcilia1618 : Predicate<"Subtarget->hasVendorXqcilia()">,1619 AssemblerPredicate<(all_of FeatureVendorXqcilia),1620 "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;1621 1622def FeatureVendorXqcilo1623 : RISCVExperimentalExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension",1624 [FeatureStdExtZca]>;1625def HasVendorXqcilo1626 : Predicate<"Subtarget->hasVendorXqcilo()">,1627 AssemblerPredicate<(all_of FeatureVendorXqcilo),1628 "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;1629 1630def FeatureVendorXqcilsm1631 : RISCVExperimentalExtension<0, 6,1632 "Qualcomm uC Load Store Multiple Extension">;1633def HasVendorXqcilsm1634 : Predicate<"Subtarget->hasVendorXqcilsm()">,1635 AssemblerPredicate<(all_of FeatureVendorXqcilsm),1636 "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">;1637 1638def FeatureVendorXqcisim1639 : RISCVExperimentalExtension<0, 2, "Qualcomm uC Simulation Hint Extension",1640 [FeatureStdExtZca]>;1641def HasVendorXqcisim1642 : Predicate<"Subtarget->hasVendorXqcisim()">,1643 AssemblerPredicate<(all_of FeatureVendorXqcisim),1644 "'Xqcisim' (Qualcomm uC Simulation Hint Extension)">;1645 1646def FeatureVendorXqcisls1647 : RISCVExperimentalExtension<0, 2,1648 "Qualcomm uC Scaled Load Store Extension">;1649def HasVendorXqcisls1650 : Predicate<"Subtarget->hasVendorXqcisls()">,1651 AssemblerPredicate<(all_of FeatureVendorXqcisls),1652 "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;1653 1654def FeatureVendorXqcisync1655 : RISCVExperimentalExtension<0, 3, "Qualcomm uC Sync Delay Extension",1656 [FeatureStdExtZca]>;1657def HasVendorXqcisync1658 : Predicate<"Subtarget->hasVendorXqcisync()">,1659 AssemblerPredicate<(all_of FeatureVendorXqcisync),1660 "'Xqcisync' (Qualcomm uC Sync Delay Extension)">;1661 1662// Rivos Extension(s)1663 1664def FeatureVendorXRivosVisni1665 : RISCVExperimentalExtension<0, 1, "Rivos Vector Integer Small New">;1666def HasVendorXRivosVisni1667 : Predicate<"Subtarget->hasVendorXRivosVisni()">,1668 AssemblerPredicate<(all_of FeatureVendorXRivosVisni),1669 "'XRivosVisni' (Rivos Vector Integer Small New)">;1670 1671def FeatureVendorXRivosVizip1672 : RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;1673def HasVendorXRivosVizip1674 : Predicate<"Subtarget->hasVendorXRivosVizip()">,1675 AssemblerPredicate<(all_of FeatureVendorXRivosVizip),1676 "'XRivosVizip' (Rivos Vector Register Zips)">;1677 1678// Andes Extension(s)1679 1680def FeatureVendorXAndesPerf1681 : RISCVExtension<5, 0, "Andes Performance Extension">;1682def HasVendorXAndesPerf1683 : Predicate<"Subtarget->hasVendorXAndesPerf()">,1684 AssemblerPredicate<(all_of FeatureVendorXAndesPerf),1685 "'XAndesPerf' (Andes Performance Extension)">;1686 1687def FeatureVendorXAndesBFHCvt1688 : RISCVExtension<5, 0, "Andes Scalar BFLOAT16 Conversion Extension",1689 [FeatureStdExtF]>;1690def HasVendorXAndesBFHCvt1691 : Predicate<"Subtarget->hasVendorXAndesBFHCvt()">,1692 AssemblerPredicate<(all_of FeatureVendorXAndesBFHCvt),1693 "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)">;1694 1695def FeatureVendorXAndesVBFHCvt1696 : RISCVExtension<5, 0, "Andes Vector BFLOAT16 Conversion Extension",1697 [FeatureStdExtZve32f]>;1698def HasVendorXAndesVBFHCvt1699 : Predicate<"Subtarget->hasVendorXAndesVBFHCvt()">,1700 AssemblerPredicate<(all_of FeatureVendorXAndesVBFHCvt),1701 "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">;1702 1703def FeatureVendorXAndesVSIntH1704 : RISCVExtension<5, 0, "Andes Vector Small INT Handling Extension",1705 [FeatureStdExtZve32x]>;1706def HasVendorXAndesVSIntH1707 : Predicate<"Subtarget->hasVendorXAndesVSIntH()">,1708 AssemblerPredicate<(all_of FeatureVendorXAndesVSIntH),1709 "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)">;1710 1711def FeatureVendorXAndesVSIntLoad1712 : RISCVExtension<5, 0, "Andes Vector INT4 Load Extension",1713 [FeatureStdExtZve32x]>;1714def HasVendorXAndesVSIntLoad1715 : Predicate<"Subtarget->hasVendorXAndesVSIntLoad()">,1716 AssemblerPredicate<(all_of FeatureVendorXAndesVSIntLoad),1717 "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)">;1718 1719def FeatureVendorXAndesVPackFPH1720 : RISCVExtension<5, 0,1721 "Andes Vector Packed FP16 Extension", [FeatureStdExtF]>;1722def HasVendorXAndesVPackFPH1723 : Predicate<"Subtarget->hasVendorXAndesVPackFPH()">,1724 AssemblerPredicate<(all_of FeatureVendorXAndesVPackFPH),1725 "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)">;1726 1727def FeatureVendorXAndesVDot1728 : RISCVExtension<5, 0, "Andes Vector Dot Product Extension",1729 [FeatureStdExtZve32x]>;1730def HasVendorXAndesVDot1731 : Predicate<"Subtarget->hasVendorXAndesVDot()">,1732 AssemblerPredicate<(all_of FeatureVendorXAndesVDot),1733 "'XAndesVDot' (Andes Vector Dot Product Extension)">;1734 1735def FeatureVendorXSMTVDot1736 : RISCVExtension<1, 0, "SpacemiT Vector Dot Product Extension",1737 [FeatureStdExtZve32f]>;1738def HasVendorXSMTVDot1739 : Predicate<"Subtarget->hasVendorXSMTVDot()">,1740 AssemblerPredicate<(all_of FeatureVendorXSMTVDot),1741 "'XSMTVDot' (SpacemiT Vector Dot Product Extension)">;1742 1743//===----------------------------------------------------------------------===//1744// LLVM specific features and extensions1745//===----------------------------------------------------------------------===//1746 1747// Feature32Bit exists to mark CPUs that support RV32 to distinguish them from1748// tuning CPU names.1749def Feature32Bit1750 : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;1751def Feature64Bit1752 : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;1753def IsRV64 : Predicate<"Subtarget->is64Bit()">,1754 AssemblerPredicate<(all_of Feature64Bit),1755 "RV64I Base Instruction Set">;1756def IsRV32 : Predicate<"!Subtarget->is64Bit()">,1757 AssemblerPredicate<(all_of (not Feature64Bit)),1758 "RV32I Base Instruction Set">;1759 1760defvar RV32 = DefaultMode;1761def RV64 : HwMode<[IsRV64]>;1762 1763def FeatureRelax1764 : SubtargetFeature<"relax", "EnableLinkerRelax", "true",1765 "Enable Linker relaxation.">;1766 1767def FeatureExactAssembly1768 : SubtargetFeature<"exact-asm", "EnableExactAssembly", "true",1769 "Enable Exact Assembly (Disables Compression and Relaxation)">;1770 1771foreach i = {1-31} in1772 def FeatureReserveX#i :1773 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",1774 "true", "Reserve X"#i>;1775 1776def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",1777 "true", "Enable save/restore.">;1778 1779def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence",1780 "EnableTrailingSeqCstFence",1781 "false",1782 "Disable trailing fence for seq-cst store.">;1783 1784def FeatureUnalignedScalarMem1785 : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",1786 "true", "Has reasonably performant unaligned scalar "1787 "loads and stores">;1788 1789def FeatureUnalignedVectorMem1790 : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",1791 "true", "Has reasonably performant unaligned vector "1792 "loads and stores">;1793 1794def TuneNLogNVRGather1795 : SubtargetFeature<"log-vrgather", "RISCVVRGatherCostModel", "NLog2N",1796 "Has vrgather.vv with LMUL*log2(LMUL) latency">;1797 1798def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",1799 "UsePostRAScheduler", "true", "Schedule again after register allocation">;1800 1801def TuneDisableMISchedLoadClustering : SubtargetFeature<"disable-misched-load-clustering",1802 "EnableMISchedLoadClustering", "false", "Disable load clustering in the machine scheduler">;1803 1804def TuneDisableMISchedStoreClustering : SubtargetFeature<"disable-misched-store-clustering",1805 "EnableMISchedStoreClustering", "false", "Disable store clustering in the machine scheduler">;1806 1807def TuneDisablePostMISchedLoadClustering : SubtargetFeature<"disable-postmisched-load-clustering",1808 "EnablePostMISchedLoadClustering", "false", "Disable PostRA load clustering in the machine scheduler">;1809 1810def TuneDisablePostMISchedStoreClustering : SubtargetFeature<"disable-postmisched-store-clustering",1811 "EnablePostMISchedStoreClustering", "false", "Disable PostRA store clustering in the machine scheduler">;1812 1813def TuneDisableLatencySchedHeuristic1814 : SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",1815 "Disable latency scheduling heuristic">;1816 1817def TunePredictableSelectIsExpensive1818 : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true",1819 "Prefer likely predicted branches over selects">;1820 1821def TuneOptimizedZeroStrideLoad1822 : SubtargetFeature<"optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",1823 "true", "Optimized (perform fewer memory operations)"1824 "zero-stride vector load">;1825 1826foreach nf = {2-8} in1827 def TuneOptimizedNF#nf#SegmentLoadStore :1828 SubtargetFeature<"optimized-nf"#nf#"-segment-load-store",1829 "HasOptimizedNF"#nf#"SegmentLoadStore",1830 "true", "vlseg"#nf#"eN.v and vsseg"#nf#"eN.v are "1831 "implemented as a wide memory op and shuffle">;1832 1833def TuneVLDependentLatency1834 : SubtargetFeature<"vl-dependent-latency", "HasVLDependentLatency", "true",1835 "Latency of vector instructions is dependent on the "1836 "dynamic value of vl">;1837 1838def Experimental1839 : SubtargetFeature<"experimental", "HasExperimental",1840 "true", "Experimental intrinsics">;1841 1842// Some vector hardware implementations do not process all VLEN bits in parallel1843// and instead split over multiple cycles. DLEN refers to the datapath width1844// that can be done in parallel.1845def TuneDLenFactor21846 : SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",1847 "Vector unit DLEN(data path width) is half of VLEN">;1848 1849def TuneNoDefaultUnroll1850 : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",1851 "Disable default unroll preference.">;1852 1853// Many Microarchitectures are able to fuse a branch over a single instruction1854// with the branched-over instruction. We call this fusion "short forward1855// branches".1856//1857// We can do this for a variety of instruction groups, depending on the1858// microarch. We broadly group these by their scheduler class:1859// - IALU: RVI Integer instructions, plus ANDN/ORN/XNOR (Zbb/Zbkb)1860// - IMinMax: Zbb MIN(U)/MAX(U)1861// - IMul: MUL1862//1863// We make the simplifying assumption that any microarches that implement1864// any "short forward branches" can do the IALU fusions, and can opt into1865// the other fusions they implement.1866//1867// The important Pseudo used by all these instructions requires the IALU1868// short forward branches.1869//1870// Vendor-specific short-forward-branch opts may be added under IALU, as1871// the vendor-specific instructions should only be enabled for vendor1872// cores.1873def TuneShortForwardBranchIALU1874 : SubtargetFeature<"short-forward-branch-ialu", "HasShortForwardBranchIALU",1875 "true", "Enable short forward branch optimization for RVI base instructions">;1876def HasShortForwardBranchIALU : Predicate<"Subtarget->hasShortForwardBranchIALU()">;1877def NoShortForwardBranch : Predicate<"!Subtarget->hasShortForwardBranchIALU()">;1878 1879def TuneShortForwardBranchIMinMax1880 : SubtargetFeature<"short-forward-branch-iminmax", "HasShortForwardBranchIMinMax",1881 "true", "Enable short forward branch optimization for MIN,MAX instructions in Zbb",1882 [TuneShortForwardBranchIALU]>;1883def HasShortForwardBranchIMinMax : Predicate<"Subtarget->hasShortForwardBranchIMinMax()">;1884 1885def TuneShortForwardBranchIMul1886 : SubtargetFeature<"short-forward-branch-imul", "HasShortForwardBranchIMul",1887 "true", "Enable short forward branch optimization for MUL instruction",1888 [TuneShortForwardBranchIALU]>;1889def HasShortForwardBranchIMul : Predicate<"Subtarget->hasShortForwardBranchIMul()">;1890 1891 1892// Some subtargets require a S2V transfer buffer to move scalars into vectors.1893// FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure.1894def TuneNoSinkSplatOperands1895 : SubtargetFeature<"no-sink-splat-operands", "SinkSplatOperands",1896 "false", "Disable sink splat operands to enable .vx, .vf,"1897 ".wx, and .wf instructions">;1898 1899def TunePreferWInst1900 : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true",1901 "Prefer instructions with W suffix">;1902 1903def TuneConditionalCompressedMoveFusion1904 : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion",1905 "true", "Enable branch+c.mv fusion">;1906def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">;1907def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">;1908 1909def TuneHasSingleElementVecFP641910 : SubtargetFeature<"single-element-vec-fp64", "HasSingleElementVectorFP64", "true",1911 "Certain vector FP64 operations produce a single result "1912 "element per cycle">;1913 1914def TuneMIPSP87001915 : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700",1916 "MIPS p8700 processor">;1917 1918def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",1919 "SiFive 7-Series processors">;1920 1921def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",1922 "Ventana Veyron-Series processors">;1923 1924def TuneAndes45 : SubtargetFeature<"andes45", "RISCVProcFamily", "Andes45",1925 "Andes 45-Series processors">;1926 1927def TuneVXRMPipelineFlush : SubtargetFeature<"vxrm-pipeline-flush", "HasVXRMPipelineFlush",1928 "true", "VXRM writes causes pipeline flush">;1929 1930def TunePreferVsetvliOverReadVLENB1931 : SubtargetFeature<"prefer-vsetvli-over-read-vlenb",1932 "PreferVsetvliOverReadVLENB",1933 "true",1934 "Prefer vsetvli over read vlenb CSR to calculate VLEN">;1935 1936// Assume that lock-free native-width atomics are available, even if the target1937// and operating system combination would not usually provide them. The user1938// is responsible for providing any necessary __sync implementations. Code1939// built with this feature is not ABI-compatible with code built without this1940// feature, if atomic variables are exposed across the ABI boundary.1941def FeatureForcedAtomics : SubtargetFeature<1942 "forced-atomics", "HasForcedAtomics", "true",1943 "Assume that lock-free native-width atomics are available">;1944def HasAtomicLdSt1945 : Predicate<"Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">;1946 1947// The RISC-V Unprivileged Architecture - ISA Volume 1 (Version: 20250508)1948// [https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf]1949// in section 13.3. Eventual Success of Store-Conditional Instructions, defines1950// _constrained_ LR/SC loops:1951// The dynamic code executed between the LR and SC instructions can only1952// contain instructions from the base ''I'' instruction set, excluding loads,1953// stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM1954// instructions. Compressed forms of the aforementioned ''I'' instructions in1955// the Zca and Zcb extensions are also permitted.1956// LR/SC loops that do not adhere to the above are _unconstrained_ LR/SC loops,1957// and success is implementation specific. For implementations which know that1958// non-base instructions (such as the ''B'' extension) will not violate any1959// forward progress guarantees, using these instructions to reduce the LR/SC1960// sequence length is desirable.1961def FeaturePermissiveZalrsc1962 : SubtargetFeature<1963 "permissive-zalrsc", "HasPermissiveZalrsc", "true",1964 "Implementation permits non-base instructions between LR/SC pairs">;1965 1966def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",1967 "AllowTaggedGlobals",1968 "true", "Use an instruction sequence for taking the address of a global "1969 "that allows a memory tag in the upper address bits">;1970