696 lines · plain
1//===-- RISCVInstrFormats.td - RISC-V Instruction Formats --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10//11// These instruction format definitions are structured to match the12// description in the RISC-V User-Level ISA specification as closely as13// possible. For instance, the specification describes instructions with the14// MSB (31st bit) on the left and the LSB (0th bit) on the right. This is15// reflected in the order of parameters to each instruction class.16//17// One area of divergence is in the description of immediates. The18// specification describes immediate encoding in terms of bit-slicing19// operations on the logical value represented. The immediate argument to20// these instruction formats instead represents the bit sequence that will be21// inserted into the instruction. e.g. although JAL's immediate is logically22// a 21-bit value (where the LSB is always zero), we describe it as an imm2023// to match how it is encoded.24//25//===----------------------------------------------------------------------===//26 27// Format specifies the encoding used by the instruction. This is used by28// RISCVMCCodeEmitter to determine which form of fixup to use. These29// definitions must be kept in-sync with RISCVBaseInfo.h.30class InstFormat<bits<5> val> {31 bits<5> Value = val;32}33def InstFormatPseudo : InstFormat<0>;34def InstFormatR : InstFormat<1>;35def InstFormatR4 : InstFormat<2>;36def InstFormatI : InstFormat<3>;37def InstFormatS : InstFormat<4>;38def InstFormatB : InstFormat<5>;39def InstFormatU : InstFormat<6>;40def InstFormatJ : InstFormat<7>;41def InstFormatCR : InstFormat<8>;42def InstFormatCI : InstFormat<9>;43def InstFormatCSS : InstFormat<10>;44def InstFormatCIW : InstFormat<11>;45def InstFormatCL : InstFormat<12>;46def InstFormatCS : InstFormat<13>;47def InstFormatCA : InstFormat<14>;48def InstFormatCB : InstFormat<15>;49def InstFormatCJ : InstFormat<16>;50def InstFormatCU : InstFormat<17>;51def InstFormatCLB : InstFormat<18>;52def InstFormatCLH : InstFormat<19>;53def InstFormatCSB : InstFormat<20>;54def InstFormatCSH : InstFormat<21>;55def InstFormatQC_EAI : InstFormat<22>;56def InstFormatQC_EI : InstFormat<23>;57def InstFormatQC_EB : InstFormat<24>;58def InstFormatQC_EJ : InstFormat<25>;59def InstFormatQC_ES : InstFormat<26>;60def InstFormatNDS_BRANCH_10 : InstFormat<27>;61def InstFormatOther : InstFormat<31>;62 63 64class RISCVVConstraint<bits<3> val> {65 bits<3> Value = val;66}67def NoConstraint : RISCVVConstraint<0b000>;68def VS2Constraint : RISCVVConstraint<0b001>;69def VS1Constraint : RISCVVConstraint<0b010>;70def VMConstraint : RISCVVConstraint<0b100>;71 72// Illegal instructions:73//74// * The destination vector register group for a masked vector instruction75// cannot overlap the source mask register (v0), unless the destination vector76// register is being written with a mask value (e.g., comparisons) or the77// scalar result of a reduction.78//79// * Widening: The destination EEW is greater than the source EEW, the source80// EMUL is at least 1. The destination vector register group cannot overlap81// with the source vector register groups besides the highest-numbered part of82// the destination register group.83//84// * Narrowing: The destination EEW is smaller than the source EEW. The85// destination vector register group cannot overlap with the source vector86// register groups besides the lowest-numbered part of the source register87// group.88//89// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the90// source register and, if masked, cannot overlap the mask register ('v0').91//92// * viota: The destination register cannot overlap the source register and,93// if masked, cannot overlap the mask register ('v0').94//95// * v[f]slide[1]up: The destination vector register group for vslideup cannot96// overlap the source vector register group.97//98// * vrgather: The destination vector register group cannot overlap with the99// source vector register groups.100//101// * vcompress: The destination vector register group cannot overlap the102// source vector register group or the source mask register103def WidenVNoMask : RISCVVConstraint<!or(VS2Constraint.Value,104 VS1Constraint.Value)>;105def WidenV : RISCVVConstraint<!or(VS2Constraint.Value,106 VS1Constraint.Value,107 VMConstraint.Value)>;108def WidenW : RISCVVConstraint<!or(VS1Constraint.Value,109 VMConstraint.Value)>;110def WidenCvt : RISCVVConstraint<!or(VS2Constraint.Value,111 VMConstraint.Value)>;112def Iota : RISCVVConstraint<!or(VS2Constraint.Value,113 VMConstraint.Value)>;114def SlideUp : RISCVVConstraint<!or(VS2Constraint.Value,115 VMConstraint.Value)>;116def Vrgather : RISCVVConstraint<!or(VS2Constraint.Value,117 VS1Constraint.Value,118 VMConstraint.Value)>;119def Vcompress : RISCVVConstraint<!or(VS2Constraint.Value,120 VS1Constraint.Value)>;121def Sha2Constraint : RISCVVConstraint<!or(VS2Constraint.Value,122 VS1Constraint.Value)>;123 124// The following opcode names match those given in Table 19.1 in the125// RISC-V User-level ISA specification ("RISC-V base opcode map").126class RISCVOpcode<string name, bits<7> val> {127 string Name = name;128 bits<7> Value = val;129}130def RISCVOpcodesList : GenericTable {131 let FilterClass = "RISCVOpcode";132 let Fields = [133 "Name", "Value"134 ];135 let PrimaryKey = [ "Value" ];136 let PrimaryKeyName = "lookupRISCVOpcodeByValue";137}138def lookupRISCVOpcodeByName : SearchIndex {139 let Table = RISCVOpcodesList;140 let Key = [ "Name" ];141}142def OPC_LOAD : RISCVOpcode<"LOAD", 0b0000011>;143def OPC_LOAD_FP : RISCVOpcode<"LOAD_FP", 0b0000111>;144def OPC_CUSTOM_0 : RISCVOpcode<"CUSTOM_0", 0b0001011>;145def OPC_MISC_MEM : RISCVOpcode<"MISC_MEM", 0b0001111>;146def OPC_OP_IMM : RISCVOpcode<"OP_IMM", 0b0010011>;147def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>;148def OPC_OP_IMM_32 : RISCVOpcode<"OP_IMM_32", 0b0011011>;149def OPC_STORE : RISCVOpcode<"STORE", 0b0100011>;150def OPC_STORE_FP : RISCVOpcode<"STORE_FP", 0b0100111>;151def OPC_CUSTOM_1 : RISCVOpcode<"CUSTOM_1", 0b0101011>;152def OPC_AMO : RISCVOpcode<"AMO", 0b0101111>;153def OPC_OP : RISCVOpcode<"OP", 0b0110011>;154def OPC_LUI : RISCVOpcode<"LUI", 0b0110111>;155def OPC_OP_32 : RISCVOpcode<"OP_32", 0b0111011>;156def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>;157def OPC_MSUB : RISCVOpcode<"MSUB", 0b1000111>;158def OPC_NMSUB : RISCVOpcode<"NMSUB", 0b1001011>;159def OPC_NMADD : RISCVOpcode<"NMADD", 0b1001111>;160def OPC_OP_FP : RISCVOpcode<"OP_FP", 0b1010011>;161def OPC_OP_V : RISCVOpcode<"OP_V", 0b1010111>;162def OPC_CUSTOM_2 : RISCVOpcode<"CUSTOM_2", 0b1011011>;163def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>;164def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;165def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>;166def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;167def OPC_OP_VE : RISCVOpcode<"OP_VE", 0b1110111>;168def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>;169 170class EltDeps<bit vl, bit mask> {171 bit VL = vl;172 bit Mask = mask;173}174 175def EltDepsNone : EltDeps<vl=0, mask=0>;176def EltDepsVL : EltDeps<vl=1, mask=0>;177def EltDepsMask : EltDeps<vl=0, mask=1>;178def EltDepsVLMask : EltDeps<vl=1, mask=1>;179 180class EEW<bits<2> val> {181 bits<2> Value = val;182}183def EEW1 : EEW<0>;184def EEWSEWx1 : EEW<1>;185def EEWSEWx2 : EEW<2>;186def EEWSEWx4 : EEW<3>;187 188class AltFmtType<bits<2> val> {189 bits<2> Value = val;190}191def DONT_CARE_ALTFMT : AltFmtType<0>;192def IS_NOT_ALTFMT : AltFmtType<1>;193def IS_ALTFMT : AltFmtType<2>;194 195class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,196 list<dag> pattern, InstFormat format> : Instruction {197 let Namespace = "RISCV";198 199 dag OutOperandList = outs;200 dag InOperandList = ins;201 let AsmString = opcodestr # !if(!empty(argstr), "", "\t" # argstr);202 let Pattern = pattern;203 204 InstFormat Format = format;205 206 let TSFlags{4-0} = Format.Value;207 208 // Defaults209 RISCVVConstraint RVVConstraint = NoConstraint;210 let TSFlags{7-5} = RVVConstraint.Value;211 212 bits<3> VLMul = 0;213 let TSFlags{10-8} = VLMul;214 215 bit IsTiedPseudo = 0;216 let TSFlags{11} = IsTiedPseudo;217 218 bit HasSEWOp = 0;219 let TSFlags{12} = HasSEWOp;220 221 bit HasVLOp = 0;222 let TSFlags{13} = HasVLOp;223 224 bit HasVecPolicyOp = 0;225 let TSFlags{14} = HasVecPolicyOp;226 227 bit IsRVVWideningReduction = 0;228 let TSFlags{15} = IsRVVWideningReduction;229 230 bit UsesMaskPolicy = 0;231 let TSFlags{16} = UsesMaskPolicy;232 233 // Indicates that the result can be considered sign extended from bit 31. Some234 // instructions with this flag aren't W instructions, but are either sign235 // extended from a smaller size, always outputs a small integer, or put zeros236 // in bits 63:31. Used by the SExtWRemoval pass.237 bit IsSignExtendingOpW = 0;238 let TSFlags{17} = IsSignExtendingOpW;239 240 bit HasRoundModeOp = 0;241 let TSFlags{18} = HasRoundModeOp;242 243 // This is only valid when HasRoundModeOp is set to 1. HasRoundModeOp is set244 // to 1 for vector fixed-point or floating-point intrinsics. This bit is245 // processed under pass 'RISCVInsertReadWriteCSR' pass to distinguish between246 // fixed-point / floating-point instructions and emit appropriate read/write247 // to the correct CSR.248 bit UsesVXRM = 0;249 let TSFlags{19} = UsesVXRM;250 251 // Indicates whether these instructions can partially overlap between source252 // registers and destination registers according to the vector spec.253 // 0 -> not a vector pseudo254 // 1 -> default value for vector pseudos. not widening or narrowing.255 // 2 -> narrowing case256 // 3 -> widening case257 bits<2> TargetOverlapConstraintType = 0;258 let TSFlags{21-20} = TargetOverlapConstraintType;259 260 // Most vector instructions are elementwise, but some may depend on the value261 // of VL (e.g. vslide1down.vx), and others may depend on the VL and mask262 // (e.g. vredsum.vs, viota.m). Mark these instructions so that peepholes avoid263 // changing their VL and/or mask.264 EltDeps ElementsDependOn = EltDepsNone;265 let TSFlags{22} = ElementsDependOn.VL;266 let TSFlags{23} = ElementsDependOn.Mask;267 268 // Indicates the EEW of a vector instruction's destination operand.269 EEW DestEEW = EEWSEWx1;270 let TSFlags{25-24} = DestEEW.Value;271 272 // Some vector instructions like vslidedown/vrgather will read elements past273 // VL, and should be marked to make sure RISCVVLOptimizer doesn't reduce its274 // operands' VLs.275 bit ReadsPastVL = 0;276 let TSFlags{26} = ReadsPastVL;277 278 // 0 -> Don't care about altfmt bit in VTYPE.279 // 1 -> Is not altfmt.280 // 2 -> Is altfmt(BF16).281 AltFmtType AltFmtType = DONT_CARE_ALTFMT;282 let TSFlags{28-27} = AltFmtType.Value;283 284 // XSfmmbase285 bit HasTWidenOp = 0;286 let TSFlags{29} = HasTWidenOp;287 288 bit HasTmOp = 0;289 let TSFlags{30} = HasTmOp;290 291 bit HasTkOp = 0;292 let TSFlags{31} = HasTkOp;293}294 295class RVInst<dag outs, dag ins, string opcodestr, string argstr,296 list<dag> pattern, InstFormat format>297 : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {298 field bits<32> Inst;299 let Size = 4;300}301 302class RVInst48<dag outs, dag ins, string opcodestr, string argstr,303 list<dag> pattern, InstFormat format>304 : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {305 field bits<48> Inst;306 let Size = 6;307}308 309class RVInst64<dag outs, dag ins, string opcodestr, string argstr,310 list<dag> pattern, InstFormat format>311 : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {312 field bits<64> Inst;313 let Size = 8;314}315 316// Pseudo instructions317class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">318 : RVInstCommon<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {319 let isPseudo = 1;320 let isCodeGenOnly = 1;321 let Size = 4;322}323 324class PseudoQuietFCMP<DAGOperand Ty>325 : Pseudo<(outs GPR:$rd), (ins Ty:$rs1, Ty:$rs2), []> {326 let hasSideEffects = 1;327 let mayLoad = 0;328 let mayStore = 0;329}330 331// Pseudo load instructions.332class PseudoLoad<string opcodestr, DAGOperand rdty = GPR>333 : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {334 let hasSideEffects = 0;335 let mayLoad = 1;336 let mayStore = 0;337 let isCodeGenOnly = 0;338 let isAsmParserOnly = 1;339}340 341class PseudoFloatLoad<string opcodestr, RegisterClass rdty>342 : Pseudo<(outs GPR:$tmp, rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {343 let hasSideEffects = 0;344 let mayLoad = 1;345 let mayStore = 0;346 let isCodeGenOnly = 0;347 let isAsmParserOnly = 1;348}349 350// Pseudo store instructions.351class PseudoStore<string opcodestr, DAGOperand rsty = GPR>352 : Pseudo<(outs GPR:$tmp), (ins rsty:$rs, bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {353 let hasSideEffects = 0;354 let mayLoad = 0;355 let mayStore = 1;356 let isCodeGenOnly = 0;357 let isAsmParserOnly = 1;358}359 360// Instruction formats are listed in the order they appear in the RISC-V361// instruction set manual (R, R4, I, S, B, U, J).362 363// Common base class for R format instructions. Bits {31-25} should be set by364// the subclasses.365class RVInstRBase<bits<3> funct3, RISCVOpcode opcode, dag outs,366 dag ins, string opcodestr, string argstr>367 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {368 bits<5> rs2;369 bits<5> rs1;370 bits<5> rd;371 372 let Inst{24-20} = rs2;373 let Inst{19-15} = rs1;374 let Inst{14-12} = funct3;375 let Inst{11-7} = rd;376 let Inst{6-0} = opcode.Value;377}378 379class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,380 dag ins, string opcodestr, string argstr>381 : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {382 let Inst{31-25} = funct7;383}384 385class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,386 RISCVOpcode opcode, dag outs, dag ins, string opcodestr,387 string argstr>388 : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {389 let Inst{31-27} = funct5;390 let Inst{26} = aq;391 let Inst{25} = rl;392}393 394class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,395 string opcodestr, string argstr>396 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {397 bits<5> rs2;398 bits<5> rs1;399 bits<3> frm;400 bits<5> rd;401 402 let Inst{31-25} = funct7;403 let Inst{24-20} = rs2;404 let Inst{19-15} = rs1;405 let Inst{14-12} = frm;406 let Inst{11-7} = rd;407 let Inst{6-0} = opcode.Value;408}409 410class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,411 dag ins, string opcodestr, string argstr>412 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {413 bits<5> rs3;414 bits<5> rs2;415 bits<5> rs1;416 bits<5> rd;417 418 let Inst{31-27} = rs3;419 let Inst{26-25} = funct2;420 let Inst{24-20} = rs2;421 let Inst{19-15} = rs1;422 let Inst{14-12} = funct3;423 let Inst{11-7} = rd;424 let Inst{6-0} = opcode.Value;425}426 427class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,428 string opcodestr, string argstr>429 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {430 bits<5> rs3;431 bits<5> rs2;432 bits<5> rs1;433 bits<3> frm;434 bits<5> rd;435 436 let Inst{31-27} = rs3;437 let Inst{26-25} = funct2;438 let Inst{24-20} = rs2;439 let Inst{19-15} = rs1;440 let Inst{14-12} = frm;441 let Inst{11-7} = rd;442 let Inst{6-0} = opcode.Value;443}444 445// Common base class for I format instructions. Bits {31-20} should be set by446// the subclasses.447class RVInstIBase<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,448 string opcodestr, string argstr>449 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {450 bits<5> rs1;451 bits<5> rd;452 453 let Inst{19-15} = rs1;454 let Inst{14-12} = funct3;455 let Inst{11-7} = rd;456 let Inst{6-0} = opcode.Value;457}458 459class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,460 string opcodestr, string argstr>461 : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {462 bits<12> imm12;463 464 let Inst{31-20} = imm12;465}466 467class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,468 dag outs, dag ins, string opcodestr, string argstr>469 : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {470 bits<6> shamt;471 472 let Inst{31-27} = imm11_7;473 let Inst{26} = 0;474 let Inst{25-20} = shamt;475}476 477class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,478 dag outs, dag ins, string opcodestr, string argstr>479 : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {480 bits<5> shamt;481 482 let Inst{31-25} = imm11_5;483 let Inst{24-20} = shamt;484}485 486class RVInstIUnary<bits<12> imm12, bits<3> funct3, RISCVOpcode opcode,487 dag outs, dag ins, string opcodestr, string argstr>488 : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {489 let Inst{31-20} = imm12;490}491 492class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,493 string opcodestr, string argstr>494 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> {495 bits<12> imm12;496 bits<5> rs2;497 bits<5> rs1;498 499 let Inst{31-25} = imm12{11-5};500 let Inst{24-20} = rs2;501 let Inst{19-15} = rs1;502 let Inst{14-12} = funct3;503 let Inst{11-7} = imm12{4-0};504 let Inst{6-0} = opcode.Value;505}506 507class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,508 string opcodestr, string argstr>509 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {510 bits<12> imm12;511 bits<5> rs2;512 bits<5> rs1;513 514 let Inst{31} = imm12{11};515 let Inst{30-25} = imm12{9-4};516 let Inst{24-20} = rs2;517 let Inst{19-15} = rs1;518 let Inst{14-12} = funct3;519 let Inst{11-8} = imm12{3-0};520 let Inst{7} = imm12{10};521 let Inst{6-0} = opcode.Value;522}523 524class RVInstBIMM<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,525 string opcodestr, string argstr>526 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {527 bits<12> imm12;528 bits<5> cimm;529 bits<5> rs1;530 let Inst{31} = imm12{11};531 let Inst{30-25} = imm12{9-4};532 let Inst{24-20} = cimm;533 let Inst{19-15} = rs1;534 let Inst{14-12} = funct3;535 let Inst{11-8} = imm12{3-0};536 let Inst{7} = imm12{10};537 let Inst{6-0} = opcode.Value;538}539 540class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,541 string argstr>542 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> {543 bits<20> imm20;544 bits<5> rd;545 546 let Inst{31-12} = imm20;547 let Inst{11-7} = rd;548 let Inst{6-0} = opcode.Value;549}550 551class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,552 string argstr>553 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> {554 bits<20> imm20;555 bits<5> rd;556 557 let Inst{31} = imm20{19};558 let Inst{30-21} = imm20{9-0};559 let Inst{20} = imm20{10};560 let Inst{19-12} = imm20{18-11};561 let Inst{11-7} = rd;562 let Inst{6-0} = opcode.Value;563}564 565//===----------------------------------------------------------------------===//566// Instruction classes for .insn directives567//===----------------------------------------------------------------------===//568 569class DirectiveInsnR<dag outs, dag ins, string argstr>570 : RVInst<outs, ins, "", "", [], InstFormatR> {571 bits<7> opcode;572 bits<7> funct7;573 bits<3> funct3;574 575 bits<5> rs2;576 bits<5> rs1;577 bits<5> rd;578 579 let Inst{31-25} = funct7;580 let Inst{24-20} = rs2;581 let Inst{19-15} = rs1;582 let Inst{14-12} = funct3;583 let Inst{11-7} = rd;584 let Inst{6-0} = opcode;585 586 let AsmString = ".insn r " # argstr;587}588 589class DirectiveInsnR4<dag outs, dag ins, string argstr>590 : RVInst<outs, ins, "", "", [], InstFormatR4> {591 bits<7> opcode;592 bits<2> funct2;593 bits<3> funct3;594 595 bits<5> rs3;596 bits<5> rs2;597 bits<5> rs1;598 bits<5> rd;599 600 let Inst{31-27} = rs3;601 let Inst{26-25} = funct2;602 let Inst{24-20} = rs2;603 let Inst{19-15} = rs1;604 let Inst{14-12} = funct3;605 let Inst{11-7} = rd;606 let Inst{6-0} = opcode;607 608 let AsmString = ".insn r4 " # argstr;609}610 611class DirectiveInsnI<dag outs, dag ins, string argstr>612 : RVInst<outs, ins, "", "", [], InstFormatI> {613 bits<7> opcode;614 bits<3> funct3;615 616 bits<12> imm12;617 bits<5> rs1;618 bits<5> rd;619 620 let Inst{31-20} = imm12;621 let Inst{19-15} = rs1;622 let Inst{14-12} = funct3;623 let Inst{11-7} = rd;624 let Inst{6-0} = opcode;625 626 let AsmString = ".insn i " # argstr;627}628 629class DirectiveInsnS<dag outs, dag ins, string argstr>630 : RVInst<outs, ins, "", "", [], InstFormatS> {631 bits<7> opcode;632 bits<3> funct3;633 634 bits<12> imm12;635 bits<5> rs2;636 bits<5> rs1;637 638 let Inst{31-25} = imm12{11-5};639 let Inst{24-20} = rs2;640 let Inst{19-15} = rs1;641 let Inst{14-12} = funct3;642 let Inst{11-7} = imm12{4-0};643 let Inst{6-0} = opcode;644 645 let AsmString = ".insn s " # argstr;646}647 648class DirectiveInsnB<dag outs, dag ins, string argstr>649 : RVInst<outs, ins, "", "", [], InstFormatB> {650 bits<7> opcode;651 bits<3> funct3;652 653 bits<12> imm12;654 bits<5> rs2;655 bits<5> rs1;656 657 let Inst{31} = imm12{11};658 let Inst{30-25} = imm12{9-4};659 let Inst{24-20} = rs2;660 let Inst{19-15} = rs1;661 let Inst{14-12} = funct3;662 let Inst{11-8} = imm12{3-0};663 let Inst{7} = imm12{10};664 let Inst{6-0} = opcode;665 666 let AsmString = ".insn b " # argstr;667}668 669class DirectiveInsnU<dag outs, dag ins, string argstr>670 : RVInst<outs, ins, "", "", [], InstFormatU> {671 bits<7> opcode;672 673 bits<20> imm20;674 bits<5> rd;675 676 let Inst{31-12} = imm20;677 let Inst{11-7} = rd;678 let Inst{6-0} = opcode;679 680 let AsmString = ".insn u " # argstr;681}682 683class DirectiveInsnJ<dag outs, dag ins, string argstr>684 : RVInst<outs, ins, "", "", [], InstFormatJ> {685 bits<7> opcode;686 687 bits<20> imm20;688 bits<5> rd;689 690 let Inst{31-12} = imm20;691 let Inst{11-7} = rd;692 let Inst{6-0} = opcode;693 694 let AsmString = ".insn j " # argstr;695}696