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1//===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V C extension instruction formats.10//11//===----------------------------------------------------------------------===//12 13class RVInst16<dag outs, dag ins, string opcodestr, string argstr,14 list<dag> pattern, InstFormat format>15 : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {16 field bits<16> Inst;17 let Size = 2;18}19 20class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,21 string opcodestr, string argstr>22 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> {23 bits<5> rs1;24 bits<5> rs2;25 26 let Inst{15-12} = funct4;27 let Inst{11-7} = rs1;28 let Inst{6-2} = rs2;29 let Inst{1-0} = opcode;30}31 32// The immediate value encoding differs for each instruction, so each subclass33// is responsible for setting the appropriate bits in the Inst field.34// The bits Inst{12} and Inst{6-2} may need to be set differently for some35// instructions.36class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,37 string opcodestr, string argstr>38 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> {39 bits<10> imm;40 bits<5> rd;41 42 let Inst{15-13} = funct3;43 let Inst{12} = imm{5};44 let Inst{11-7} = rd;45 let Inst{6-2} = imm{4-0};46 let Inst{1-0} = opcode;47}48 49// The immediate value encoding differs for each instruction, so each subclass50// is responsible for setting the appropriate bits in the Inst field.51// The bits Inst{12-7} may need to be set differently for some instructions.52class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,53 string opcodestr, string argstr>54 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> {55 bits<10> imm;56 bits<5> rs2;57 58 let Inst{15-13} = funct3;59 let Inst{12-7} = imm{5-0};60 let Inst{6-2} = rs2;61 let Inst{1-0} = opcode;62}63 64class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins,65 string opcodestr, string argstr>66 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> {67 bits<10> imm;68 bits<3> rd;69 70 let Inst{15-13} = funct3;71 let Inst{4-2} = rd;72 let Inst{1-0} = opcode;73}74 75// The immediate value encoding differs for each instruction, so each subclass76// is responsible for setting the appropriate bits in the Inst field.77// The bits Inst{12-10} and Inst{6-5} must be set for each instruction.78class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,79 string opcodestr, string argstr>80 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCL> {81 bits<3> rd;82 bits<3> rs1;83 84 let Inst{15-13} = funct3;85 let Inst{9-7} = rs1;86 let Inst{4-2} = rd;87 let Inst{1-0} = opcode;88}89 90// The immediate value encoding differs for each instruction, so each subclass91// is responsible for setting the appropriate bits in the Inst field.92// The bits Inst{12-10} and Inst{6-5} must be set for each instruction.93class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,94 string opcodestr, string argstr>95 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCS> {96 bits<3> rs2;97 bits<3> rs1;98 99 let Inst{15-13} = funct3;100 let Inst{9-7} = rs1;101 let Inst{4-2} = rs2;102 let Inst{1-0} = opcode;103}104 105class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs,106 dag ins, string opcodestr, string argstr>107 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> {108 bits<3> rs2;109 bits<3> rs1;110 111 let Inst{15-10} = funct6;112 let Inst{9-7} = rs1;113 let Inst{6-5} = funct2;114 let Inst{4-2} = rs2;115 let Inst{1-0} = opcode;116}117 118class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins,119 string opcodestr, string argstr>120 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> {121 bits<9> imm;122 bits<3> rs1;123 124 let Inst{15-13} = funct3;125 let Inst{9-7} = rs1;126 let Inst{1-0} = opcode;127}128 129class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,130 string opcodestr, string argstr>131 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCJ> {132 bits<11> offset;133 134 let Inst{15-13} = funct3;135 let Inst{12} = offset{10};136 let Inst{11} = offset{3};137 let Inst{10-9} = offset{8-7};138 let Inst{8} = offset{9};139 let Inst{7} = offset{5};140 let Inst{6} = offset{6};141 let Inst{5-3} = offset{2-0};142 let Inst{2} = offset{4};143 let Inst{1-0} = opcode;144}145 146class RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,147 dag ins, string opcodestr, string argstr>148 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCU>{149 bits<3> rd;150 151 let Inst{15-10} = funct6;152 let Inst{9-7} = rd;153 let Inst{6-2} = funct5;154 let Inst{1-0} = opcode;155}156 157// The immediate value encoding differs for each instruction, so each subclass158// is responsible for setting the appropriate bits in the Inst field.159// The bits Inst{6-5} must be set for each instruction.160class RVInst16CLB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,161 string opcodestr, string argstr>162 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLB> {163 bits<3> rd;164 bits<3> rs1;165 166 let Inst{15-10} = funct6;167 let Inst{9-7} = rs1;168 let Inst{4-2} = rd;169 let Inst{1-0} = opcode;170}171 172// The immediate value encoding differs for each instruction, so each subclass173// is responsible for setting the appropriate bits in the Inst field.174// The bits Inst{5} must be set for each instruction.175class RVInst16CLH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,176 dag ins, string opcodestr, string argstr>177 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLH> {178 bits<3> rd;179 bits<3> rs1;180 181 let Inst{15-10} = funct6;182 let Inst{9-7} = rs1;183 let Inst{6} = funct1;184 let Inst{4-2} = rd;185 let Inst{1-0} = opcode;186}187 188// The immediate value encoding differs for each instruction, so each subclass189// is responsible for setting the appropriate bits in the Inst field.190// The bits Inst{6-5} must be set for each instruction.191class RVInst16CSB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,192 string opcodestr, string argstr>193 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSB> {194 bits<3> rs2;195 bits<3> rs1;196 197 let Inst{15-10} = funct6;198 let Inst{9-7} = rs1;199 let Inst{4-2} = rs2;200 let Inst{1-0} = opcode;201}202 203// The immediate value encoding differs for each instruction, so each subclass204// is responsible for setting the appropriate bits in the Inst field.205// The bits Inst{5} must be set for each instruction.206class RVInst16CSH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,207 dag ins, string opcodestr, string argstr>208 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSH> {209 bits<3> rs2;210 bits<3> rs1;211 212 let Inst{15-10} = funct6;213 let Inst{9-7} = rs1;214 let Inst{6} = funct1;215 let Inst{4-2} = rs2;216 let Inst{1-0} = opcode;217}218 219//===----------------------------------------------------------------------===//220// Instruction classes for .insn directives221//===----------------------------------------------------------------------===//222 223class DirectiveInsnCR<dag outs, dag ins, string argstr>224 : RVInst16<outs, ins, "", "", [], InstFormatCR> {225 bits<2> opcode;226 bits<4> funct4;227 228 bits<5> rs2;229 bits<5> rd;230 231 let Inst{15-12} = funct4;232 let Inst{11-7} = rd;233 let Inst{6-2} = rs2;234 let Inst{1-0} = opcode;235 236 let AsmString = ".insn cr " # argstr;237}238 239class DirectiveInsnCI<dag outs, dag ins, string argstr>240 : RVInst16<outs, ins, "", "", [], InstFormatCI> {241 bits<2> opcode;242 bits<3> funct3;243 244 bits<6> imm6;245 bits<5> rd;246 247 let Inst{15-13} = funct3;248 let Inst{12} = imm6{5};249 let Inst{11-7} = rd;250 let Inst{6-2} = imm6{4-0};251 let Inst{1-0} = opcode;252 253 let AsmString = ".insn ci " # argstr;254}255 256class DirectiveInsnCIW<dag outs, dag ins, string argstr>257 : RVInst16<outs, ins, "", "", [], InstFormatCIW> {258 bits<2> opcode;259 bits<3> funct3;260 261 bits<8> imm8;262 bits<3> rd;263 264 let Inst{15-13} = funct3;265 let Inst{12-5} = imm8;266 let Inst{4-2} = rd;267 let Inst{1-0} = opcode;268 269 let AsmString = ".insn ciw " # argstr;270}271 272class DirectiveInsnCSS<dag outs, dag ins, string argstr>273 : RVInst16<outs, ins, "", "", [], InstFormatCSS> {274 bits<2> opcode;275 bits<3> funct3;276 277 bits<6> imm6;278 bits<5> rs2;279 280 let Inst{15-13} = funct3;281 let Inst{12-7} = imm6;282 let Inst{6-2} = rs2;283 let Inst{1-0} = opcode;284 285 let AsmString = ".insn css " # argstr;286}287 288class DirectiveInsnCL<dag outs, dag ins, string argstr>289 : RVInst16<outs, ins, "", "", [], InstFormatCL> {290 bits<2> opcode;291 bits<3> funct3;292 293 bits<5> imm5;294 bits<3> rd;295 bits<3> rs1;296 297 let Inst{15-13} = funct3;298 let Inst{12-10} = imm5{4-2};299 let Inst{9-7} = rs1;300 let Inst{6-5} = imm5{1-0};301 let Inst{4-2} = rd;302 let Inst{1-0} = opcode;303 304 let AsmString = ".insn cl " # argstr;305}306 307class DirectiveInsnCS<dag outs, dag ins, string argstr>308 : RVInst16<outs, ins, "", "", [], InstFormatCS> {309 bits<2> opcode;310 bits<3> funct3;311 312 bits<5> imm5;313 bits<3> rs2;314 bits<3> rs1;315 316 let Inst{15-13} = funct3;317 let Inst{12-10} = imm5{4-2};318 let Inst{9-7} = rs1;319 let Inst{6-5} = imm5{1-0};320 let Inst{4-2} = rs2;321 let Inst{1-0} = opcode;322 323 let AsmString = ".insn cs " # argstr;324}325 326class DirectiveInsnCA<dag outs, dag ins, string argstr>327 : RVInst16<outs, ins, "", "", [], InstFormatCA> {328 bits<2> opcode;329 bits<6> funct6;330 bits<2> funct2;331 332 bits<3> rd;333 bits<3> rs2;334 335 let Inst{15-10} = funct6;336 let Inst{9-7} = rd;337 let Inst{6-5} = funct2;338 let Inst{4-2} = rs2;339 let Inst{1-0} = opcode;340 341 let AsmString = ".insn ca " # argstr;342}343 344class DirectiveInsnCB<dag outs, dag ins, string argstr>345 : RVInst16<outs, ins, "", "", [], InstFormatCB> {346 bits<2> opcode;347 bits<3> funct3;348 349 bits<8> imm8;350 bits<3> rs1;351 352 let Inst{15-13} = funct3;353 let Inst{12} = imm8{7};354 let Inst{11-10} = imm8{3-2};355 let Inst{9-7} = rs1;356 let Inst{6-5} = imm8{6-5};357 let Inst{4-3} = imm8{1-0};358 let Inst{2} = imm8{4};359 let Inst{1-0} = opcode;360 361 let AsmString = ".insn cb " # argstr;362}363 364class DirectiveInsnCJ<dag outs, dag ins, string argstr>365 : RVInst16<outs, ins, "", "", [], InstFormatCJ> {366 bits<2> opcode;367 bits<3> funct3;368 369 bits<11> imm11;370 371 let Inst{15-13} = funct3;372 let Inst{12} = imm11{10};373 let Inst{11} = imm11{3};374 let Inst{10-9} = imm11{8-7};375 let Inst{8} = imm11{9};376 let Inst{7} = imm11{5};377 let Inst{6} = imm11{6};378 let Inst{5-3} = imm11{2-0};379 let Inst{2} = imm11{4};380 let Inst{1-0} = opcode;381 382 let AsmString = ".insn cj " # argstr;383}384