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1//===- RISCVInstrInfoC.td - Compressed RISC-V instructions -*- tblgen-*----===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Operand definitions.11//===----------------------------------------------------------------------===//12 13def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {14 let Name = "UImmLog2XLenNonZero";15 let RenderMethod = "addImmOperands";16 let DiagnosticType = "InvalidUImmLog2XLenNonZero";17}18 19def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{20 if (Subtarget->is64Bit())21 return isUInt<6>(Imm) && (Imm != 0);22 return isUInt<5>(Imm) && (Imm != 0);23}]> {24 let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;25 let DecoderMethod = "decodeUImmLog2XLenNonZeroOperand";26 let OperandType = "OPERAND_UIMMLOG2XLEN_NONZERO";27 let MCOperandPredicate = [{28 int64_t Imm;29 if (!MCOp.evaluateAsConstantImm(Imm))30 return false;31 if (STI.getTargetTriple().isArch64Bit())32 return isUInt<6>(Imm) && (Imm != 0);33 return isUInt<5>(Imm) && (Imm != 0);34 }];35}36 37def simm6 : RISCVSImmLeafOp<6> {38 let MCOperandPredicate = [{39 int64_t Imm;40 if (MCOp.evaluateAsConstantImm(Imm))41 return isInt<6>(Imm);42 return MCOp.isBareSymbolRef();43 }];44}45 46def simm6nonzero : RISCVOp,47 ImmLeaf<XLenVT, [{return (Imm != 0) && isInt<6>(Imm);}]> {48 let ParserMatchClass = SImmAsmOperand<6, "NonZero">;49 let EncoderMethod = "getImmOpValue";50 let DecoderMethod = "decodeSImmNonZeroOperand<6>";51 let OperandType = "OPERAND_SIMM6_NONZERO";52 let MCOperandPredicate = [{53 int64_t Imm;54 if (MCOp.evaluateAsConstantImm(Imm))55 return (Imm != 0) && isInt<6>(Imm);56 return MCOp.isBareSymbolRef();57 }];58}59 60def CLUIImmAsmOperand : AsmOperandClass {61 let Name = "CLUIImm";62 let RenderMethod = "addImmOperands";63 let DiagnosticType = !strconcat("Invalid", Name);64}65 66 67// c_lui_imm checks the immediate range is in [1, 31] or [0xfffe0, 0xfffff].68// The RISC-V ISA describes the constraint as [1, 63], with that value being69// loaded in to bits 17-12 of the destination register and sign extended from70// bit 17. Therefore, this 6-bit immediate can represent values in the ranges71// [1, 31] and [0xfffe0, 0xfffff].72def c_lui_imm : RISCVOp,73 ImmLeaf<XLenVT, [{return (Imm != 0) &&74 (isUInt<5>(Imm) ||75 (Imm >= 0xfffe0 && Imm <= 0xfffff));}]> {76 let ParserMatchClass = CLUIImmAsmOperand;77 let EncoderMethod = "getImmOpValue";78 let DecoderMethod = "decodeCLUIImmOperand";79 let OperandType = "OPERAND_CLUI_IMM";80 let MCOperandPredicate = [{81 int64_t Imm;82 if (!MCOp.evaluateAsConstantImm(Imm))83 return false;84 return (Imm != 0) && (isUInt<5>(Imm) ||85 (Imm >= 0xfffe0 && Imm <= 0xfffff));86 }];87}88 89// A 7-bit unsigned immediate where the least significant two bits are zero.90def uimm7_lsb00 : RISCVOp,91 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {92 let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;93 let EncoderMethod = "getImmOpValue";94 let DecoderMethod = "decodeUImmOperand<7>";95 let OperandType = "OPERAND_UIMM7_LSB00";96 let MCOperandPredicate = [{97 int64_t Imm;98 if (!MCOp.evaluateAsConstantImm(Imm))99 return false;100 return isShiftedUInt<5, 2>(Imm);101 }];102}103 104// A 8-bit unsigned immediate where the least significant two bits are zero.105def uimm8_lsb00 : RISCVOp,106 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {107 let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;108 let EncoderMethod = "getImmOpValue";109 let DecoderMethod = "decodeUImmOperand<8>";110 let OperandType = "OPERAND_UIMM8_LSB00";111 let MCOperandPredicate = [{112 int64_t Imm;113 if (!MCOp.evaluateAsConstantImm(Imm))114 return false;115 return isShiftedUInt<6, 2>(Imm);116 }];117}118 119// A 8-bit unsigned immediate where the least significant three bits are zero.120def uimm8_lsb000 : RISCVOp,121 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {122 let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;123 let EncoderMethod = "getImmOpValue";124 let DecoderMethod = "decodeUImmOperand<8>";125 let OperandType = "OPERAND_UIMM8_LSB000";126 let MCOperandPredicate = [{127 int64_t Imm;128 if (!MCOp.evaluateAsConstantImm(Imm))129 return false;130 return isShiftedUInt<5, 3>(Imm);131 }];132}133 134// A 9-bit signed immediate where the least significant bit is zero.135def bare_simm9_lsb0 : Operand<OtherVT>,136 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {137 let ParserMatchClass = BareSImmNLsb0AsmOperand<9>;138 let PrintMethod = "printBranchOperand";139 let EncoderMethod = "getImmOpValueAsrN<1>";140 let DecoderMethod = "decodeSImmOperandAndLslN<9, 1>";141 let MCOperandPredicate = [{142 int64_t Imm;143 if (MCOp.evaluateAsConstantImm(Imm))144 return isShiftedInt<8, 1>(Imm);145 return MCOp.isBareSymbolRef();146 }];147 let OperandType = "OPERAND_PCREL";148}149 150// A 9-bit unsigned immediate where the least significant three bits are zero.151def uimm9_lsb000 : RISCVOp,152 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {153 let ParserMatchClass = UImmAsmOperand<9, "Lsb000">;154 let EncoderMethod = "getImmOpValue";155 let DecoderMethod = "decodeUImmOperand<9>";156 let OperandType = "OPERAND_UIMM9_LSB000";157 let MCOperandPredicate = [{158 int64_t Imm;159 if (!MCOp.evaluateAsConstantImm(Imm))160 return false;161 return isShiftedUInt<6, 3>(Imm);162 }];163}164 165// A 10-bit unsigned immediate where the least significant two bits are zero166// and the immediate can't be zero.167def uimm10_lsb00nonzero : RISCVOp,168 ImmLeaf<XLenVT,169 [{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {170 let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">;171 let EncoderMethod = "getImmOpValue";172 let DecoderMethod = "decodeUImmNonZeroOperand<10>";173 let OperandType = "OPERAND_UIMM10_LSB00_NONZERO";174 let MCOperandPredicate = [{175 int64_t Imm;176 if (!MCOp.evaluateAsConstantImm(Imm))177 return false;178 return isShiftedUInt<8, 2>(Imm) && (Imm != 0);179 }];180}181 182// A 10-bit signed immediate where the least significant four bits are zero.183def simm10_lsb0000nonzero : RISCVOp,184 ImmLeaf<XLenVT,185 [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {186 let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">;187 let EncoderMethod = "getImmOpValue";188 let DecoderMethod = "decodeSImmNonZeroOperand<10>";189 let OperandType = "OPERAND_SIMM10_LSB0000_NONZERO";190 let MCOperandPredicate = [{191 int64_t Imm;192 if (!MCOp.evaluateAsConstantImm(Imm))193 return false;194 return isShiftedInt<6, 4>(Imm) && (Imm != 0);195 }];196}197 198// A 12-bit signed immediate where the least significant bit is zero.199def bare_simm12_lsb0 : Operand<OtherVT>,200 ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {201 let ParserMatchClass = BareSImmNLsb0AsmOperand<12>;202 let PrintMethod = "printBranchOperand";203 let EncoderMethod = "getImmOpValueAsrN<1>";204 let DecoderMethod = "decodeSImmOperandAndLslN<12, 1>";205 let MCOperandPredicate = [{206 int64_t Imm;207 if (MCOp.evaluateAsConstantImm(Imm))208 return isShiftedInt<11, 1>(Imm);209 return MCOp.isBareSymbolRef();210 }];211 let OperandType = "OPERAND_PCREL";212}213 214def InsnCDirectiveOpcode : AsmOperandClass {215 let Name = "InsnCDirectiveOpcode";216 let ParserMethod = "parseInsnCDirectiveOpcode";217 let RenderMethod = "addImmOperands";218 let PredicateMethod = "isImm";219}220 221def uimm2_opcode : RISCVUImmOp<2> {222 let ParserMatchClass = InsnCDirectiveOpcode;223}224 225//===----------------------------------------------------------------------===//226// Instruction Class Templates227//===----------------------------------------------------------------------===//228 229let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in230class CStackLoad<bits<3> funct3, string OpcodeStr,231 DAGOperand cls, DAGOperand opnd>232 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SPMem:$rs1, opnd:$imm),233 OpcodeStr, "$rd, ${imm}(${rs1})"> {234 bits<0> rs1;235}236 237let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in238class CStackStore<bits<3> funct3, string OpcodeStr,239 DAGOperand cls, DAGOperand opnd>240 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SPMem:$rs1, opnd:$imm),241 OpcodeStr, "$rs2, ${imm}(${rs1})"> {242 bits<0> rs1;243}244 245let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in246class CLoad_ri<bits<3> funct3, string OpcodeStr,247 DAGOperand cls, DAGOperand opnd>248 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRCMem:$rs1, opnd:$imm),249 OpcodeStr, "$rd, ${imm}(${rs1})">;250 251let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in252class CStore_rri<bits<3> funct3, string OpcodeStr,253 DAGOperand cls, DAGOperand opnd>254 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2,GPRCMem:$rs1, opnd:$imm),255 OpcodeStr, "$rs2, ${imm}(${rs1})">;256 257let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in258class Bcz<bits<3> funct3, string OpcodeStr>259 : RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, bare_simm9_lsb0:$imm),260 OpcodeStr, "$rs1, $imm"> {261 let isBranch = 1;262 let isTerminator = 1;263 let Inst{12} = imm{7};264 let Inst{11-10} = imm{3-2};265 let Inst{6-5} = imm{6-5};266 let Inst{4-3} = imm{1-0};267 let Inst{2} = imm{4};268}269 270let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in271class Shift_right<bits<2> funct2, string OpcodeStr>272 : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),273 (ins GPRC:$rs1, uimmlog2xlen:$imm),274 OpcodeStr, "$rs1, $imm"> {275 let Constraints = "$rs1 = $rd";276 let Inst{12} = imm{5};277 let Inst{11-10} = funct2;278 let Inst{6-2} = imm{4-0};279}280 281let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in282class CA_ALU<bits<6> funct6, bits<2> funct2, string OpcodeStr>283 : RVInst16CA<funct6, funct2, 0b01, (outs GPRC:$rd_wb),284 (ins GPRC:$rd, GPRC:$rs2), OpcodeStr, "$rd, $rs2"> {285 bits<3> rd;286 let Constraints = "$rd = $rd_wb";287 let Inst{9-7} = rd;288}289 290//===----------------------------------------------------------------------===//291// Instructions292//===----------------------------------------------------------------------===//293 294let Predicates = [HasStdExtZca] in {295 296let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [X2] in297def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),298 (ins SP:$rs1, uimm10_lsb00nonzero:$imm),299 "c.addi4spn", "$rd, $rs1, $imm">,300 Sched<[WriteIALU, ReadIALU]> {301 bits<0> rs1;302 let Inst{12-11} = imm{5-4};303 let Inst{10-7} = imm{9-6};304 let Inst{6} = imm{2};305 let Inst{5} = imm{3};306}307 308def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,309 Sched<[WriteLDW, ReadMemBase]> {310 bits<7> imm;311 let Inst{12-10} = imm{5-3};312 let Inst{6} = imm{2};313 let Inst{5} = imm{6};314}315 316let isCodeGenOnly = 1 in317def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,318 Sched<[WriteLDW, ReadMemBase]> {319 bits<7> imm;320 let Inst{12-10} = imm{5-3};321 let Inst{6} = imm{2};322 let Inst{5} = imm{6};323}324 325let Predicates = [HasStdExtZca, IsRV64] in326def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,327 Sched<[WriteLDD, ReadMemBase]> {328 bits<8> imm;329 let Inst{12-10} = imm{5-3};330 let Inst{6-5} = imm{7-6};331}332 333def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,334 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {335 bits<7> imm;336 let Inst{12-10} = imm{5-3};337 let Inst{6} = imm{2};338 let Inst{5} = imm{6};339}340 341let isCodeGenOnly = 1 in342def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,343 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {344 bits<7> imm;345 let Inst{12-10} = imm{5-3};346 let Inst{6} = imm{2};347 let Inst{5} = imm{6};348}349 350let Predicates = [HasStdExtZca, IsRV64] in351def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,352 Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {353 bits<8> imm;354 let Inst{12-10} = imm{5-3};355 let Inst{6-5} = imm{7-6};356}357 358let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in359def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,360 Sched<[WriteNop]> {361 let rd = 0;362 let imm = 0;363}364 365let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in366def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),367 (ins GPRNoX0:$rd, simm6:$imm),368 "c.addi", "$rd, $imm">,369 Sched<[WriteIALU, ReadIALU]> {370 let Constraints = "$rd = $rd_wb";371}372 373// Alternate syntax for c.nop. Converted to C_NOP/C_NOP_HINT by the assembler.374let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,375 isAsmParserOnly = 1 in376def PseudoC_ADDI_NOP : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, simm6:$imm),377 [], "c.addi", "$rd, $imm"> {378 let Constraints = "$rs1 = $rd";379}380 381let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,382 DecoderNamespace = "RV32Only", Defs = [X1],383 Predicates = [HasStdExtZca, IsRV32] in384def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins bare_simm12_lsb0:$offset),385 "c.jal", "$offset">, Sched<[WriteJal]>;386 387let hasSideEffects = 0, mayLoad = 0, mayStore = 0,388 Predicates = [HasStdExtZca, IsRV64] in389def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),390 (ins GPRNoX0:$rd, simm6:$imm),391 "c.addiw", "$rd, $imm">,392 Sched<[WriteIALU32, ReadIALU32]> {393 let Constraints = "$rd = $rd_wb";394}395 396let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in397def C_LI : RVInst16CI<0b010, 0b01, (outs GPR:$rd), (ins simm6:$imm),398 "c.li", "$rd, $imm">,399 Sched<[WriteIALU]>;400 401let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in402def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),403 (ins SP:$rd, simm10_lsb0000nonzero:$imm),404 "c.addi16sp", "$rd, $imm">,405 Sched<[WriteIALU, ReadIALU]> {406 let Constraints = "$rd = $rd_wb";407 let rd = 2;408 let Inst{12} = imm{9};409 let Inst{6} = imm{4};410 let Inst{5} = imm{6};411 let Inst{4-3} = imm{8-7};412 let Inst{2} = imm{5};413}414 415let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in416def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX2:$rd),417 (ins c_lui_imm:$imm),418 "c.lui", "$rd, $imm">,419 Sched<[WriteIALU]>;420 421def C_SRLI : Shift_right<0b00, "c.srli">,422 Sched<[WriteShiftImm, ReadShiftImm]>;423def C_SRAI : Shift_right<0b01, "c.srai">,424 Sched<[WriteShiftImm, ReadShiftImm]>;425 426let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in427def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rd), (ins GPRC:$rs1, simm6:$imm),428 "c.andi", "$rs1, $imm">,429 Sched<[WriteIALU, ReadIALU]> {430 let Constraints = "$rs1 = $rd";431 let Inst{12} = imm{5};432 let Inst{11-10} = 0b10;433 let Inst{6-2} = imm{4-0};434}435 436def C_SUB : CA_ALU<0b100011, 0b00, "c.sub">,437 Sched<[WriteIALU, ReadIALU, ReadIALU]>;438def C_XOR : CA_ALU<0b100011, 0b01, "c.xor">,439 Sched<[WriteIALU, ReadIALU, ReadIALU]>;440def C_OR : CA_ALU<0b100011, 0b10, "c.or">,441 Sched<[WriteIALU, ReadIALU, ReadIALU]>;442def C_AND : CA_ALU<0b100011, 0b11, "c.and">,443 Sched<[WriteIALU, ReadIALU, ReadIALU]>;444 445let Predicates = [HasStdExtZca, IsRV64] in {446def C_SUBW : CA_ALU<0b100111, 0b00, "c.subw">,447 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;448def C_ADDW : CA_ALU<0b100111, 0b01, "c.addw">,449 Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;450}451 452let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in453def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins bare_simm12_lsb0:$offset),454 "c.j", "$offset">, Sched<[WriteJmp]> {455 let isBranch = 1;456 let isTerminator=1;457 let isBarrier=1;458}459 460def C_BEQZ : Bcz<0b110, "c.beqz">, Sched<[WriteJmp, ReadJmp]>;461def C_BNEZ : Bcz<0b111, "c.bnez">, Sched<[WriteJmp, ReadJmp]>;462 463let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in464def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb),465 (ins GPR:$rd, uimmlog2xlen:$imm),466 "c.slli", "$rd, $imm">,467 Sched<[WriteShiftImm, ReadShiftImm]> {468 let Constraints = "$rd = $rd_wb";469}470 471def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00>,472 Sched<[WriteLDW, ReadMemBase]> {473 let Inst{3-2} = imm{7-6};474}475 476let isCodeGenOnly = 1 in477def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,478 Sched<[WriteLDW, ReadMemBase]> {479 let Inst{3-2} = imm{7-6};480}481 482let Predicates = [HasStdExtZca, IsRV64] in483def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,484 Sched<[WriteLDD, ReadMemBase]> {485 let Inst{4-2} = imm{8-6};486}487 488let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in489def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),490 "c.jr", "$rs1">, Sched<[WriteJalr, ReadJalr]> {491 let isBarrier = 1;492 let isTerminator = 1;493 let rs2 = 0;494}495 496let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,497 isAsCheapAsAMove = 1 in498def C_MV : RVInst16CR<0b1000, 0b10, (outs GPR:$rs1), (ins GPRNoX0:$rs2),499 "c.mv", "$rs1, $rs2">,500 Sched<[WriteIALU, ReadIALU]>;501 502let rs1 = 0, rs2 = 0, hasSideEffects = 1, mayLoad = 0, mayStore = 0 in503def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">, Sched<[]>;504 505let hasSideEffects = 0, mayLoad = 0, mayStore = 0,506 isCall=1, Defs=[X1], rs2 = 0 in507def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),508 "c.jalr", "$rs1">, Sched<[WriteJalr, ReadJalr]>;509 510let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in511def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPR:$rd),512 (ins GPR:$rs1, GPRNoX0:$rs2),513 "c.add", "$rs1, $rs2">,514 Sched<[WriteIALU, ReadIALU, ReadIALU]> {515 let Constraints = "$rs1 = $rd";516}517 518def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00>,519 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {520 let Inst{8-7} = imm{7-6};521}522 523let isCodeGenOnly = 1 in524def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,525 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {526 let Inst{8-7} = imm{7-6};527}528 529let Predicates = [HasStdExtZca, IsRV64] in530def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,531 Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {532 let Inst{9-7} = imm{8-6};533}534 535// The all zeros pattern isn't a valid RISC-V instruction. It's used by GNU536// binutils as 16-bit instruction known to be unimplemented (i.e., trapping).537let hasSideEffects = 1, mayLoad = 0, mayStore = 0, isTrap = 1 in538def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,539 Sched<[]> {540 let Inst{15-0} = 0;541}542 543} // Predicates = [HasStdExtZca]544 545let DecoderNamespace = "RV32Only",546 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {547 def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,548 Sched<[WriteFLD32, ReadFMemBase]> {549 bits<7> imm;550 let Inst{12-10} = imm{5-3};551 let Inst{6} = imm{2};552 let Inst{5} = imm{6};553 }554 555 def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,556 Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {557 bits<7> imm;558 let Inst{12-10} = imm{5-3};559 let Inst{6} = imm{2};560 let Inst{5} = imm{6};561 }562 563 def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,564 Sched<[WriteFLD32, ReadFMemBase]> {565 let Inst{3-2} = imm{7-6};566 }567 568 def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,569 Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {570 let Inst{8-7} = imm{7-6};571 }572} // DecoderNamespace = "RV32Only", Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]573 574let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {575 def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,576 Sched<[WriteFLD64, ReadFMemBase]> {577 bits<8> imm;578 let Inst{12-10} = imm{5-3};579 let Inst{6-5} = imm{7-6};580 }581 582 def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,583 Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {584 bits<8> imm;585 let Inst{12-10} = imm{5-3};586 let Inst{6-5} = imm{7-6};587 }588 589 def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,590 Sched<[WriteFLD64, ReadFMemBase]> {591 let Inst{4-2} = imm{8-6};592 }593 594 def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,595 Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {596 let Inst{9-7} = imm{8-6};597 }598} // Predicates = [HasStdExtCOrZcd, HasStdExtD] in {599 600//===----------------------------------------------------------------------===//601// HINT Instructions602//===----------------------------------------------------------------------===//603 604let Predicates = [HasStdExtZca], hasSideEffects = 0, mayLoad = 0,605 mayStore = 0 in {606 607def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),608 "c.nop", "$imm">, Sched<[WriteNop]> {609 let rd = 0;610}611 612} // Predicates = [HasStdExtZca], hasSideEffects = 0, mayLoad = 0,613 // mayStore = 0614 615//===----------------------------------------------------------------------===//616// Assembler Pseudo Instructions617//===----------------------------------------------------------------------===//618 619let Predicates = [HasStdExtZca] in {620// Legacy aliases.621def : InstAlias<"c.slli64 $rd", (C_SLLI GPR:$rd, 0), 0>;622def : InstAlias<"c.srli64 $rs1", (C_SRLI GPRC:$rs1, 0), 0>;623def : InstAlias<"c.srai64 $rs1", (C_SRAI GPRC:$rs1, 0), 0>;624}625 626let Predicates = [HasStdExtC, HasStdExtZihintntl] in {627def : InstAlias<"c.ntl.p1", (C_ADD X0, X2)>;628def : InstAlias<"c.ntl.pall", (C_ADD X0, X3)>;629def : InstAlias<"c.ntl.s1", (C_ADD X0, X4)>;630def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>;631} // Predicates = [HasStdExtC, HasStdExtZihintntl]632 633let EmitPriority = 0 in {634let Predicates = [HasStdExtZca] in {635def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRCMem:$rs1, 0)>;636def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRCMem:$rs1, 0)>;637def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRNoX0:$rd, SPMem:$rs1, 0)>;638def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPR:$rs2, SPMem:$rs1, 0)>;639}640 641let Predicates = [HasStdExtZca, IsRV64] in {642def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRCMem:$rs1, 0)>;643def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRCMem:$rs1, 0)>;644def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRNoX0:$rd, SPMem:$rs1, 0)>;645def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPR:$rs2, SPMem:$rs1, 0)>;646}647 648let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {649def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>;650def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>;651def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>;652def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>;653}654 655let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {656def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;657def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>;658def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>;659def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64:$rs2, SPMem:$rs1, 0)>;660}661} // EmitPriority = 0662 663//===----------------------------------------------------------------------===//664// .insn directive instructions665//===----------------------------------------------------------------------===//666 667def AnyRegCOperand : AsmOperandClass {668 let Name = "AnyRegCOperand";669 let RenderMethod = "addRegOperands";670 let PredicateMethod = "isAnyRegC";671}672 673def AnyRegC : Operand<XLenVT> {674 let OperandType = "OPERAND_REGISTER";675 let ParserMatchClass = AnyRegCOperand;676}677 678// isCodeGenOnly = 1 to hide them from the tablegened assembly parser.679let isCodeGenOnly = 1, hasSideEffects = 1, mayLoad = 1, mayStore = 1,680 hasNoSchedulingInfo = 1, Predicates = [HasStdExtZca] in {681def InsnCR : DirectiveInsnCR<(outs AnyReg:$rd), (ins uimm2_opcode:$opcode,682 uimm4:$funct4,683 AnyReg:$rs2),684 "$opcode, $funct4, $rd, $rs2">;685def InsnCI : DirectiveInsnCI<(outs AnyReg:$rd), (ins uimm2_opcode:$opcode,686 uimm3:$funct3,687 simm6:$imm6),688 "$opcode, $funct3, $rd, $imm6">;689def InsnCIW : DirectiveInsnCIW<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,690 uimm3:$funct3,691 uimm8:$imm8),692 "$opcode, $funct3, $rd, $imm8">;693def InsnCSS : DirectiveInsnCSS<(outs), (ins uimm2_opcode:$opcode,694 uimm3:$funct3,695 AnyReg:$rs2,696 uimm6:$imm6),697 "$opcode, $funct3, $rs2, $imm6">;698def InsnCL : DirectiveInsnCL<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,699 uimm3:$funct3,700 AnyRegC:$rs1,701 uimm5:$imm5),702 "$opcode, $funct3, $rd, ${imm5}(${rs1})">;703def InsnCS : DirectiveInsnCS<(outs), (ins uimm2_opcode:$opcode,704 uimm3:$funct3,705 AnyRegC:$rs2,706 AnyRegC:$rs1,707 uimm5:$imm5),708 "$opcode, $funct3, $rs2, ${imm5}(${rs1})">;709def InsnCA : DirectiveInsnCA<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,710 uimm6:$funct6,711 uimm2:$funct2,712 AnyRegC:$rs2),713 "$opcode, $funct6, $funct2, $rd, $rs2">;714def InsnCB : DirectiveInsnCB<(outs), (ins uimm2_opcode:$opcode, uimm3:$funct3,715 AnyRegC:$rs1,716 bare_simm9_lsb0:$imm8),717 "$opcode, $funct3, $rs1, $imm8">;718def InsnCJ : DirectiveInsnCJ<(outs), (ins uimm2_opcode:$opcode,719 uimm3:$funct3,720 bare_simm12_lsb0:$imm11),721 "$opcode, $funct3, $imm11">;722}723 724// Use InstAliases to match these so that we can combine the insn and format725// into a mnemonic to use as the key for the tablegened asm matcher table. The726// parser will take care of creating these fake mnemonics and will only do it727// for known formats.728let EmitPriority = 0, Predicates = [HasStdExtZca] in {729def : InstAlias<".insn_cr $opcode, $funct4, $rd, $rs2",730 (InsnCR AnyReg:$rd, uimm2_opcode:$opcode, uimm4:$funct4,731 AnyReg:$rs2)>;732def : InstAlias<".insn_ci $opcode, $funct3, $rd, $imm6",733 (InsnCI AnyReg:$rd, uimm2_opcode:$opcode, uimm3:$funct3,734 simm6:$imm6)>;735def : InstAlias<".insn_ciw $opcode, $funct3, $rd, $imm8",736 (InsnCIW AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,737 uimm8:$imm8)>;738def : InstAlias<".insn_css $opcode, $funct3, $rs2, $imm6",739 (InsnCSS uimm2_opcode:$opcode, uimm3:$funct3, AnyReg:$rs2,740 uimm6:$imm6)>;741def : InstAlias<".insn_cl $opcode, $funct3, $rd, ${imm5}(${rs1})",742 (InsnCL AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,743 AnyRegC:$rs1, uimm5:$imm5)>;744def : InstAlias<".insn_cl $opcode, $funct3, $rd, (${rs1})",745 (InsnCL AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,746 AnyRegC:$rs1, 0)>;747def : InstAlias<".insn_cs $opcode, $funct3, $rs2, ${imm5}(${rs1})",748 (InsnCS uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs2,749 AnyRegC:$rs1, uimm5:$imm5)>;750def : InstAlias<".insn_cs $opcode, $funct3, $rs2, (${rs1})",751 (InsnCS uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs2,752 AnyRegC:$rs1, 0)>;753def : InstAlias<".insn_ca $opcode, $funct6, $funct2, $rd, $rs2",754 (InsnCA AnyRegC:$rd, uimm2_opcode:$opcode, uimm6:$funct6,755 uimm2:$funct2, AnyRegC:$rs2)>;756def : InstAlias<".insn_cb $opcode, $funct3, $rs1, $imm8",757 (InsnCB uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs1,758 bare_simm9_lsb0:$imm8)>;759def : InstAlias<".insn_cj $opcode, $funct3, $imm11",760 (InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, bare_simm12_lsb0:$imm11)>;761}762 763//===----------------------------------------------------------------------===/i764// Compress Instruction tablegen backend.765//===----------------------------------------------------------------------===//766 767// Zca patterns are defined in the same order the compressed instructions appear768// under the "RVC Instruction Set Listings" section of the ISA manual.769 770// Zca Instructions771 772// Quadrant 0773let Predicates = [HasStdExtZca] in {774def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),775 (C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;776} // Predicates = [HasStdExtZca]777 778let Predicates = [HasStdExtZca] in {779def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),780 (C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;781 782let isCompressOnly = true in783def : CompressPat<(LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),784 (C_LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;785} // Predicates = [HasStdExtZca]786 787let Predicates = [HasStdExtZca, IsRV64] in {788def : CompressPat<(LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),789 (C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;790} // Predicates = [HasStdExtZca, IsRV64]791 792let Predicates = [HasStdExtZca] in {793def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),794 (C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;795 796let isCompressOnly = true in797def : CompressPat<(SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),798 (C_SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;799} // Predicates = [HasStdExtZca]800 801let Predicates = [HasStdExtZca, IsRV64] in {802def : CompressPat<(SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),803 (C_SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;804} // Predicates = [HasStdExtZca, IsRV64]805 806// Quadrant 1807let Predicates = [HasStdExtZca] in {808def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;809def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),810 (C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>;811} // Predicates = [HasStdExtZca]812 813let Predicates = [HasStdExtZca, IsRV32] in {814def : CompressPat<(JAL X1, bare_simm12_lsb0:$offset),815 (C_JAL bare_simm12_lsb0:$offset)>;816} // Predicates = [HasStdExtZca, IsRV32]817 818let Predicates = [HasStdExtZca, IsRV64] in {819def : CompressPat<(ADDIW GPRNoX0:$rs1, GPRNoX0:$rs1, simm6:$imm),820 (C_ADDIW GPRNoX0:$rs1, simm6:$imm)>;821} // Predicates = [HasStdExtZca, IsRV64]822 823let Predicates = [HasStdExtZca] in {824def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),825 (C_LI GPRNoX0:$rd, simm6:$imm)>;826def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),827 (C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;828def : CompressPat<(LUI GPRNoX0X2:$rd, c_lui_imm:$imm),829 (C_LUI GPRNoX0X2:$rd, c_lui_imm:$imm)>;830def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),831 (C_SRLI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;832def : CompressPat<(SRAI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),833 (C_SRAI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;834def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),835 (C_ANDI GPRC:$rs1, simm6:$imm)>;836def : CompressPat<(SUB GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),837 (C_SUB GPRC:$rs1, GPRC:$rs2)>;838def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),839 (C_XOR GPRC:$rs1, GPRC:$rs2)>;840let isCompressOnly = true in841def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),842 (C_XOR GPRC:$rs1, GPRC:$rs2)>;843def : CompressPat<(OR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),844 (C_OR GPRC:$rs1, GPRC:$rs2)>;845let isCompressOnly = true in846def : CompressPat<(OR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),847 (C_OR GPRC:$rs1, GPRC:$rs2)>;848def : CompressPat<(AND GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),849 (C_AND GPRC:$rs1, GPRC:$rs2)>;850let isCompressOnly = true in851def : CompressPat<(AND GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),852 (C_AND GPRC:$rs1, GPRC:$rs2)>;853} // Predicates = [HasStdExtZca]854 855let Predicates = [HasStdExtZca, IsRV64] in {856let isCompressOnly = true in857def : CompressPat<(ADDIW GPRNoX0:$rd, X0, simm6:$imm),858 (C_LI GPRNoX0:$rd, simm6:$imm)>;859def : CompressPat<(SUBW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),860 (C_SUBW GPRC:$rs1, GPRC:$rs2)>;861def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),862 (C_ADDW GPRC:$rs1, GPRC:$rs2)>;863let isCompressOnly = true in864def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),865 (C_ADDW GPRC:$rs1, GPRC:$rs2)>;866} // Predicates = [HasStdExtZca, IsRV64]867 868let Predicates = [HasStdExtZca] in {869def : CompressPat<(JAL X0, bare_simm12_lsb0:$offset),870 (C_J bare_simm12_lsb0:$offset)>;871def : CompressPat<(BEQ GPRC:$rs1, X0, bare_simm9_lsb0:$imm),872 (C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;873let isCompressOnly = true in874def : CompressPat<(BEQ X0, GPRC:$rs1, bare_simm9_lsb0:$imm),875 (C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;876def : CompressPat<(BNE GPRC:$rs1, X0, bare_simm9_lsb0:$imm),877 (C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;878let isCompressOnly = true in879def : CompressPat<(BNE X0, GPRC:$rs1, bare_simm9_lsb0:$imm),880 (C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;881} // Predicates = [HasStdExtZca]882 883// Quadrant 2884let Predicates = [HasStdExtZca] in {885def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),886 (C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;887} // Predicates = [HasStdExtZca]888 889let Predicates = [HasStdExtZca] in {890def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),891 (C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;892 893let isCompressOnly = true in894def : CompressPat<(LW_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),895 (C_LWSP_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;896} // Predicates = [HasStdExtZca]897 898let Predicates = [HasStdExtZca, IsRV64] in {899def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm),900 (C_LDSP GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;901} // Predicates = [HasStdExtZca, IsRV64]902 903let Predicates = [HasStdExtZca] in {904def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),905 (C_JR GPRNoX0:$rs1)>;906let isCompressOnly = true in {907def : CompressPat<(ADD GPRNoX0:$rs1, X0, GPRNoX0:$rs2),908 (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;909def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, X0),910 (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;911}912def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),913 (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;914def : CompressPat<(EBREAK), (C_EBREAK)>;915def : CompressPat<(UNIMP), (C_UNIMP)>;916def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),917 (C_JALR GPRNoX0:$rs1)>;918def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),919 (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;920let isCompressOnly = true in921def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),922 (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;923} // Predicates = [HasStdExtZca]924 925let Predicates = [HasStdExtZca] in {926def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),927 (C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;928 929let isCompressOnly = true in930def : CompressPat<(SW_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),931 (C_SWSP_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;932} // Predicates = [HasStdExtZca]933 934let Predicates = [HasStdExtZca, IsRV64] in {935def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),936 (C_SDSP GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;937} // Predicates = [HasStdExtZca, IsRV64]938 939// Zcf Instructions940let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {941 // Quadrant 0942 def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),943 (C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;944 def : CompressPat<(FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),945 (C_FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;946 947 // Quadrant 2948 def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),949 (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;950 def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),951 (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;952} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]953 954// Zcd Instructions955let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {956 // Quadrant 0957 def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),958 (C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;959 def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),960 (C_FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;961 962 // Quadrant 2963 def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),964 (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;965 def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),966 (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;967} // Predicates = [HasStdExtCOrZcd, HasStdExtD]968