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1//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'D',10// Double-Precision Floating-Point instruction set extension.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// RISC-V specific DAG Nodes.16//===----------------------------------------------------------------------===//17 18def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,19 SDTCisVT<1, i32>,20 SDTCisSameAs<1, 2>]>;21def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>,22 SDTCisVT<1, i32>,23 SDTCisVT<2, f64>]>;24 25def RISCVBuildPairF64 : RVSDNode<"BuildPairF64", SDT_RISCVBuildPairF64>;26def : GINodeEquiv<G_MERGE_VALUES, RISCVBuildPairF64>;27def RISCVSplitF64 : RVSDNode<"SplitF64", SDT_RISCVSplitF64>;28def : GINodeEquiv<G_UNMERGE_VALUES, RISCVSplitF64>;29 30//===----------------------------------------------------------------------===//31// Operand and SDNode transformation definitions.32//===----------------------------------------------------------------------===//33 34// Zdinx35 36def GPRPairAsFPR : AsmOperandClass {37 let Name = "GPRPairAsFPR";38 let ParserMethod = "parseGPRPairAsFPR64";39 let PredicateMethod = "isGPRPairAsFPR64";40 let RenderMethod = "addRegOperands";41}42 43def GPRF64AsFPR : AsmOperandClass {44 let Name = "GPRF64AsFPR";45 let PredicateMethod = "isGPRAsFPR";46 let ParserMethod = "parseGPRAsFPR64";47 let RenderMethod = "addRegOperands";48}49 50def FPR64INX : RegisterOperand<GPR> {51 let ParserMatchClass = GPRF64AsFPR;52 let DecoderMethod = "DecodeGPRRegisterClass";53}54 55def FPR64IN32X : RegisterOperand<GPRPair> {56 let ParserMatchClass = GPRPairAsFPR;57}58 59def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;60 61def ZdinxExt : ExtInfo<"_INX", "Zfinx", [HasStdExtZdinx, IsRV64],62 f64, FPR64INX, FPR32INX, FPR64INX, ?, i64>;63def Zdinx32Ext : ExtInfo<"_IN32X", "ZdinxRV32Only", [HasStdExtZdinx, IsRV32],64 f64, FPR64IN32X, FPR32INX, FPR64IN32X, ?, i32>;65 66defvar DExts = [DExt, ZdinxExt, Zdinx32Ext];67defvar DExtsRV64 = [DExt, ZdinxExt];68 69//===----------------------------------------------------------------------===//70// Instructions71//===----------------------------------------------------------------------===//72 73let Predicates = [HasStdExtD] in {74let canFoldAsLoad = 1, isReMaterializable = 1 in75def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>;76 77// Operands for stores are in the order srcreg, base, offset rather than78// reflecting the order these fields are specified in the instruction79// encoding.80def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;81} // Predicates = [HasStdExtD]82 83foreach Ext = DExts in {84 let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in {85 defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", Ext>;86 defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", Ext>;87 defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", Ext>;88 defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", Ext>;89 }90 91 let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in {92 defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", Ext, Commutable=1>;93 defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", Ext>;94 }95 let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in96 defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", Ext, Commutable=1>;97 98 let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in99 defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", Ext>;100 101 defm FSQRT_D : FPUnaryOp_r_frm_m<0b0101101, 0b00000, Ext, Ext.PrimaryTy,102 Ext.PrimaryTy, "fsqrt.d">,103 Sched<[WriteFSqrt64, ReadFSqrt64]>;104 105 let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64],106 mayRaiseFPException = 0 in {107 defm FSGNJ_D : FPALU_rr_m<0b0010001, 0b000, "fsgnj.d", Ext>;108 defm FSGNJN_D : FPALU_rr_m<0b0010001, 0b001, "fsgnjn.d", Ext>;109 defm FSGNJX_D : FPALU_rr_m<0b0010001, 0b010, "fsgnjx.d", Ext>;110 }111 112 let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {113 defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", Ext, Commutable=1>;114 defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", Ext, Commutable=1>;115 }116 117 defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, Ext, Ext.F32Ty,118 Ext.PrimaryTy, "fcvt.s.d">,119 Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;120 121 defm FCVT_D_S : FPUnaryOp_r_frmlegacy_m<0b0100001, 0b00000, Ext, Ext.PrimaryTy,122 Ext.F32Ty, "fcvt.d.s">,123 Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;124 125 let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in {126 defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", Ext, Commutable=1>;127 defm FLT_D : FPCmp_rr_m<0b1010001, 0b001, "flt.d", Ext>;128 defm FLE_D : FPCmp_rr_m<0b1010001, 0b000, "fle.d", Ext>;129 }130 131 let mayRaiseFPException = 0 in132 defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy,133 "fclass.d">,134 Sched<[WriteFClass64, ReadFClass64]>;135 136 let IsSignExtendingOpW = 1 in137 defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, Ext, GPR, Ext.PrimaryTy,138 "fcvt.w.d">,139 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;140 141 let IsSignExtendingOpW = 1 in142 defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, Ext, GPR, Ext.PrimaryTy,143 "fcvt.wu.d">,144 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;145 146 let mayRaiseFPException = 0 in147 defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext,148 Ext.PrimaryTy, GPR, "fcvt.d.w">,149 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;150 151 let mayRaiseFPException = 0 in152 defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext,153 Ext.PrimaryTy, GPR, "fcvt.d.wu">,154 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;155} // foreach Ext = DExts156 157foreach Ext = DExtsRV64 in {158 defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, Ext, GPR, Ext.PrimaryTy,159 "fcvt.l.d", [IsRV64]>,160 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;161 162 defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, Ext, GPR, Ext.PrimaryTy,163 "fcvt.lu.d", [IsRV64]>,164 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;165 166 defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, Ext, Ext.PrimaryTy, GPR,167 "fcvt.d.l", [IsRV64]>,168 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;169 170 defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, Ext, Ext.PrimaryTy, GPR,171 "fcvt.d.lu", [IsRV64]>,172 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;173} // foreach Ext = DExts64174 175let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in176def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,177 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;178 179let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in180def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">,181 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;182 183//===----------------------------------------------------------------------===//184// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)185//===----------------------------------------------------------------------===//186 187let Predicates = [HasStdExtD] in {188def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;189def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;190 191def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;192def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;193def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;194 195// fgt.d/fge.d are recognised by the GNU assembler but the canonical196// flt.d/fle.d forms will always be printed. Therefore, set a zero weight.197def : InstAlias<"fgt.d $rd, $rs, $rt",198 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;199def : InstAlias<"fge.d $rd, $rs, $rt",200 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;201 202def PseudoFLD : PseudoFloatLoad<"fld", FPR64>;203def PseudoFSD : PseudoStore<"fsd", FPR64>;204let usesCustomInserter = 1 in {205def PseudoQuietFLE_D : PseudoQuietFCMP<FPR64>;206def PseudoQuietFLT_D : PseudoQuietFCMP<FPR64>;207}208} // Predicates = [HasStdExtD]209 210let Predicates = [HasStdExtZdinx, IsRV64] in {211def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;212def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;213def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;214 215def : InstAlias<"fgt.d $rd, $rs, $rt",216 (FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>;217def : InstAlias<"fge.d $rd, $rs, $rt",218 (FLE_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>;219let usesCustomInserter = 1 in {220def PseudoQuietFLE_D_INX : PseudoQuietFCMP<FPR64INX>;221def PseudoQuietFLT_D_INX : PseudoQuietFCMP<FPR64INX>;222}223} // Predicates = [HasStdExtZdinx, IsRV64]224 225let Predicates = [HasStdExtZdinx, IsRV32] in {226def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>;227def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>;228def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>;229 230def : InstAlias<"fgt.d $rd, $rs, $rt",231 (FLT_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>;232def : InstAlias<"fge.d $rd, $rs, $rt",233 (FLE_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>;234let usesCustomInserter = 1 in {235def PseudoQuietFLE_D_IN32X : PseudoQuietFCMP<FPR64IN32X>;236def PseudoQuietFLT_D_IN32X : PseudoQuietFCMP<FPR64IN32X>;237}238} // Predicates = [HasStdExtZdinx, IsRV32]239 240//===----------------------------------------------------------------------===//241// Pseudo-instructions and codegen patterns242//===----------------------------------------------------------------------===//243 244let Predicates = [HasStdExtD] in {245 246/// Float conversion operations247 248// f64 -> f32, f32 -> f64249def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, FRM_DYN)>;250def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1, FRM_RNE)>;251} // Predicates = [HasStdExtD]252 253let Predicates = [HasStdExtZdinx, IsRV64] in {254/// Float conversion operations255 256// f64 -> f32, f32 -> f64257def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_S_D_INX FPR64INX:$rs1, FRM_DYN)>;258def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_INX FPR32INX:$rs1, FRM_RNE)>;259} // Predicates = [HasStdExtZdinx, IsRV64]260 261let Predicates = [HasStdExtZdinx, IsRV32] in {262/// Float conversion operations263 264// f64 -> f32, f32 -> f64265def : Pat<(any_fpround FPR64IN32X:$rs1),266 (FCVT_S_D_IN32X FPR64IN32X:$rs1, (i32 FRM_DYN))>;267def : Pat<(any_fpextend FPR32INX:$rs1),268 (FCVT_D_S_IN32X FPR32INX:$rs1, (i32 FRM_RNE))>;269} // Predicates = [HasStdExtZdinx, IsRV32]270 271// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so272// are defined later.273 274/// Float arithmetic operations275 276foreach Ext = DExts in {277 defm : PatFprFprDynFrm_m<any_fadd, FADD_D, Ext>;278 defm : PatFprFprDynFrm_m<any_fsub, FSUB_D, Ext>;279 defm : PatFprFprDynFrm_m<any_fmul, FMUL_D, Ext>;280 defm : PatFprFprDynFrm_m<any_fdiv, FDIV_D, Ext>;281}282 283let Predicates = [HasStdExtD] in {284def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, FRM_DYN)>;285 286def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;287def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;288 289def : Pat<(riscv_fclass FPR64:$rs1), (FCLASS_D $rs1)>;290 291def : PatFprFpr<fcopysign, FSGNJ_D, FPR64, f64>;292def : PatFprFpr<riscv_fsgnjx, FSGNJX_D, FPR64, f64>;293def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)),294 (FSGNJN_D FPR64:$rs1, FPR64:$rs2)>;295def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2,296 FRM_RNE))>;297def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,298 FRM_DYN))>;299 300// fmadd: rs1 * rs2 + rs3301def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),302 (FMADD_D $rs1, $rs2, $rs3, FRM_DYN)>;303 304// fmsub: rs1 * rs2 - rs3305def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),306 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;307 308// fnmsub: -rs1 * rs2 + rs3309def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),310 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;311 312// fnmadd: -rs1 * rs2 - rs3313def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),314 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;315 316// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)317def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),318 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;319} // Predicates = [HasStdExtD]320 321let Predicates = [HasStdExtZdinx, IsRV64] in {322def : Pat<(any_fsqrt FPR64INX:$rs1), (FSQRT_D_INX FPR64INX:$rs1, FRM_DYN)>;323 324def : Pat<(fneg FPR64INX:$rs1), (FSGNJN_D_INX $rs1, $rs1)>;325def : Pat<(fabs FPR64INX:$rs1), (FSGNJX_D_INX $rs1, $rs1)>;326 327def : Pat<(i64 (riscv_fclass FPR64INX:$rs1)), (FCLASS_D_INX $rs1)>;328 329def : PatFprFpr<fcopysign, FSGNJ_D_INX, FPR64INX, f64>;330def : PatFprFpr<riscv_fsgnjx, FSGNJX_D_INX, FPR64INX, f64>;331def : Pat<(fcopysign FPR64INX:$rs1, (fneg FPR64INX:$rs2)),332 (FSGNJN_D_INX FPR64INX:$rs1, FPR64INX:$rs2)>;333def : Pat<(fcopysign FPR64INX:$rs1, FPR32INX:$rs2),334 (FSGNJ_D_INX $rs1, (f64 (FCVT_D_S_INX $rs2, FRM_RNE)))>;335def : Pat<(fcopysign FPR32INX:$rs1, FPR64INX:$rs2),336 (FSGNJ_S_INX $rs1, (FCVT_S_D_INX $rs2, FRM_DYN))>;337 338// fmadd: rs1 * rs2 + rs3339def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3),340 (FMADD_D_INX $rs1, $rs2, $rs3, FRM_DYN)>;341 342// fmsub: rs1 * rs2 - rs3343def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, (fneg FPR64INX:$rs3)),344 (FMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;345 346// fnmsub: -rs1 * rs2 + rs3347def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, FPR64INX:$rs3),348 (FNMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;349 350// fnmadd: -rs1 * rs2 - rs3351def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, (fneg FPR64INX:$rs3)),352 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;353 354// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)355def : Pat<(fneg (any_fma_nsz FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3)),356 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;357} // Predicates = [HasStdExtZdinx, IsRV64]358 359let Predicates = [HasStdExtZdinx, IsRV32] in {360def : Pat<(any_fsqrt FPR64IN32X:$rs1),361 (FSQRT_D_IN32X FPR64IN32X:$rs1, (i32 FRM_DYN))>;362 363def : Pat<(fneg FPR64IN32X:$rs1), (FSGNJN_D_IN32X $rs1, $rs1)>;364def : Pat<(fabs FPR64IN32X:$rs1), (FSGNJX_D_IN32X $rs1, $rs1)>;365 366def : Pat<(i32 (riscv_fclass FPR64IN32X:$rs1)), (FCLASS_D_IN32X $rs1)>;367 368def : PatFprFpr<fcopysign, FSGNJ_D_IN32X, FPR64IN32X, f64>;369def : PatFprFpr<riscv_fsgnjx, FSGNJX_D_IN32X, FPR64IN32X, f64>;370def : Pat<(fcopysign FPR64IN32X:$rs1, (fneg FPR64IN32X:$rs2)),371 (FSGNJN_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2)>;372def : Pat<(fcopysign FPR64IN32X:$rs1, FPR32INX:$rs2),373 (FSGNJ_D_IN32X $rs1, (FCVT_D_S_IN32X $rs2, (i32 FRM_RNE)))>;374def : Pat<(fcopysign FPR32INX:$rs1, FPR64IN32X:$rs2),375 (FSGNJ_S_INX $rs1, (FCVT_S_D_IN32X $rs2, (i32 FRM_DYN)))>;376 377// fmadd: rs1 * rs2 + rs3378def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3),379 (FMADD_D_IN32X $rs1, $rs2, $rs3, (i32 FRM_DYN))>;380 381// fmsub: rs1 * rs2 - rs3382def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)),383 (FMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3,384 (i32 FRM_DYN))>;385 386// fnmsub: -rs1 * rs2 + rs3387def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, FPR64IN32X:$rs3),388 (FNMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3,389 (i32 FRM_DYN))>;390 391// fnmadd: -rs1 * rs2 - rs3392def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)),393 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3,394 (i32 FRM_DYN))>;395 396// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)397def : Pat<(fneg (any_fma_nsz FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3)),398 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3,399 (i32 FRM_DYN))>;400} // Predicates = [HasStdExtZdinx, IsRV32]401 402// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches403// LLVM's fminnum and fmaxnum.404// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.405foreach Ext = DExts in {406 defm : PatFprFpr_m<fminnum, FMIN_D, Ext>;407 defm : PatFprFpr_m<fmaxnum, FMAX_D, Ext>;408 defm : PatFprFpr_m<fminimumnum, FMIN_D, Ext>;409 defm : PatFprFpr_m<fmaximumnum, FMAX_D, Ext>;410 defm : PatFprFpr_m<riscv_fmin, FMIN_D, Ext>;411 defm : PatFprFpr_m<riscv_fmax, FMAX_D, Ext>;412 let Predicates = Ext.Predicates in413 def : Pat<(f64 (fcanonicalize FPR64:$rs1)), (FMIN_D $rs1, $rs1)>;414}415 416/// Setcc417// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for418// strict versions of those.419 420// Match non-signaling FEQ_D421foreach Ext = DExts in {422 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_D, Ext>;423 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_D, Ext>;424 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_D, Ext>;425 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_D, Ext>;426 defm : PatSetCC_m<strict_fsetcc, SETLE, PseudoQuietFLE_D, Ext>;427 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_D, Ext>;428}429 430let Predicates = [HasStdExtD] in {431// Match signaling FEQ_D432def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),433 (AND (XLenVT (FLE_D $rs1, $rs2)),434 (XLenVT (FLE_D $rs2, $rs1)))>;435def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)),436 (AND (XLenVT (FLE_D $rs1, $rs2)),437 (XLenVT (FLE_D $rs2, $rs1)))>;438// If both operands are the same, use a single FLE.439def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)),440 (FLE_D $rs1, $rs1)>;441def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ)),442 (FLE_D $rs1, $rs1)>;443 444def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D, f64>;445def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D, f64>;446def : PatSetCC<FPR64, any_fsetccs, SETLE, FLE_D, f64>;447def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D, f64>;448} // Predicates = [HasStdExtD]449 450let Predicates = [HasStdExtZdinx, IsRV64] in {451// Match signaling FEQ_D452def : Pat<(XLenVT (strict_fsetccs FPR64INX:$rs1, FPR64INX:$rs2, SETEQ)),453 (AND (XLenVT (FLE_D_INX $rs1, $rs2)),454 (XLenVT (FLE_D_INX $rs2, $rs1)))>;455def : Pat<(XLenVT (strict_fsetccs FPR64INX:$rs1, FPR64INX:$rs2, SETOEQ)),456 (AND (XLenVT (FLE_D_INX $rs1, $rs2)),457 (XLenVT (FLE_D_INX $rs2, $rs1)))>;458// If both operands are the same, use a single FLE.459def : Pat<(XLenVT (strict_fsetccs FPR64INX:$rs1, FPR64INX:$rs1, SETEQ)),460 (FLE_D_INX $rs1, $rs1)>;461def : Pat<(XLenVT (strict_fsetccs FPR64INX:$rs1, FPR64INX:$rs1, SETOEQ)),462 (FLE_D_INX $rs1, $rs1)>;463 464def : PatSetCC<FPR64INX, any_fsetccs, SETLT, FLT_D_INX, f64, i64>;465def : PatSetCC<FPR64INX, any_fsetccs, SETOLT, FLT_D_INX, f64, i64>;466def : PatSetCC<FPR64INX, any_fsetccs, SETLE, FLE_D_INX, f64, i64>;467def : PatSetCC<FPR64INX, any_fsetccs, SETOLE, FLE_D_INX, f64, i64>;468} // Predicates = [HasStdExtZdinx, IsRV64]469 470let Predicates = [HasStdExtZdinx, IsRV32] in {471// Match signaling FEQ_D472def : Pat<(i32 (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETEQ)),473 (AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),474 (XLenVT (FLE_D_IN32X $rs2, $rs1)))>;475def : Pat<(i32 (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETOEQ)),476 (AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),477 (XLenVT (FLE_D_IN32X $rs2, $rs1)))>;478// If both operands are the same, use a single FLE.479def : Pat<(i32 (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETEQ)),480 (FLE_D_IN32X $rs1, $rs1)>;481def : Pat<(i32 (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETOEQ)),482 (FLE_D_IN32X $rs1, $rs1)>;483 484def : PatSetCC<FPR64IN32X, any_fsetccs, SETLT, FLT_D_IN32X, f64, i32>;485def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLT, FLT_D_IN32X, f64, i32>;486def : PatSetCC<FPR64IN32X, any_fsetccs, SETLE, FLE_D_IN32X, f64, i32>;487def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLE, FLE_D_IN32X, f64, i32>;488} // Predicates = [HasStdExtZdinx, IsRV32]489 490let Predicates = [HasStdExtD] in {491defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64, f64>;492 493def PseudoFROUND_D : PseudoFROUND<FPR64, f64>;494 495/// Loads496 497def : LdPat<load, FLD, f64>;498 499/// Stores500 501def : StPat<store, FSD, FPR64, f64>;502} // Predicates = [HasStdExtD]503 504let Predicates = [HasStdExtD, NoStdExtZfa, IsRV32] in {505/// Pseudo-instructions needed for the soft-float ABI with RV32D506 507// Moves two GPRs to an FPR.508let usesCustomInserter = 1 in509def BuildPairF64Pseudo510 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2),511 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;512 513// Moves an FPR to two GPRs.514let usesCustomInserter = 1 in515def SplitF64Pseudo516 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),517 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;518 519} // Predicates = [HasStdExtD, NoStdExtZfa, IsRV32]520 521let Predicates = [HasStdExtZdinx, IsRV64] in {522defm Select_FPR64INX : SelectCC_GPR_rrirr<FPR64INX, f64, i64>;523 524def PseudoFROUND_D_INX : PseudoFROUND<FPR64INX, f64>;525 526/// Loads527def : LdPat<load, LD, f64>;528 529/// Stores530def : StPat<store, SD, GPR, f64>;531} // Predicates = [HasStdExtZdinx, IsRV64]532 533let Predicates = [HasStdExtZdinx, IsRV32] in {534defm Select_FPR64IN32X : SelectCC_GPR_rrirr<FPR64IN32X, f64, i32>;535 536def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64, i32>;537 538/// Loads539let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in540def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12_lo:$imm12), []>;541 542/// Stores543let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in544def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12_lo:$imm12), []>;545} // Predicates = [HasStdExtZdinx, IsRV32]546 547let Predicates = [HasStdExtZdinx, HasStdExtZilsd, IsRV32] in {548def : LdPat<load, LD_RV32, f64, i32>;549def : StPat<store, SD_RV32, GPRPair, f64, i32>;550}551 552let Predicates = [HasStdExtD, IsRV32] in {553 554// double->[u]int. Round-to-zero must be used.555def : Pat<(i32 (any_fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, FRM_RTZ)>;556def : Pat<(i32 (any_fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, FRM_RTZ)>;557 558// Saturating double->[u]int32.559def : Pat<(i32 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_W_D $rs1, timm:$frm)>;560def : Pat<(i32 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_WU_D $rs1, timm:$frm)>;561 562// float->int32 with current rounding mode.563def : Pat<(i32 (any_lrint FPR64:$rs1)), (FCVT_W_D $rs1, FRM_DYN)>;564 565// float->int32 rounded to nearest with ties rounded away from zero.566def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, FRM_RMM)>;567 568// [u]int->double.569def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1, FRM_RNE)>;570def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1, FRM_RNE)>;571} // Predicates = [HasStdExtD, IsRV32]572 573let Predicates = [HasStdExtZdinx, IsRV32] in {574 575// double->[u]int. Round-to-zero must be used.576def : Pat<(i32 (any_fp_to_sint FPR64IN32X:$rs1)), (FCVT_W_D_IN32X FPR64IN32X:$rs1, FRM_RTZ)>;577def : Pat<(i32 (any_fp_to_uint FPR64IN32X:$rs1)), (FCVT_WU_D_IN32X FPR64IN32X:$rs1, FRM_RTZ)>;578 579// Saturating double->[u]int32.580def : Pat<(i32 (riscv_fcvt_x FPR64IN32X:$rs1, timm:$frm)), (FCVT_W_D_IN32X $rs1, timm:$frm)>;581def : Pat<(i32 (riscv_fcvt_xu FPR64IN32X:$rs1, timm:$frm)), (FCVT_WU_D_IN32X $rs1, timm:$frm)>;582 583// float->int32 with current rounding mode.584def : Pat<(i32 (any_lrint FPR64IN32X:$rs1)), (FCVT_W_D_IN32X $rs1, FRM_DYN)>;585 586// float->int32 rounded to nearest with ties rounded away from zero.587def : Pat<(i32 (any_lround FPR64IN32X:$rs1)), (FCVT_W_D_IN32X $rs1, FRM_RMM)>;588 589// [u]int->double.590def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W_IN32X GPR:$rs1, FRM_RNE)>;591def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU_IN32X GPR:$rs1, FRM_RNE)>;592} // Predicates = [HasStdExtZdinx, IsRV32]593 594let Predicates = [HasStdExtD, IsRV64] in {595 596// Moves (no conversion)597def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>;598def : Pat<(i64 (bitconvert FPR64:$rs1)), (FMV_X_D FPR64:$rs1)>;599 600// Use target specific isd nodes to help us remember the result is sign601// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be602// duplicated if it has another user that didn't need the sign_extend.603def : Pat<(riscv_any_fcvt_w_rv64 FPR64:$rs1, timm:$frm), (FCVT_W_D $rs1, timm:$frm)>;604def : Pat<(riscv_any_fcvt_wu_rv64 FPR64:$rs1, timm:$frm), (FCVT_WU_D $rs1, timm:$frm)>;605 606// [u]int32->fp607def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1, FRM_RNE)>;608def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1, FRM_RNE)>;609 610// Saturating double->[u]int64.611def : Pat<(i64 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_L_D $rs1, timm:$frm)>;612def : Pat<(i64 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_LU_D $rs1, timm:$frm)>;613 614// double->[u]int64. Round-to-zero must be used.615def : Pat<(i64 (any_fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, FRM_RTZ)>;616def : Pat<(i64 (any_fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, FRM_RTZ)>;617 618// double->int64 with current rounding mode.619def : Pat<(i64 (any_lrint FPR64:$rs1)), (FCVT_L_D $rs1, FRM_DYN)>;620def : Pat<(i64 (any_llrint FPR64:$rs1)), (FCVT_L_D $rs1, FRM_DYN)>;621 622// double->int64 rounded to nearest with ties rounded away from zero.623def : Pat<(i64 (any_lround FPR64:$rs1)), (FCVT_L_D $rs1, FRM_RMM)>;624def : Pat<(i64 (any_llround FPR64:$rs1)), (FCVT_L_D $rs1, FRM_RMM)>;625 626// [u]int64->fp. Match GCC and default to using dynamic rounding mode.627def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, FRM_DYN)>;628def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, FRM_DYN)>;629} // Predicates = [HasStdExtD, IsRV64]630 631let Predicates = [HasStdExtZdinx, IsRV64] in {632 633// Moves (no conversion)634def : Pat<(f64 (bitconvert (i64 GPR:$rs1))), (COPY_TO_REGCLASS GPR:$rs1, GPR)>;635def : Pat<(i64 (bitconvert (f64 GPR:$rs1))), (COPY_TO_REGCLASS GPR:$rs1, GPR)>;636 637// Use target specific isd nodes to help us remember the result is sign638// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be639// duplicated if it has another user that didn't need the sign_extend.640def : Pat<(riscv_any_fcvt_w_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_W_D_INX $rs1, timm:$frm)>;641def : Pat<(riscv_any_fcvt_wu_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_WU_D_INX $rs1, timm:$frm)>;642 643// [u]int32->fp644def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W_INX $rs1, FRM_RNE)>;645def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU_INX $rs1, FRM_RNE)>;646 647// Saturating double->[u]int64.648def : Pat<(i64 (riscv_fcvt_x FPR64INX:$rs1, timm:$frm)), (FCVT_L_D_INX $rs1, timm:$frm)>;649def : Pat<(i64 (riscv_fcvt_xu FPR64INX:$rs1, timm:$frm)), (FCVT_LU_D_INX $rs1, timm:$frm)>;650 651// double->[u]int64. Round-to-zero must be used.652def : Pat<(i64 (any_fp_to_sint FPR64INX:$rs1)), (FCVT_L_D_INX FPR64INX:$rs1, FRM_RTZ)>;653def : Pat<(i64 (any_fp_to_uint FPR64INX:$rs1)), (FCVT_LU_D_INX FPR64INX:$rs1, FRM_RTZ)>;654 655// double->int64 with current rounding mode.656def : Pat<(i64 (any_lrint FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_DYN)>;657def : Pat<(i64 (any_llrint FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_DYN)>;658 659// double->int64 rounded to nearest with ties rounded away from zero.660def : Pat<(i64 (any_lround FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_RMM)>;661def : Pat<(i64 (any_llround FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_RMM)>;662 663// [u]int64->fp. Match GCC and default to using dynamic rounding mode.664def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L_INX GPR:$rs1, FRM_DYN)>;665def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU_INX GPR:$rs1, FRM_DYN)>;666} // Predicates = [HasStdExtZdinx, IsRV64]667