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1//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Base P'10// Packed SIMD instruction set extension.11//12// This version is still experimental as the 'P' extension hasn't been13// ratified yet.14//15//===----------------------------------------------------------------------===//16 17//===----------------------------------------------------------------------===//18// Operand and SDNode transformation definitions.19//===----------------------------------------------------------------------===//20 21def simm10 : RISCVSImmOp<10>, ImmLeaf<XLenVT, "return isInt<10>(Imm);">;22 23def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> {24 let RenderMethod = "addSImm8UnsignedOperands";25}26 27// (<2 x i16>, <2 x i16>) PPACK_DH (<4 x i8>, <4 x i8>, <4 x i8>, <4 x i8>)28def SDT_RISCVPPackDH29 : SDTypeProfile<2, 4, [SDTCisVT<0, v2i16>, SDTCisSameAs<0, 1>,30 SDTCisVT<2, v4i8>, SDTCisSameAs<0, 3>,31 SDTCisSameAs<0, 4>, SDTCisSameAs<0, 5>]>;32def riscv_ppack_dh : RVSDNode<"PPACK_DH", SDT_RISCVPPackDH>;33 34// A 8-bit signed immediate allowing range [-128, 255]35// but represented as [-128, 127].36def simm8_unsigned : RISCVOp, ImmLeaf<XLenVT, "return isInt<8>(Imm);"> {37 let ParserMatchClass = SImm8UnsignedAsmOperand;38 let EncoderMethod = "getImmOpValue";39 let DecoderMethod = "decodeSImmOperand<8>";40 let OperandType = "OPERAND_SIMM8_UNSIGNED";41 let MCOperandPredicate = [{42 int64_t Imm;43 if (!MCOp.evaluateAsConstantImm(Imm))44 return false;45 return isInt<8>(Imm);46 }];47}48 49def SImm10UnsignedAsmOperand : SImmAsmOperand<10, "Unsigned"> {50 let RenderMethod = "addSImm10UnsignedOperands";51}52 53// A 10-bit signed immediate allowing range [-512, 1023]54// but represented as [-512, 511].55def simm10_unsigned : RISCVOp {56 let ParserMatchClass = SImm10UnsignedAsmOperand;57 let EncoderMethod = "getImmOpValue";58 let DecoderMethod = "decodeSImmOperand<10>";59 let OperandType = "OPERAND_SIMM10_UNSIGNED";60 let MCOperandPredicate = [{61 int64_t Imm;62 if (!MCOp.evaluateAsConstantImm(Imm))63 return false;64 return isInt<10>(Imm);65 }];66}67 68//===----------------------------------------------------------------------===//69// Instruction class templates70//===----------------------------------------------------------------------===//71 72// Common base for pli.b/h/w and plui.h/w73class RVPLoadImm_i<bits<7> funct7, dag ins, string opcodestr,74 string argstr>75 : RVInst<(outs GPR:$rd), ins, opcodestr, argstr, [],76 InstFormatOther> {77 bits<5> rd;78 79 let Inst{31-25} = funct7;80 let Inst{14-12} = 0b010;81 let Inst{11-7} = rd;82 let Inst{6-0} = OPC_OP_IMM_32.Value;83 84 let hasSideEffects = 0;85 let mayLoad = 0;86 let mayStore = 0;87}88 89// Base for pli.h/w.90class PLI_i<bits<7> funct7, string opcodestr>91 : RVPLoadImm_i<funct7, (ins simm10:$imm10), opcodestr, "$rd, $imm10"> {92 bits<10> imm10;93 94 let Inst{24-16} = imm10{8-0};95 let Inst{15} = imm10{9};96}97 98// Base for plui.h/w.99class PLUI_i<bits<7> funct7, string opcodestr>100 : RVPLoadImm_i<funct7, (ins simm10_unsigned:$imm10), opcodestr,101 "$rd, $imm10"> {102 bits<10> imm10;103 104 let Inst{24} = imm10{0};105 let Inst{23-15} = imm10{9-1};106}107 108// Common base for widening Binary/Ternary ops109class RVPWideningBase<bits<2> w, bit arith_shift, dag outs, dag ins,110 string opcodestr>111 : RVInst<outs, ins, opcodestr, "$rd, $rs1, $rs2", [], InstFormatOther> {112 bits<5> rs2;113 bits<5> rs1;114 bits<5> rd;115 116 let Inst{31} = 0b0;117 let Inst{26-25} = w;118 let Inst{24-20} = rs2;119 let Inst{19-15} = rs1;120 let Inst{14-12} = 0b010;121 let Inst{11-8} = rd{4-1};122 let Inst{7} = arith_shift;123 let Inst{6-0} = OPC_OP_IMM_32.Value;124}125 126// Common base for narrowing ops127class RVPNarrowingBase<bits<3> f, bit r, bits<4> funct4, dag outs, dag ins,128 string opcodestr, string argstr>129 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {130 bits<5> rs1;131 bits<5> rd;132 133 let Inst{31} = 0b0;134 let Inst{30-28} = f;135 let Inst{27} = r;136 let Inst{19-16} = rs1{4-1};137 let Inst{15-12} = funct4;138 let Inst{11-7} = rd;139 let Inst{6-0} = OPC_OP_IMM_32.Value;140}141 142// Common base for pair ops (non-widening nor narrowing)143class RVPPairBase<bits<3> f, bit r, bit direction, dag outs, dag ins,144 string opcodestr, string argstr>145 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {146 bits<5> rs1;147 bits<5> rd;148 149 let Inst{30-28} = f;150 let Inst{27} = r;151 let Inst{19-16} = rs1{4-1};152 let Inst{15} = direction;153 let Inst{14-12} = 0b110;154 let Inst{11-8} = rd{4-1};155 let Inst{7} = 0b0;156 let Inst{6-0} = OPC_OP_IMM_32.Value;157}158 159// Common base for pair binary ops160class RVPPairBinaryBase_rr<bits<3> f, bit r, bits<2> w, bit pack, bit direction,161 string opcodestr>162 : RVPPairBase<f, r, direction, (outs GPRPairRV32:$rd),163 (ins GPRPairRV32:$rs1, GPRPairRV32:$rs2), opcodestr,164 "$rd, $rs1, $rs2"> {165 bits<5> rs2;166 167 let Inst{31} = 0b1;168 let Inst{26-25} = w;169 let Inst{24-21} = rs2{4-1};170 let Inst{20} = pack;171}172 173let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in174class RVPShift_ri<bits<3> f, bits<3> funct3, string opcodestr, Operand ImmType>175 : RVInstIBase<funct3, OPC_OP_IMM_32, (outs GPR:$rd),176 (ins GPR:$rs1, ImmType:$shamt), opcodestr,177 "$rd, $rs1, $shamt"> {178 let Inst{31} = 0b1;179 let Inst{30-28} = f;180 let Inst{27} = 0b0;181}182 183class RVPShiftD_ri<bits<3> f, bits<3> funct3, string opcodestr>184 : RVPShift_ri<f, funct3, opcodestr, uimm6> {185 bits<6> shamt;186 187 let Inst{26} = 0b1;188 let Inst{25-20} = shamt;189}190 191class RVPShiftW_ri<bits<3> f, bits<3> funct3, string opcodestr>192 : RVPShift_ri<f, funct3, opcodestr, uimm5> {193 bits<5> shamt;194 195 let Inst{26-25} = 0b01;196 let Inst{24-20} = shamt;197}198 199class RVPShiftH_ri<bits<3> f, bits<3> funct3, string opcodestr>200 : RVPShift_ri<f, funct3, opcodestr, uimm4> {201 bits<4> shamt;202 203 let Inst{26-24} = 0b001;204 let Inst{23-20} = shamt;205}206 207class RVPShiftB_ri<bits<3> f, bits<3> funct3, string opcodestr>208 : RVPShift_ri<f, funct3, opcodestr, uimm3> {209 bits<3> shamt;210 211 let Inst{26-23} = 0b0001;212 let Inst{22-20} = shamt;213}214 215let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in216class RVPWideningShift_ri<bits<3> f, string opcodestr, Operand ImmType>217 : RVInst<(outs GPRPairRV32:$rd), (ins GPR:$rs1, ImmType:$shamt), opcodestr,218 "$rd, $rs1, $shamt", [], InstFormatOther> {219 bits<5> rs1;220 bits<5> rd;221 222 let Inst{31} = 0b0;223 let Inst{30-28} = f;224 let Inst{27} = 0b0;225 let Inst{19-15} = rs1;226 let Inst{14-12} = 0b010;227 let Inst{11-8} = rd{4-1};228 let Inst{7} = 0b0;229 let Inst{6-0} = OPC_OP_IMM_32.Value;230 231 let hasSideEffects = 0;232 let mayLoad = 0;233 let mayStore = 0;234}235 236class RVPWideningShiftW_ri<bits<3> f, string opcodestr>237 : RVPWideningShift_ri<f, opcodestr, uimm6> {238 bits<6> shamt;239 240 let Inst{26} = 0b1;241 let Inst{25-20} = shamt;242}243 244class RVPWideningShiftH_ri<bits<3> f, string opcodestr>245 : RVPWideningShift_ri<f, opcodestr, uimm5> {246 bits<5> shamt;247 248 let Inst{26-25} = 0b01;249 let Inst{24-20} = shamt;250}251 252class RVPWideningShiftB_ri<bits<3> f, string opcodestr>253 : RVPWideningShift_ri<f, opcodestr, uimm4> {254 bits<4> shamt;255 256 let Inst{26-24} = 0b001;257 let Inst{23-20} = shamt;258}259 260let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in261class RVPNarrowingShift_ri<bits<3> f, string opcodestr, Operand ImmType>262 : RVPNarrowingBase<f, 0b0, 0b1100, (outs GPR:$rd),263 (ins GPRPairRV32:$rs1, ImmType:$shamt), opcodestr,264 "$rd, $rs1, $shamt">;265 266class RVPNarrowingShiftW_ri<bits<3> f, string opcodestr>267 : RVPNarrowingShift_ri<f, opcodestr, uimm6> {268 bits<6> shamt;269 270 let Inst{26} = 0b1;271 let Inst{25-20} = shamt;272}273 274class RVPNarrowingShiftH_ri<bits<3> f, string opcodestr>275 : RVPNarrowingShift_ri<f, opcodestr, uimm5> {276 bits<5> shamt;277 278 let Inst{26-25} = 0b01;279 let Inst{24-20} = shamt;280}281 282class RVPNarrowingShiftB_ri<bits<3> f, string opcodestr>283 : RVPNarrowingShift_ri<f, opcodestr, uimm4> {284 bits<4> shamt;285 286 let Inst{26-24} = 0b001;287 let Inst{23-20} = shamt;288}289 290let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in291class RVPPairShift_ri<bits<3> f, string opcodestr, Operand ImmType, 292 bit direction>293 : RVPPairBase<f, 0b0, direction, (outs GPRPairRV32:$rd),294 (ins GPRPairRV32:$rs1, ImmType:$shamt), opcodestr,295 "$rd, $rs1, $shamt"> {296 let Inst{31} = 0b0;297}298 299class RVPPairShiftW_ri<bits<3> f, string opcodestr, bit direction = 0b0>300 : RVPPairShift_ri<f, opcodestr, uimm5, direction> {301 bits<5> shamt;302 303 let Inst{26-25} = 0b01;304 let Inst{24-20} = shamt;305}306 307class RVPPairShiftH_ri<bits<3> f, string opcodestr, bit direction = 0b0>308 : RVPPairShift_ri<f, opcodestr, uimm4, direction> {309 bits<4> shamt;310 311 let Inst{26-24} = 0b001;312 let Inst{23-20} = shamt;313}314 315class RVPPairShiftB_ri<bits<3> f, string opcodestr, bit direction = 0b0>316 : RVPPairShift_ri<f, opcodestr, uimm3, direction> {317 bits<3> shamt;318 319 let Inst{26-23} = 0b0001;320 let Inst{22-20} = shamt;321}322 323let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in324class RVPNarrowingShift_rr<bits<3> f, bits<2> w, string opcodestr>325 : RVPNarrowingBase<f, 0b1, 0b1100, (outs GPR:$rd),326 (ins GPRPairRV32:$rs1, GPR:$rs2), opcodestr,327 "$rd, $rs1, $rs2"> {328 bits<5> rs2;329 330 let Inst{26-25} = w;331 let Inst{24-20} = rs2;332}333 334let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in335class RVPWideningShift_rr<bits<3> f, bits<2> w, string opcodestr>336 : RVPWideningBase<w, 0b0, (outs GPRPairRV32:$rd), (ins GPR:$rs1, GPR:$rs2),337 opcodestr> {338 let Inst{30-28} = f;339 let Inst{27} = 0b1;340}341 342let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in343class RVPPairShift_rr<bits<3> f, bits<2> w, string opcodestr,344 bit direction = 0b0>345 : RVPPairBase<f, 0b1, direction, (outs GPRPairRV32:$rd),346 (ins GPRPairRV32:$rs1, GPR:$rs2), opcodestr,347 "$rd, $rs1, $rs2"> {348 bits<5> rs2;349 350 let Inst{26-25} = w;351 let Inst{24-20} = rs2;352}353 354let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in355class RVPUnary_ri<bits<2> w, bits<5> uf, string opcodestr>356 : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),357 opcodestr, "$rd, $rs1"> {358 let Inst{31-27} = 0b11100;359 let Inst{26-25} = w;360 let Inst{24-20} = uf;361}362 363let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in364class RVPPairUnary_r<bits<2> w, bits<5> uf, string opcodestr>365 : RVPPairBase<0b110, 0b0, 0b0, (outs GPRPairRV32:$rd),366 (ins GPRPairRV32:$rs1), opcodestr, "$rd, $rs1"> {367 let Inst{31} = 0b0;368 let Inst{26-25} = w;369 let Inst{24-20} = uf;370}371 372let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in373class RVPBinaryScalar_rr<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr>374 : RVInstRBase<funct3, OPC_OP_IMM_32, (outs GPR:$rd),375 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {376 let Inst{31} = 0b1;377 let Inst{30-28} = f;378 let Inst{27} = 0b1;379 let Inst{26-25} = w;380}381 382let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in383class RVPBinary_rr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>384 : RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd),385 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {386 let Inst{31} = 0b1;387 let Inst{30-27} = f;388 let Inst{26-25} = w;389}390 391let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in392class RVPWideningBinary_rr<bits<4> f, bits<2> w, string opcodestr>393 : RVPWideningBase<w, 0b1, (outs GPRPairRV32:$rd), (ins GPR:$rs1, GPR:$rs2),394 opcodestr> {395 let Inst{30-27} = f;396}397 398let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in399class RVPNarrowingBinary_rr<bits<3> f, bits<2> w, string opcodestr>400 : RVPNarrowingBase<f, 0b1, 0b0100, (outs GPR:$rd),401 (ins GPRPairRV32:$rs1, GPR:$rs2), opcodestr,402 "$rd, $rs1, $rs2"> {403 bits<5> rs2;404 405 let Inst{26-25} = w;406 let Inst{24-20} = rs2;407}408 409let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in410class RVPPairBinary_rr<bits<4> f, bits<2> w, string opcodestr>411 : RVPPairBinaryBase_rr<f{3-1}, f{0}, w, 0b0, 0b0, opcodestr>;412 413let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in414class RVPPairBinaryShift_rr<bits<3> f, bits<2> w, string opcodestr>415 : RVPPairBinaryBase_rr<f, 0b0, w, 0b1, 0b0, opcodestr>;416 417let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in418class RVPPairBinaryPack_rr<bits<3> f, bits<2> w, string opcodestr>419 : RVPPairBinaryBase_rr<f, 0b0, w, 0b0, 0b1, opcodestr>;420 421let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in422class RVPPairBinaryExchanged_rr<bits<4> f, bits<2> w, string opcodestr>423 : RVPPairBinaryBase_rr<f{3-1}, f{0}, w, 0b1, 0b1, opcodestr>;424 425let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in426class RVPTernary_rrr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>427 : RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd_wb),428 (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr,429 "$rd, $rs1, $rs2"> {430 let Inst{31} = 0b1;431 let Inst{30-27} = f;432 let Inst{26-25} = w;433 434 let Constraints = "$rd = $rd_wb";435}436 437let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in438class RVPWideningTernary_rrr<bits<4> f, bits<2> w, string opcodestr>439 : RVPWideningBase<w, 0b1, (outs GPRPairRV32:$rd_wb),440 (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr> {441 let Inst{30-27} = f;442 443 let Constraints = "$rd = $rd_wb";444}445 446// Common base for pli.db/h/w and plui.dh/w447class RVPPairLoadImm_i<bits<7> funct7, dag ins, string opcodestr,448 string argstr>449 : RVInst<(outs GPRPairRV32:$rd), ins, opcodestr, argstr, [],450 InstFormatOther> {451 bits<5> rd;452 453 let Inst{31-25} = funct7;454 let Inst{14-12} = 0b010;455 let Inst{11-8} = rd{4-1};456 let Inst{7} = 0b0;457 let Inst{6-0} = OPC_OP_IMM_32.Value;458 459 let hasSideEffects = 0;460 let mayLoad = 0;461 let mayStore = 0;462}463 464//===----------------------------------------------------------------------===//465// Instructions466//===----------------------------------------------------------------------===//467 468let Predicates = [HasStdExtP] in {469 let IsSignExtendingOpW = 1 in470 def CLS : Unary_r<0b011000000011, 0b001, "cls">;471 def ABS : Unary_r<0b011000000111, 0b001, "abs">;472} // Predicates = [HasStdExtP]473 474let Predicates = [HasStdExtP, IsRV32] in {475 def REV_RV32 : Unary_r<0b011010011111, 0b101, "rev">;476} // Predicates = [HasStdExtP, IsRV32]477 478let Predicates = [HasStdExtP, IsRV64] in {479 def REV16 : Unary_r<0b011010110000, 0b101, "rev16">;480 def REV_RV64 : Unary_r<0b011010111111, 0b101, "rev">;481 482 let IsSignExtendingOpW = 1 in {483 def CLSW : UnaryW_r<0b011000000011, 0b001, "clsw">;484 def ABSW : UnaryW_r<0b011000000111, 0b001, "absw">;485 }486} // Predicates = [HasStdExtP, IsRV64]487 488let Predicates = [HasStdExtP] in {489 def PSLLI_B : RVPShiftB_ri<0b000, 0b010, "pslli.b">;490 def PSLLI_H : RVPShiftH_ri<0b000, 0b010, "pslli.h">;491 def PSSLAI_H : RVPShiftH_ri<0b101, 0b010, "psslai.h">;492} // Predicates = [HasStdExtP]493let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {494 def SSLAI : RVPShiftW_ri<0b101, 0b010, "sslai">;495} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"496let Predicates = [HasStdExtP, IsRV64] in {497 def PSLLI_W : RVPShiftW_ri<0b000, 0b010, "pslli.w">;498 def PSSLAI_W : RVPShiftW_ri<0b101, 0b010, "psslai.w">;499} // Predicates = [HasStdExtP, IsRV64]500 501let Predicates = [HasStdExtP] in502def PLI_H : PLI_i<0b1011000, "pli.h">;503let Predicates = [HasStdExtP, IsRV64] in504def PLI_W : PLI_i<0b1011001, "pli.w">;505let Predicates = [HasStdExtP] in {506 def PLI_B : RVPLoadImm_i<0b1011010, (ins simm8_unsigned:$imm8), "pli.b",507 "$rd, $imm8"> {508 bits<8> imm8;509 510 let Inst{24} = 0b0;511 let Inst{23-16} = imm8;512 let Inst{15} = 0b0;513 }514}515 516let Predicates = [HasStdExtP] in {517 def PSEXT_H_B : RVPUnary_ri<0b00, 0b00100, "psext.h.b">;518 def PSABS_H : RVPUnary_ri<0b00, 0b00111, "psabs.h">;519 def PSABS_B : RVPUnary_ri<0b10, 0b00111, "psabs.b">;520} // Predicates = [HasStdExtP]521let Predicates = [HasStdExtP, IsRV64] in {522 def PSEXT_W_B : RVPUnary_ri<0b01, 0b00100, "psext.w.b">;523 def PSEXT_W_H : RVPUnary_ri<0b01, 0b00101, "psext.w.h">;524} // Predicates = [HasStdExtP, IsRV64]525 526let Predicates = [HasStdExtP] in527def PLUI_H : PLUI_i<0b1111000, "plui.h">;528let Predicates = [HasStdExtP, IsRV64] in529def PLUI_W : PLUI_i<0b1111001, "plui.w">;530 531let Predicates = [HasStdExtP] in {532 def PSLL_HS : RVPBinaryScalar_rr<0b000, 0b00, 0b010, "psll.hs">;533 def PSLL_BS : RVPBinaryScalar_rr<0b000, 0b10, 0b010, "psll.bs">;534 535 def PADD_HS : RVPBinaryScalar_rr<0b001, 0b00, 0b010, "padd.hs">;536 def PADD_BS : RVPBinaryScalar_rr<0b001, 0b10, 0b010, "padd.bs">;537 538 def PSSHA_HS : RVPBinaryScalar_rr<0b110, 0b00, 0b010, "pssha.hs">;539 540 def PSSHAR_HS : RVPBinaryScalar_rr<0b111, 0b00, 0b010, "psshar.hs">;541} // Predicates = [HasStdExtP]542let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {543 def SSHA : RVPBinaryScalar_rr<0b110, 0b01, 0b010, "ssha">;544 545 def SSHAR : RVPBinaryScalar_rr<0b111, 0b01, 0b010, "sshar">;546} // Predicates = [HasStdExtP, IsRV32]547let Predicates = [HasStdExtP, IsRV64] in {548 def PSLL_WS : RVPBinaryScalar_rr<0b000, 0b01, 0b010, "psll.ws">;549 550 def PADD_WS : RVPBinaryScalar_rr<0b001, 0b01, 0b010, "padd.ws">;551 552 def PSSHA_WS : RVPBinaryScalar_rr<0b110, 0b01, 0b010, "pssha.ws">;553 def SHA : RVPBinaryScalar_rr<0b110, 0b11, 0b010, "sha">;554 555 def PSSHAR_WS : RVPBinaryScalar_rr<0b111, 0b01, 0b010, "psshar.ws">;556 def SHAR : RVPBinaryScalar_rr<0b111, 0b11, 0b010, "shar">;557} // Predicates = [HasStdExtP, IsRV64]558 559let Predicates = [HasStdExtP] in {560 def PSRLI_B : RVPShiftB_ri<0b000, 0b100, "psrli.b">;561 def PSRLI_H : RVPShiftH_ri<0b000, 0b100, "psrli.h">;562 563 def PUSATI_H : RVPShiftH_ri<0b010, 0b100, "pusati.h">;564 565 def PSRAI_B : RVPShiftB_ri<0b100, 0b100, "psrai.b">;566 def PSRAI_H : RVPShiftH_ri<0b100, 0b100, "psrai.h">;567 568 def PSRARI_H : RVPShiftH_ri<0b101, 0b100, "psrari.h">;569 570 def PSATI_H : RVPShiftH_ri<0b110, 0b100, "psati.h">;571} // Predicates = [HasStdExtP]572let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {573 def USATI_RV32 : RVPShiftW_ri<0b010, 0b100, "usati">;574 575 def SRARI_RV32 : RVPShiftW_ri<0b101, 0b100, "srari">;576 577 def SATI_RV32 : RVPShiftW_ri<0b110, 0b100, "sati">;578} // Predicates = [HasStdExtP, IsRV32]579let Predicates = [HasStdExtP, IsRV64] in {580 def PSRLI_W : RVPShiftW_ri<0b000, 0b100, "psrli.w">;581 def PSRAI_W : RVPShiftW_ri<0b100, 0b100, "psrai.w">;582 583 def PUSATI_W : RVPShiftW_ri<0b010, 0b100, "pusati.w">;584 def USATI_RV64 : RVPShiftD_ri<0b010, 0b100, "usati">;585 586 def PSRARI_W : RVPShiftW_ri<0b101, 0b100, "psrari.w">;587 def SRARI_RV64 : RVPShiftD_ri<0b101, 0b100, "srari">;588 589 def PSATI_W : RVPShiftW_ri<0b110, 0b100, "psati.w">;590 def SATI_RV64 : RVPShiftD_ri<0b110, 0b100, "sati">;591} // Predicates = [HasStdExtP, IsRV64]592 593let Predicates = [HasStdExtP] in {594 def PSRL_HS : RVPBinaryScalar_rr<0b000, 0b00, 0b100, "psrl.hs">;595 def PSRL_BS : RVPBinaryScalar_rr<0b000, 0b10, 0b100, "psrl.bs">;596 597 def PREDSUM_HS : RVPBinaryScalar_rr<0b001, 0b00, 0b100, "predsum.hs">;598 def PREDSUM_BS : RVPBinaryScalar_rr<0b001, 0b10, 0b100, "predsum.bs">;599 600 def PREDSUMU_HS : RVPBinaryScalar_rr<0b011, 0b00, 0b100, "predsumu.hs">;601 def PREDSUMU_BS : RVPBinaryScalar_rr<0b011, 0b10, 0b100, "predsumu.bs">;602 603 def PSRA_HS : RVPBinaryScalar_rr<0b100, 0b00, 0b100, "psra.hs">;604 def PSRA_BS : RVPBinaryScalar_rr<0b100, 0b10, 0b100, "psra.bs">;605} // Predicates = [HasStdExtP]606let Predicates = [HasStdExtP, IsRV64] in {607 def PSRL_WS : RVPBinaryScalar_rr<0b000, 0b01, 0b100, "psrl.ws">;608 609 def PREDSUM_WS : RVPBinaryScalar_rr<0b001, 0b01, 0b100, "predsum.ws">;610 611 def PREDSUMU_WS : RVPBinaryScalar_rr<0b011, 0b01, 0b100, "predsumu.ws">;612 613 def PSRA_WS : RVPBinaryScalar_rr<0b100, 0b01, 0b100, "psra.ws">;614} // Predicates = [HasStdExtP, IsRV64]615 616let Predicates = [HasStdExtP] in {617 def PADD_H : RVPBinary_rr<0b0000, 0b00, 0b000, "padd.h">;618 def PADD_B : RVPBinary_rr<0b0000, 0b10, 0b000, "padd.b">;619 620 def PSADD_H : RVPBinary_rr<0b0010, 0b00, 0b000, "psadd.h">;621 def PSADD_B : RVPBinary_rr<0b0010, 0b10, 0b000, "psadd.b">;622 623 def PAADD_H : RVPBinary_rr<0b0011, 0b00, 0b000, "paadd.h">;624 def PAADD_B : RVPBinary_rr<0b0011, 0b10, 0b000, "paadd.b">;625 626 def PSADDU_H : RVPBinary_rr<0b0110, 0b00, 0b000, "psaddu.h">;627 def PSADDU_B : RVPBinary_rr<0b0110, 0b10, 0b000, "psaddu.b">;628 629 def PAADDU_H : RVPBinary_rr<0b0111, 0b00, 0b000, "paaddu.h">;630 def PAADDU_B : RVPBinary_rr<0b0111, 0b10, 0b000, "paaddu.b">;631 632 def PSUB_H : RVPBinary_rr<0b1000, 0b00, 0b000, "psub.h">;633 def PSUB_B : RVPBinary_rr<0b1000, 0b10, 0b000, "psub.b">;634 635 def PDIF_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pdif.h">;636 def PDIF_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pdif.b">;637 638 def PSSUB_H : RVPBinary_rr<0b1010, 0b00, 0b000, "pssub.h">;639 def PSSUB_B : RVPBinary_rr<0b1010, 0b10, 0b000, "pssub.b">;640 641 def PASUB_H : RVPBinary_rr<0b1011, 0b00, 0b000, "pasub.h">;642 def PASUB_B : RVPBinary_rr<0b1011, 0b10, 0b000, "pasub.b">;643 644 def PDIFU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pdifu.h">;645 def PDIFU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pdifu.b">;646 647 def PSSUBU_H : RVPBinary_rr<0b1110, 0b00, 0b000, "pssubu.h">;648 def PSSUBU_B : RVPBinary_rr<0b1110, 0b10, 0b000, "pssubu.b">;649 650 def PASUBU_H : RVPBinary_rr<0b1111, 0b00, 0b000, "pasubu.h">;651 def PASUBU_B : RVPBinary_rr<0b1111, 0b10, 0b000, "pasubu.b">;652} // Predicates = [HasStdExtP]653let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {654 def SADD : RVPBinary_rr<0b0010, 0b01, 0b000, "sadd">;655 656 def AADD : RVPBinary_rr<0b0011, 0b01, 0b000, "aadd">;657 658 def SADDU : RVPBinary_rr<0b0110, 0b01, 0b000, "saddu">;659 660 def AADDU : RVPBinary_rr<0b0111, 0b01, 0b000, "aaddu">;661 662 def SSUB : RVPBinary_rr<0b1010, 0b01, 0b000, "ssub">;663 664 def ASUB : RVPBinary_rr<0b1011, 0b01, 0b000, "asub">;665 666 def SSUBU : RVPBinary_rr<0b1110, 0b01, 0b000, "ssubu">;667 668 def ASUBU : RVPBinary_rr<0b1111, 0b01, 0b000, "asubu">;669} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"670let Predicates = [HasStdExtP, IsRV64] in {671 def PADD_W : RVPBinary_rr<0b0000, 0b01, 0b000, "padd.w">;672 673 def PSADD_W : RVPBinary_rr<0b0010, 0b01, 0b000, "psadd.w">;674 675 def PAADD_W : RVPBinary_rr<0b0011, 0b01, 0b000, "paadd.w">;676 677 def PSADDU_W : RVPBinary_rr<0b0110, 0b01, 0b000, "psaddu.w">;678 679 def PAADDU_W : RVPBinary_rr<0b0111, 0b01, 0b000, "paaddu.w">;680 681 def PSUB_W : RVPBinary_rr<0b1000, 0b01, 0b000, "psub.w">;682 683 def PSSUB_W : RVPBinary_rr<0b1010, 0b01, 0b000, "pssub.w">;684 685 def PASUB_W : RVPBinary_rr<0b1011, 0b01, 0b000, "pasub.w">;686 687 def PSSUBU_W : RVPBinary_rr<0b1110, 0b01, 0b000, "pssubu.w">;688 689 def PASUBU_W : RVPBinary_rr<0b1111, 0b01, 0b000, "pasubu.w">;690} // Predicates = [HasStdExtP, IsRV64]691 692let Predicates = [HasStdExtP] in {693 def SLX : RVPBinary_rr<0b0001, 0b11, 0b001, "slx">;694 695 def PMUL_H_B01 : RVPBinary_rr<0b0010, 0b00, 0b001, "pmul.h.b01">;696 697 def MVM : RVPTernary_rrr<0b0101, 0b00, 0b001, "mvm">;698 def MVMN : RVPTernary_rrr<0b0101, 0b01, 0b001, "mvmn">;699 def MERGE : RVPTernary_rrr<0b0101, 0b10, 0b001, "merge">;700 def SRX : RVPTernary_rrr<0b0101, 0b11, 0b001, "srx">;701 702 def PMULU_H_B01 : RVPBinary_rr<0b0110, 0b00, 0b001, "pmulu.h.b01">;703 def PDIFSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pdifsumu.b">;704 705 def PDIFSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pdifsumau.b">;706} // Predicates = [HasStdExtP]707let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {708 def MUL_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "mul.h01">;709 710 def MACC_H01 : RVPTernary_rrr<0b0011, 0b01, 0b001, "macc.h01">;711 712 def MULU_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "mulu.h01">;713 714 def MACCU_H01 : RVPTernary_rrr<0b0111, 0b01, 0b001, "maccu.h01">;715} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"716let Predicates = [HasStdExtP, IsRV64] in {717 def PMUL_W_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "pmul.w.h01">;718 def MUL_W01 : RVPBinary_rr<0b0010, 0b11, 0b001, "mul.w01">;719 720 def PMACC_W_H01 : RVPTernary_rrr<0b0011, 0b01, 0b001, "pmacc.w.h01">;721 def MACC_W01 : RVPTernary_rrr<0b0011, 0b11, 0b001, "macc.w01">;722 723 def PMULU_W_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "pmulu.w.h01">;724 def MULU_W01 : RVPBinary_rr<0b0110, 0b11, 0b001, "mulu.w01">;725 726 def PMACCU_W_H01 : RVPTernary_rrr<0b0111, 0b01, 0b001, "pmaccu.w.h01">;727 def MACCU_W01 : RVPTernary_rrr<0b0111, 0b11, 0b001, "maccu.w01">;728} // Predicates = [HasStdExtP, IsRV64]729 730// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.731// Here we include the 0 in the f field to reduce number of tablegen classes.732let Predicates = [HasStdExtP] in {733 def PSH1ADD_H : RVPBinary_rr<0b0100, 0b00, 0b010, "psh1add.h">;734 735 def PSSH1SADD_H : RVPBinary_rr<0b0110, 0b00, 0b010, "pssh1sadd.h">;736} // Predicates = [HasStdExtP]737let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {738 def SSH1SADD : RVPBinary_rr<0b0110, 0b01, 0b010, "ssh1sadd">;739} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"740let Predicates = [HasStdExtP, IsRV64] in {741 def PSH1ADD_W : RVPBinary_rr<0b0100, 0b01, 0b010, "psh1add.w">;742 743 def PSSH1SADD_W : RVPBinary_rr<0b0110, 0b01, 0b010, "pssh1sadd.w">;744 745 def UNZIP8P : RVPBinary_rr<0b1100, 0b00, 0b010, "unzip8p">;746 def UNZIP16P : RVPBinary_rr<0b1100, 0b01, 0b010, "unzip16p">;747 def UNZIP8HP : RVPBinary_rr<0b1100, 0b10, 0b010, "unzip8hp">;748 def UNZIP16HP : RVPBinary_rr<0b1100, 0b11, 0b010, "unzip16hp">;749 750 def ZIP8P : RVPBinary_rr<0b1110, 0b00, 0b010, "zip8p">;751 def ZIP16P : RVPBinary_rr<0b1110, 0b01, 0b010, "zip16p">;752 def ZIP8HP : RVPBinary_rr<0b1110, 0b10, 0b010, "zip8hp">;753 def ZIP16HP : RVPBinary_rr<0b1110, 0b11, 0b010, "zip16hp">;754} // Predicates = [HasStdExtP, IsRV64]755 756let Predicates = [HasStdExtP] in {757 def PMUL_H_B00 : RVPBinary_rr<0b0000, 0b00, 0b011, "pmul.h.b00">;758 759 def PMUL_H_B11 : RVPBinary_rr<0b0010, 0b00, 0b011, "pmul.h.b11">;760 761 def PMULU_H_B00 : RVPBinary_rr<0b0100, 0b00, 0b011, "pmulu.h.b00">;762 763 def PMULU_H_B11 : RVPBinary_rr<0b0110, 0b00, 0b011, "pmulu.h.b11">;764 765 def PMULSU_H_B00 : RVPBinary_rr<0b1100, 0b00, 0b011, "pmulsu.h.b00">;766 767 def PMULSU_H_B11 : RVPBinary_rr<0b1110, 0b00, 0b011, "pmulsu.h.b11">;768} // Predicates = [HasStdExtP]769let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {770 def MUL_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "mul.h00">;771 772 def MACC_H00 : RVPTernary_rrr<0b0001, 0b01, 0b011, "macc.h00">;773 774 def MUL_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "mul.h11">;775 776 def MACC_H11 : RVPTernary_rrr<0b0011, 0b01, 0b011, "macc.h11">;777 778 def MULU_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "mulu.h00">;779 780 def MACCU_H00 : RVPTernary_rrr<0b0101, 0b01, 0b011, "maccu.h00">;781 782 def MULU_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "mulu.h11">;783 784 def MACCU_H11 : RVPTernary_rrr<0b0111, 0b01, 0b011, "maccu.h11">;785 786 def MULSU_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "mulsu.h00">;787 788 def MACCSU_H00 : RVPTernary_rrr<0b1101, 0b01, 0b011, "maccsu.h00">;789 790 def MULSU_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "mulsu.h11">;791 792 def MACCSU_H11 : RVPTernary_rrr<0b1111, 0b01, 0b011, "maccsu.h11">;793} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"794let Predicates = [HasStdExtP, IsRV64] in {795 def PMUL_W_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "pmul.w.h00">;796 def MUL_W00 : RVPBinary_rr<0b0000, 0b11, 0b011, "mul.w00">;797 798 def PMACC_W_H00 : RVPTernary_rrr<0b0001, 0b01, 0b011, "pmacc.w.h00">;799 def MACC_W00 : RVPTernary_rrr<0b0001, 0b11, 0b011, "macc.w00">;800 801 def PMUL_W_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "pmul.w.h11">;802 def MUL_W11 : RVPBinary_rr<0b0010, 0b11, 0b011, "mul.w11">;803 804 def PMACC_W_H11 : RVPTernary_rrr<0b0011, 0b01, 0b011, "pmacc.w.h11">;805 def MACC_W11 : RVPTernary_rrr<0b0011, 0b11, 0b011, "macc.w11">;806 807 def PMULU_W_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "pmulu.w.h00">;808 def MULU_W00 : RVPBinary_rr<0b0100, 0b11, 0b011, "mulu.w00">;809 810 def PMACCU_W_H00 : RVPTernary_rrr<0b0101, 0b01, 0b011, "pmaccu.w.h00">;811 def MACCU_W00 : RVPTernary_rrr<0b0101, 0b11, 0b011, "maccu.w00">;812 813 def PMULU_W_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "pmulu.w.h11">;814 def MULU_W11 : RVPBinary_rr<0b0110, 0b11, 0b011, "mulu.w11">;815 816 def PMACCU_W_H11 : RVPTernary_rrr<0b0111, 0b01, 0b011, "pmaccu.w.h11">;817 def MACCU_W11 : RVPTernary_rrr<0b0111, 0b11, 0b011, "maccu.w11">;818 819 def PMULSU_W_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "pmulsu.w.h00">;820 def MULSU_W00 : RVPBinary_rr<0b1100, 0b11, 0b011, "mulsu.w00">;821 822 def PMACCSU_W_H00 : RVPTernary_rrr<0b1101, 0b01, 0b011, "pmaccsu.w.h00">;823 def MACCSU_W00 : RVPTernary_rrr<0b1101, 0b11, 0b011, "maccsu.w00">;824 825 def PMULSU_W_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "pmulsu.w.h11">;826 def MULSU_W11 : RVPBinary_rr<0b1110, 0b11, 0b011, "mulsu.w11">;827 828 def PMACCSU_W_H11 : RVPTernary_rrr<0b1111, 0b01, 0b011, "pmaccsu.w.h11">;829 def MACCSU_W11 : RVPTernary_rrr<0b1111, 0b11, 0b011, "maccsu.w11">;830} // Predicates = [HasStdExtP, IsRV64]831 832// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.833// Here we include the 0 in the f field to reduce number of tablegen classes.834let Predicates = [HasStdExtP] in {835 def PPACK_H : RVPBinary_rr<0b0000, 0b00, 0b100, "ppack.h">;836 837 def PPACKBT_H : RVPBinary_rr<0b0010, 0b00, 0b100, "ppackbt.h">;838 839 def PPACKTB_H : RVPBinary_rr<0b0100, 0b00, 0b100, "ppacktb.h">;840 841 def PPACKT_H : RVPBinary_rr<0b0110, 0b00, 0b100, "ppackt.h">;842} // Predicates = [HasStdExtP]843let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {844 def PACKBT_RV32 : RVPBinary_rr<0b0010, 0b01, 0b100, "packbt">;845 846 def PACKTB_RV32 : RVPBinary_rr<0b0100, 0b01, 0b100, "packtb">;847 848 def PACKT_RV32 : RVPBinary_rr<0b0110, 0b01, 0b100, "packt">;849} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"850let Predicates = [HasStdExtP, IsRV64] in {851 def PPACK_W : RVPBinary_rr<0b0000, 0b01, 0b100, "ppack.w">;852 853 def PPACKBT_W : RVPBinary_rr<0b0010, 0b01, 0b100, "ppackbt.w">;854 def PACKBT_RV64 : RVPBinary_rr<0b0010, 0b11, 0b100, "packbt">;855 856 def PPACKTB_W : RVPBinary_rr<0b0100, 0b01, 0b100, "ppacktb.w">;857 def PACKTB_RV64 : RVPBinary_rr<0b0100, 0b11, 0b100, "packtb">;858 859 def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;860 def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;861} // Predicates = [HasStdExtP, IsRV64]862 863let Predicates = [HasStdExtP] in {864 def PM2ADD_H : RVPBinary_rr<0b0000, 0b00, 0b101, "pm2add.h">;865 def PM4ADD_B : RVPBinary_rr<0b0000, 0b10, 0b101, "pm4add.b">;866 867 def PM2ADDA_H : RVPTernary_rrr<0b0001, 0b00, 0b101, "pm2adda.h">;868 def PM4ADDA_B : RVPTernary_rrr<0b0001, 0b10, 0b101, "pm4adda.b">;869 870 def PM2ADD_HX : RVPBinary_rr<0b0010, 0b00, 0b101, "pm2add.hx">;871 872 def PM2ADDA_HX : RVPTernary_rrr<0b0011, 0b00, 0b101, "pm2adda.hx">;873 874 def PM2ADDU_H : RVPBinary_rr<0b0100, 0b00, 0b101, "pm2addu.h">;875 def PM4ADDU_B : RVPBinary_rr<0b0100, 0b10, 0b101, "pm4addu.b">;876 877 def PM2ADDAU_H : RVPTernary_rrr<0b0101, 0b00, 0b101, "pm2addau.h">;878 def PM4ADDAU_B : RVPTernary_rrr<0b0101, 0b10, 0b101, "pm4addau.b">;879 880 def PMQ2ADD_H : RVPBinary_rr<0b0110, 0b00, 0b101, "pmq2add.h">;881 def PMQR2ADD_H : RVPBinary_rr<0b0110, 0b10, 0b101, "pmqr2add.h">;882 883 def PMQ2ADDA_H : RVPTernary_rrr<0b0111, 0b00, 0b101, "pmq2adda.h">;884 def PMQR2ADDA_H : RVPTernary_rrr<0b0111, 0b10, 0b101, "pmqr2adda.h">;885 886 def PM2SUB_H : RVPBinary_rr<0b1000, 0b00, 0b101, "pm2sub.h">;887 def PM2SADD_H : RVPBinary_rr<0b1000, 0b10, 0b101, "pm2sadd.h">;888 889 def PM2SUBA_H : RVPTernary_rrr<0b1001, 0b00, 0b101, "pm2suba.h">;890 891 def PM2SUB_HX : RVPBinary_rr<0b1010, 0b00, 0b101, "pm2sub.hx">;892 def PM2SADD_HX : RVPBinary_rr<0b1010, 0b10, 0b101, "pm2sadd.hx">;893 894 def PM2SUBA_HX : RVPTernary_rrr<0b1011, 0b00, 0b101, "pm2suba.hx">;895 896 def PM2ADDSU_H : RVPBinary_rr<0b1100, 0b00, 0b101, "pm2addsu.h">;897 def PM4ADDSU_B : RVPBinary_rr<0b1100, 0b10, 0b101, "pm4addsu.b">;898 899 def PM2ADDASU_H : RVPBinary_rr<0b1101, 0b00, 0b101, "pm2addasu.h">;900 def PM4ADDASU_B : RVPBinary_rr<0b1101, 0b10, 0b101, "pm4addasu.b">;901} // Predicates = [HasStdExtP]902let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {903 def MQACC_H01 : RVPTernary_rrr<0b1111, 0b00, 0b101, "mqacc.h01">;904 def MQRACC_H01 : RVPTernary_rrr<0b1111, 0b10, 0b101, "mqracc.h01">;905} // // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"906let Predicates = [HasStdExtP, IsRV64] in {907 def PM2ADD_W : RVPBinary_rr<0b0000, 0b01, 0b101, "pm2add.w">;908 def PM4ADD_H : RVPBinary_rr<0b0000, 0b11, 0b101, "pm4add.h">;909 910 def PM2ADDA_W : RVPTernary_rrr<0b0001, 0b01, 0b101, "pm2adda.w">;911 def PM4ADDA_H : RVPTernary_rrr<0b0001, 0b11, 0b101, "pm4adda.h">;912 913 def PM2ADD_WX : RVPBinary_rr<0b0010, 0b01, 0b101, "pm2add.wx">;914 915 def PM2ADDA_WX : RVPTernary_rrr<0b0011, 0b01, 0b101, "pm2adda.wx">;916 917 def PM2ADDU_W : RVPBinary_rr<0b0100, 0b01, 0b101, "pm2addu.w">;918 def PM4ADDU_H : RVPBinary_rr<0b0100, 0b11, 0b101, "pm4addu.h">;919 920 def PM2ADDAU_W : RVPTernary_rrr<0b0101, 0b01, 0b101, "pm2addau.w">;921 def PM4ADDAU_H : RVPTernary_rrr<0b0101, 0b11, 0b101, "pm4addau.h">;922 923 def PMQ2ADD_W : RVPBinary_rr<0b0110, 0b01, 0b101, "pmq2add.w">;924 def PMQR2ADD_W : RVPBinary_rr<0b0110, 0b11, 0b101, "pmqr2add.w">;925 926 def PMQ2ADDA_W : RVPTernary_rrr<0b0111, 0b01, 0b101, "pmq2adda.w">;927 def PMQR2ADDA_W : RVPTernary_rrr<0b0111, 0b11, 0b101, "pmqr2adda.w">;928 929 def PM2SUB_W : RVPBinary_rr<0b1000, 0b01, 0b101, "pm2sub.w">;930 931 def PM2SUBA_W : RVPTernary_rrr<0b1001, 0b01, 0b101, "pm2suba.w">;932 933 def PM2SUB_WX : RVPBinary_rr<0b1010, 0b01, 0b101, "pm2sub.wx">;934 935 def PM2SUBA_WX : RVPBinary_rr<0b1011, 0b01, 0b101, "pm2suba.wx">;936 937 def PM2ADDSU_W : RVPBinary_rr<0b1100, 0b01, 0b101, "pm2addsu.w">;938 def PM4ADDSU_H : RVPBinary_rr<0b1100, 0b11, 0b101, "pm4addsu.h">;939 940 def PM2ADDASU_W : RVPTernary_rrr<0b1101, 0b01, 0b101, "pm2addasu.w">;941 def PM4ADDASU_H : RVPTernary_rrr<0b1101, 0b11, 0b101, "pm4addasu.h">;942 943 def PMQACC_W_H01 : RVPTernary_rrr<0b1111, 0b00, 0b101, "pmqacc.w.h01">;944 def MQACC_W01 : RVPTernary_rrr<0b1111, 0b01, 0b101, "mqacc.w01">;945 946 def PMQRACC_W_H01 : RVPTernary_rrr<0b1111, 0b10, 0b101, "pmqracc.w.h01">;947 def MQRACC_W01 : RVPTernary_rrr<0b1111, 0b11, 0b101, "mqracc.w01">;948} // Predicates = [HasStdExtP, IsRV64]949 950let Predicates = [HasStdExtP] in {951 def PAS_HX : RVPBinary_rr<0b0000, 0b00, 0b110, "pas.hx">;952 def PSA_HX : RVPBinary_rr<0b0000, 0b10, 0b110, "psa.hx">;953 954 def PSAS_HX : RVPBinary_rr<0b0010, 0b00, 0b110, "psas.hx">;955 def PSSA_HX : RVPBinary_rr<0b0010, 0b10, 0b110, "pssa.hx">;956 957 def PAAS_HX : RVPBinary_rr<0b0011, 0b00, 0b110, "paas.hx">;958 def PASA_HX : RVPBinary_rr<0b0011, 0b10, 0b110, "pasa.hx">;959 960 def PMSEQ_H : RVPBinary_rr<0b1000, 0b00, 0b110, "pmseq.h">;961 def PMSEQ_B : RVPBinary_rr<0b1000, 0b10, 0b110, "pmseq.b">;962 963 def PMSLT_H : RVPBinary_rr<0b1010, 0b00, 0b110, "pmslt.h">;964 def PMSLT_B : RVPBinary_rr<0b1010, 0b10, 0b110, "pmslt.b">;965 966 def PMSLTU_H : RVPBinary_rr<0b1011, 0b00, 0b110, "pmsltu.h">;967 def PMSLTU_B : RVPBinary_rr<0b1011, 0b10, 0b110, "pmsltu.b">;968 969 def PMIN_H : RVPBinary_rr<0b1100, 0b00, 0b110, "pmin.h">;970 def PMIN_B : RVPBinary_rr<0b1100, 0b10, 0b110, "pmin.b">;971 972 def PMINU_H : RVPBinary_rr<0b1101, 0b00, 0b110, "pminu.h">;973 def PMINU_B : RVPBinary_rr<0b1101, 0b10, 0b110, "pminu.b">;974 975 def PMAX_H : RVPBinary_rr<0b1110, 0b00, 0b110, "pmax.h">;976 def PMAX_B : RVPBinary_rr<0b1110, 0b10, 0b110, "pmax.b">;977 978 def PMAXU_H : RVPBinary_rr<0b1111, 0b00, 0b110, "pmaxu.h">;979 def PMAXU_B : RVPBinary_rr<0b1111, 0b10, 0b110, "pmaxu.b">;980} // Predicates = [HasStdExtP]981let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {982 def MSEQ : RVPBinary_rr<0b1000, 0b01, 0b110, "mseq">;983 984 def MSLT : RVPBinary_rr<0b1010, 0b01, 0b110, "mslt">;985 986 def MSLTU : RVPBinary_rr<0b1011, 0b01, 0b110, "msltu">;987} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"988let Predicates = [HasStdExtP, IsRV64] in {989 def PAS_WX : RVPBinary_rr<0b0000, 0b01, 0b110, "pas.wx">;990 def PSA_WX : RVPBinary_rr<0b0000, 0b11, 0b110, "psa.wx">;991 992 def PSAS_WX : RVPBinary_rr<0b0010, 0b01, 0b110, "psas.wx">;993 def PSSA_WX : RVPBinary_rr<0b0010, 0b11, 0b110, "pssa.wx">;994 995 def PAAS_WX : RVPBinary_rr<0b0011, 0b01, 0b110, "paas.wx">;996 def PASA_WX : RVPBinary_rr<0b0011, 0b11, 0b110, "pasa.wx">;997 998 def PMSEQ_W : RVPBinary_rr<0b1000, 0b01, 0b110, "pmseq.w">;999 1000 def PMSLT_W : RVPBinary_rr<0b1010, 0b01, 0b110, "pmslt.w">;1001 1002 def PMSLTU_W : RVPBinary_rr<0b1011, 0b01, 0b110, "pmsltu.w">;1003 1004 def PMIN_W : RVPBinary_rr<0b1100, 0b01, 0b110, "pmin.w">;1005 1006 def PMINU_W : RVPBinary_rr<0b1101, 0b01, 0b110, "pminu.w">;1007 1008 def PMAX_W : RVPBinary_rr<0b1110, 0b01, 0b110, "pmax.w">;1009 1010 def PMAXU_W : RVPBinary_rr<0b1111, 0b01, 0b110, "pmaxu.w">;1011} // Predicates = [HasStdExtP, IsRV64]1012 1013let Predicates = [HasStdExtP] in {1014 def PMULH_H : RVPBinary_rr<0b0000, 0b00, 0b111, "pmulh.h">;1015 def PMULHR_H : RVPBinary_rr<0b0000, 0b10, 0b111, "pmulhr.h">;1016 1017 def PMHACC_H : RVPTernary_rrr<0b0001, 0b00, 0b111, "pmhacc.h">;1018 def PMHRACC_H : RVPTernary_rrr<0b0001, 0b10, 0b111, "pmhracc.h">;1019 1020 def PMULHU_H : RVPBinary_rr<0b0010, 0b00, 0b111, "pmulhu.h">;1021 def PMULHRU_H : RVPBinary_rr<0b0010, 0b10, 0b111, "pmulhru.h">;1022 1023 def PMHACCU_H : RVPTernary_rrr<0b0011, 0b00, 0b111, "pmhaccu.h">;1024 def PMHRACCU_H : RVPTernary_rrr<0b0011, 0b10, 0b111, "pmhraccu.h">;1025 1026 def PMULH_H_B0 : RVPBinary_rr<0b0100, 0b00, 0b111, "pmulh.h.b0">;1027 def PMULHSU_H_B0 : RVPBinary_rr<0b0100, 0b10, 0b111, "pmulhsu.h.b0">;1028 1029 def PMHACC_H_B0 : RVPTernary_rrr<0b0101, 0b00, 0b111, "pmhacc.h.b0">;1030 def PMHACCSU_H_B0 : RVPTernary_rrr<0b0101, 0b10, 0b111, "pmhaccsu.h.b0">;1031 1032 def PMULH_H_B1 : RVPBinary_rr<0b0110, 0b00, 0b111, "pmulh.h.b1">;1033 def PMULHSU_H_B1 : RVPBinary_rr<0b0110, 0b10, 0b111, "pmulhsu.h.b1">;1034 1035 def PMHACC_H_B1 : RVPTernary_rrr<0b0111, 0b00, 0b111, "pmhacc.h.b1">;1036 def PMHACCSU_H_B1 : RVPTernary_rrr<0b0111, 0b10, 0b111, "pmhaccsu.h.b1">;1037 1038 def PMULHSU_H : RVPBinary_rr<0b1000, 0b00, 0b111, "pmulhsu.h">;1039 def PMULHRSU_H : RVPBinary_rr<0b1000, 0b10, 0b111, "pmulhrsu.h">;1040 1041 def PMHACCSU_H : RVPTernary_rrr<0b1001, 0b00, 0b111, "pmhaccsu.h">;1042 def PMHRACCSU_H : RVPTernary_rrr<0b1001, 0b10, 0b111, "pmhraccsu.h">;1043 1044 def PMULQ_H : RVPBinary_rr<0b1010, 0b00, 0b111, "pmulq.h">;1045 def PMULQR_H : RVPBinary_rr<0b1010, 0b10, 0b111, "pmulqr.h">;1046} // Predicates = [HasStdExtP]1047let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {1048 def MULHR : RVPBinary_rr<0b0000, 0b11, 0b111, "mulhr">;1049 1050 def MHACC : RVPTernary_rrr<0b0001, 0b01, 0b111, "mhacc">;1051 def MHRACC : RVPTernary_rrr<0b0001, 0b11, 0b111, "mhracc">;1052 1053 def MULHRU : RVPBinary_rr<0b0010, 0b11, 0b111, "mulhru">;1054 1055 def MHACCU : RVPTernary_rrr<0b0011, 0b01, 0b111, "mhaccu">;1056 def MHRACCU : RVPTernary_rrr<0b0011, 0b11, 0b111, "mhraccu">;1057 1058 def MULH_H0 : RVPBinary_rr<0b0100, 0b01, 0b111, "mulh.h0">;1059 def MULHSU_H0 : RVPBinary_rr<0b0100, 0b11, 0b111, "mulhsu.h0">;1060 1061 def MHACC_H0 : RVPTernary_rrr<0b0101, 0b01, 0b111, "mhacc.h0">;1062 def MHACCSU_H0 : RVPTernary_rrr<0b0101, 0b11, 0b111, "mhaccsu.h0">;1063 1064 def MULH_H1 : RVPBinary_rr<0b0110, 0b01, 0b111, "mulh.h1">;1065 def MULHSU_H1 : RVPBinary_rr<0b0110, 0b11, 0b111, "mulhsu.h1">;1066 1067 def MHACC_H1 : RVPTernary_rrr<0b0111, 0b01, 0b111, "mhacc.h1">;1068 def MHACCSU_H1 : RVPTernary_rrr<0b0111, 0b11, 0b111, "mhaccsu.h1">;1069 1070 def MULHRSU : RVPBinary_rr<0b1000, 0b11, 0b111, "mulhrsu">;1071 1072 def MHACCSU : RVPTernary_rrr<0b1001, 0b01, 0b111, "mhaccsu">;1073 def MHRACCSU : RVPTernary_rrr<0b1001, 0b11, 0b111, "mhraccsu">;1074 1075 def MULQ : RVPBinary_rr<0b1010, 0b01, 0b111, "mulq">;1076 def MULQR : RVPBinary_rr<0b1010, 0b11, 0b111, "mulqr">;1077 1078 def MQACC_H00 : RVPTernary_rrr<0b1101, 0b00, 0b111, "mqacc.h00">;1079 def MQRACC_H00 : RVPTernary_rrr<0b1101, 0b10, 0b111, "mqracc.h00">;1080 1081 def MQACC_H11 : RVPTernary_rrr<0b1111, 0b00, 0b111, "mqacc.h11">;1082 def MQRACC_H11 : RVPTernary_rrr<0b1111, 0b10, 0b111, "mqracc.h11">;1083} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in1084let Predicates = [HasStdExtP, IsRV64] in {1085 def PMULH_W : RVPBinary_rr<0b0000, 0b01, 0b111, "pmulh.w">;1086 def PMULHR_W : RVPBinary_rr<0b0000, 0b11, 0b111, "pmulhr.w">;1087 1088 def PMHACC_W : RVPTernary_rrr<0b0001, 0b01, 0b111, "pmhacc.w">;1089 def PMHRACC_W : RVPTernary_rrr<0b0001, 0b11, 0b111, "pmhracc.w">;1090 1091 def PMULHU_W : RVPBinary_rr<0b0010, 0b01, 0b111, "pmulhu.w">;1092 def PMULHRU_W : RVPBinary_rr<0b0010, 0b11, 0b111, "pmulhru.w">;1093 1094 def PMHACCU_W : RVPTernary_rrr<0b0011, 0b01, 0b111, "pmhaccu.w">;1095 def PMHRACCU_W : RVPTernary_rrr<0b0011, 0b11, 0b111, "pmhraccu.w">;1096 1097 def PMULH_W_H0 : RVPBinary_rr<0b0100, 0b01, 0b111, "pmulh.w.h0">;1098 def PMULHSU_W_H0 : RVPBinary_rr<0b0100, 0b11, 0b111, "pmulhsu.w.h0">;1099 1100 def PMHACC_W_H0 : RVPTernary_rrr<0b0101, 0b01, 0b111, "pmhacc.w.h0">;1101 def PMHACCSU_W_H0 : RVPTernary_rrr<0b0101, 0b11, 0b111, "pmhaccsu.w.h0">;1102 1103 def PMULH_W_H1 : RVPBinary_rr<0b0110, 0b01, 0b111, "pmulh.w.h1">;1104 def PMULHSU_W_H1 : RVPBinary_rr<0b0110, 0b11, 0b111, "pmulhsu.w.h1">;1105 1106 def PMHACC_W_H1 : RVPTernary_rrr<0b0111, 0b01, 0b111, "pmhacc.w.h1">;1107 def PMHACCSU_W_H1 : RVPTernary_rrr<0b0111, 0b11, 0b111, "pmhaccsu.w.h1">;1108 1109 def PMULHSU_W : RVPBinary_rr<0b1000, 0b01, 0b111, "pmulhsu.w">;1110 def PMULHRSU_W : RVPBinary_rr<0b1000, 0b11, 0b111, "pmulhrsu.w">;1111 1112 def PMHACCSU_W : RVPTernary_rrr<0b1001, 0b01, 0b111, "pmhaccsu.w">;1113 def PMHRACCSU_W : RVPTernary_rrr<0b1001, 0b11, 0b111, "pmhraccsu.w">;1114 1115 def PMULQ_W : RVPBinary_rr<0b1010, 0b01, 0b111, "pmulq.w">;1116 def PMULQR_W : RVPBinary_rr<0b1010, 0b11, 0b111, "pmulqr.w">;1117 1118 def PMQACC_W_H00 : RVPTernary_rrr<0b1101, 0b00, 0b111, "pmqacc.w.h00">;1119 def MQACC_W00 : RVPTernary_rrr<0b1101, 0b01, 0b111, "mqacc.w00">;1120 def PMQRACC_W_H00 : RVPTernary_rrr<0b1101, 0b10, 0b111, "pmqracc.w.h00">;1121 def MQRACC_W00 : RVPTernary_rrr<0b1101, 0b11, 0b111, "mqracc.w00">;1122 1123 def PMQACC_W_H11 : RVPTernary_rrr<0b1111, 0b00, 0b111, "pmqacc.w.h11">;1124 def MQACC_W11 : RVPTernary_rrr<0b1111, 0b01, 0b111, "mqacc.w11">;1125 def PMQRACC_W_H11 : RVPTernary_rrr<0b1111, 0b10, 0b111, "pmqracc.w.h11">;1126 def MQRACC_W11 : RVPTernary_rrr<0b1111, 0b11, 0b111, "mqracc.w11">;1127} // Predicates = [HasStdExtP, IsRV64]1128 1129let Predicates = [HasStdExtP, IsRV32] in {1130 def PLI_DH : RVPPairLoadImm_i<0b0011000, (ins simm10:$imm10), "pli.dh",1131 "$rd, $imm10"> {1132 bits<10> imm10;1133 1134 let Inst{24-16} = imm10{8-0};1135 let Inst{15} = imm10{9};1136 }1137 1138 def PLI_DB : RVPPairLoadImm_i<0b0011010, (ins simm8_unsigned:$imm8), "pli.db",1139 "$rd, $imm8"> {1140 bits<8> imm8;1141 1142 let Inst{24} = 0b0;1143 let Inst{23-16} = imm8;1144 let Inst{15} = 0b0;1145 }1146 1147 def PLUI_DH : RVPPairLoadImm_i<0b0111000, (ins simm10_unsigned:$imm10),1148 "plui.dh", "$rd, $imm10"> {1149 bits<10> imm10;1150 1151 let Inst{24} = imm10{0};1152 let Inst{23-15} = imm10{9-1};1153 }1154}1155 1156let Predicates = [HasStdExtP, IsRV32] in {1157 def PWSLLI_B : RVPWideningShiftB_ri<0b000, "pwslli.b">;1158 def PWSLLI_H : RVPWideningShiftH_ri<0b000, "pwslli.h">;1159 def WSLLI : RVPWideningShiftW_ri<0b000, "wslli">;1160 1161 def PWSLAI_B : RVPWideningShiftB_ri<0b100, "pwslai.b">;1162 def PWSLAI_H : RVPWideningShiftH_ri<0b100, "pwslai.h">;1163 def WSLAI : RVPWideningShiftW_ri<0b100, "wslai">;1164 1165 def PWSLL_BS : RVPWideningShift_rr<0b000, 0b00, "pwsll.bs">;1166 def PWSLL_HS : RVPWideningShift_rr<0b000, 0b01, "pwsll.hs">;1167 def WSLL : RVPWideningShift_rr<0b000, 0b11, "wsll">;1168 1169 def PWSLA_BS : RVPWideningShift_rr<0b100, 0b00, "pwsla.bs">;1170 def PWSLA_HS : RVPWideningShift_rr<0b100, 0b01, "pwsla.hs">;1171 def WSLA : RVPWideningShift_rr<0b100, 0b11, "wsla">;1172 1173 def WZIP8P : RVPWideningShift_rr<0b111, 0b00, "wzip8p">;1174 def WZIP16P : RVPWideningShift_rr<0b111, 0b01, "wzip16p">;1175 1176 def PWADD_H : RVPWideningBinary_rr<0b0000, 0b00, "pwadd.h">;1177 def WADD : RVPWideningBinary_rr<0b0000, 0b01, "wadd">;1178 def PWADD_B : RVPWideningBinary_rr<0b0000, 0b10, "pwadd.b">;1179 def PM2WADD_H : RVPWideningBinary_rr<0b0000, 0b11, "pm2wadd.h">;1180 1181 def PWADDA_H : RVPWideningTernary_rrr<0b0001, 0b00, "pwadda.h">;1182 def WADDA : RVPWideningTernary_rrr<0b0001, 0b01, "wadda">;1183 def PWADDA_B : RVPWideningTernary_rrr<0b0001, 0b10, "pwadda.b">;1184 def PM2WADDA_H : RVPWideningTernary_rrr<0b0001, 0b11, "pm2wadda.h">;1185 1186 def PWADDU_H : RVPWideningBinary_rr<0b0010, 0b00, "pwaddu.h">;1187 def WADDU : RVPWideningBinary_rr<0b0010, 0b01, "waddu">;1188 def PWADDU_B : RVPWideningBinary_rr<0b0010, 0b10, "pwaddu.b">;1189 def PM2WADD_HX : RVPWideningBinary_rr<0b0010, 0b11, "pm2wadd.hx">;1190 1191 def PWADDAU_H : RVPWideningTernary_rrr<0b0011, 0b00, "pwaddau.h">;1192 def WADDAU : RVPWideningTernary_rrr<0b0011, 0b01, "waddau">;1193 def PWADDAU_B : RVPWideningTernary_rrr<0b0011, 0b10, "pwaddau.b">;1194 def PM2WADDA_HX : RVPWideningTernary_rrr<0b0011, 0b11, "pm2wadda.hx">;1195 1196 def PWMUL_H : RVPWideningBinary_rr<0b0100, 0b00, "pwmul.h">;1197 def WMUL : RVPWideningBinary_rr<0b0100, 0b01, "wmul">;1198 def PWMUL_B : RVPWideningBinary_rr<0b0100, 0b10, "pwmul.b">;1199 def PM2WADDU_H : RVPWideningBinary_rr<0b0100, 0b11, "pm2waddu.h">;1200 1201 def PWMACC_H : RVPWideningTernary_rrr<0b0101, 0b00, "pwmacc.h">;1202 def WMACC : RVPWideningTernary_rrr<0b0101, 0b01, "wmacc">;1203 def PM2WADDAU_H : RVPWideningTernary_rrr<0b0101, 0b11, "pm2waddau.h">;1204 1205 def PWMULU_H : RVPWideningBinary_rr<0b0110, 0b00, "pwmulu.h">;1206 def WMULU : RVPWideningBinary_rr<0b0110, 0b01, "wmulu">;1207 def PWMULU_B : RVPWideningBinary_rr<0b0110, 0b10, "pwmulu.b">;1208 1209 def PWMACCU_H : RVPWideningTernary_rrr<0b0111, 0b00, "pwmaccu.h">;1210 def WMACCU : RVPWideningTernary_rrr<0b0111, 0b01, "wmaccu">;1211 1212 def PWSUB_H : RVPWideningBinary_rr<0b1000, 0b00, "pwsub.h">;1213 def WSUB : RVPWideningBinary_rr<0b1000, 0b01, "wsub">;1214 def PWSUB_B : RVPWideningBinary_rr<0b1000, 0b10, "pwsub.b">;1215 def PM2WSUB_H : RVPWideningBinary_rr<0b1000, 0b11, "pm2wsub.h">;1216 1217 def PWSUBA_H : RVPWideningTernary_rrr<0b1001, 0b00, "pwsuba.h">;1218 def WSUBA : RVPWideningTernary_rrr<0b1001, 0b01, "wsuba">;1219 def PWSUBA_B : RVPWideningTernary_rrr<0b1001, 0b10, "pwsuba.b">;1220 def PM2WSUBA_H : RVPWideningTernary_rrr<0b1001, 0b11, "pm2wsuba.h">;1221 1222 def PWSUBU_H : RVPWideningBinary_rr<0b1010, 0b00, "pwsubu.h">;1223 def WSUBU : RVPWideningBinary_rr<0b1010, 0b01, "wsubu">;1224 def PWSUBU_B : RVPWideningBinary_rr<0b1010, 0b10, "pwsubu.b">;1225 def PM2WSUB_HX : RVPWideningBinary_rr<0b1010, 0b11, "pm2wsub.hx">;1226 1227 def PWSUBAU_H : RVPWideningTernary_rrr<0b1011, 0b00, "pwsubau.h">;1228 def WSUBAU : RVPWideningTernary_rrr<0b1011, 0b01, "wsubau">;1229 def PWSUBAU_B : RVPWideningTernary_rrr<0b1011, 0b10, "pwsubau.b">;1230 def PM2WSUBA_HX : RVPWideningTernary_rrr<0b1011, 0b11, "pm2wsuba.hx">;1231 1232 def PWMULSU_H : RVPWideningBinary_rr<0b1100, 0b00, "pwmulsu.h">;1233 def WMULSU : RVPWideningBinary_rr<0b1100, 0b01, "wmulsu">;1234 def PWMULSU_B : RVPWideningBinary_rr<0b1100, 0b10, "pwmulsu.b">;1235 def PM2WADDSU_H : RVPWideningBinary_rr<0b1100, 0b11, "pm2waddsu.h">;1236 1237 def PWMACCSU_H : RVPWideningTernary_rrr<0b1101, 0b00, "pwmaccsu.h">;1238 def WMACCSU : RVPWideningTernary_rrr<0b1101, 0b01, "wmaccsu">;1239 def PM2WADDASU_H : RVPWideningTernary_rrr<0b1101, 0b11, "pm2waddasu.h">;1240 1241 def PMQWACC_H : RVPWideningTernary_rrr<0b1111, 0b00, "pmqwacc.h">;1242 def PMQWACC : RVPWideningTernary_rrr<0b1111, 0b01, "pmqwacc">;1243 def PMQRWACC_H : RVPWideningTernary_rrr<0b1111, 0b10, "pmqrwacc.h">;1244 def PMQRWACC : RVPWideningTernary_rrr<0b1111, 0b11, "pmqrwacc">;1245 1246 def PREDSUM_DHS : RVPNarrowingBinary_rr<0b001, 0b00, "predsum.dhs">;1247 def PREDSUM_DBS : RVPNarrowingBinary_rr<0b001, 0b10, "predsum.dbs">;1248 1249 def PREDSUMU_DHS : RVPNarrowingBinary_rr<0b011, 0b00, "predsumu.dhs">;1250 def PREDSUMU_DBS : RVPNarrowingBinary_rr<0b011, 0b10, "predsumu.dbs">;1251 1252 def PNSRLI_B : RVPNarrowingShiftB_ri<0b000, "pnsrli.b">;1253 def PNSRLI_H : RVPNarrowingShiftH_ri<0b000, "pnsrli.h">;1254 def NSRLI : RVPNarrowingShiftW_ri<0b000, "nsrli">;1255 1256 def PNCLIPIU_B : RVPNarrowingShiftB_ri<0b010, "pnclipiu.b">;1257 def PNCLIPIU_H : RVPNarrowingShiftH_ri<0b010, "pnclipiu.h">;1258 def NCLIPIU : RVPNarrowingShiftW_ri<0b010, "nclipiu">;1259 1260 def PNCLIPRIU_B : RVPNarrowingShiftB_ri<0b011, "pnclipriu.b">;1261 def PNCLIPRIU_H : RVPNarrowingShiftH_ri<0b011, "pnclipriu.h">;1262 def NCLIPRIU : RVPNarrowingShiftW_ri<0b011, "nclipriu">;1263 1264 def PNSRAI_B : RVPNarrowingShiftB_ri<0b100, "pnsrai.b">;1265 def PNSRAI_H : RVPNarrowingShiftH_ri<0b100, "pnsrai.h">;1266 def NSRAI : RVPNarrowingShiftW_ri<0b100, "nsrai">;1267 1268 def PNSARI_B : RVPNarrowingShiftB_ri<0b101, "pnsari.b">;1269 def PNSARI_H : RVPNarrowingShiftH_ri<0b101, "pnsari.h">;1270 def NSARI : RVPNarrowingShiftW_ri<0b101, "nsari">;1271 1272 def PNCLIPI_B : RVPNarrowingShiftB_ri<0b110, "pnclipi.b">;1273 def PNCLIPI_H : RVPNarrowingShiftH_ri<0b110, "pnclipi.h">;1274 def NCLIPI : RVPNarrowingShiftW_ri<0b110, "nclipi">;1275 1276 def PNCLIPRI_B : RVPNarrowingShiftB_ri<0b111, "pnclipri.b">;1277 def PNCLIPRI_H : RVPNarrowingShiftH_ri<0b111, "pnclipri.h">;1278 def NCLIPRI : RVPNarrowingShiftW_ri<0b111, "nclipri">;1279 1280 def PNSRL_BS : RVPNarrowingShift_rr<0b000, 0b00, "pnsrl.bs">;1281 def PNSRL_HS : RVPNarrowingShift_rr<0b000, 0b01, "pnsrl.hs">;1282 def NSRL : RVPNarrowingShift_rr<0b000, 0b11, "nsrl">;1283 1284 def PNCLIPU_BS : RVPNarrowingShift_rr<0b010, 0b00, "pnclipu.bs">;1285 def PNCLIPU_HS : RVPNarrowingShift_rr<0b010, 0b01, "pnclipu.hs">;1286 def NCLIPU : RVPNarrowingShift_rr<0b010, 0b11, "nclipu">;1287 1288 def PNCLIPRU_BS : RVPNarrowingShift_rr<0b011, 0b00, "pnclipru.bs">;1289 def PNCLIPRU_HS : RVPNarrowingShift_rr<0b011, 0b01, "pnclipru.hs">;1290 def NCLIPRU : RVPNarrowingShift_rr<0b011, 0b11, "nclipru">;1291 1292 def PNSRA_BS : RVPNarrowingShift_rr<0b100, 0b00, "pnsra.bs">;1293 def PNSRA_HS : RVPNarrowingShift_rr<0b100, 0b01, "pnsra.hs">;1294 def NSRA : RVPNarrowingShift_rr<0b100, 0b11, "nsra">;1295 1296 def PNSRAR_BS : RVPNarrowingShift_rr<0b101, 0b00, "pnsrar.bs">;1297 def PNSRAR_HS : RVPNarrowingShift_rr<0b101, 0b01, "pnsrar.hs">;1298 def NSRAR : RVPNarrowingShift_rr<0b101, 0b11, "nsrar">;1299 1300 def PNCLIP_BS : RVPNarrowingShift_rr<0b110, 0b00, "pnclip.bs">;1301 def PNCLIP_HS : RVPNarrowingShift_rr<0b110, 0b01, "pnclip.hs">;1302 def NCLIP : RVPNarrowingShift_rr<0b110, 0b11, "nclip">;1303 1304 def PNCLIPR_BS : RVPNarrowingShift_rr<0b111, 0b00, "pnclipr.bs">;1305 def PNCLIPR_HS : RVPNarrowingShift_rr<0b111, 0b01, "pnclipr.hs">;1306 def NCLIPR : RVPNarrowingShift_rr<0b111, 0b11, "nclipr">;1307 1308 def PSLLI_DB : RVPPairShiftB_ri<0b000, "pslli.db">;1309 def PSLLI_DH : RVPPairShiftH_ri<0b000, "pslli.dh">;1310 def PSLLI_DW : RVPPairShiftW_ri<0b000, "pslli.dw">;1311 1312 def PSSLAI_DH : RVPPairShiftH_ri<0b101, "psslai.dh">;1313 def PSSLAI_DW : RVPPairShiftW_ri<0b101, "psslai.dw">;1314 1315 def PSEXT_DH_B : RVPPairUnary_r<0b00, 0b00100, "psext.dh.b">;1316 def PSEXT_DW_B : RVPPairUnary_r<0b01, 0b00100, "psext.dw.b">;1317 1318 def PSEXT_DW_H : RVPPairUnary_r<0b01, 0b00101, "psext.dw.h">;1319 1320 def PSABS_DH : RVPPairUnary_r<0b00, 0b00111, "psabs.dh">;1321 def PSABS_DB : RVPPairUnary_r<0b10, 0b00111, "psabs.db">;1322 1323 def PSLL_DHS : RVPPairShift_rr<0b000, 0b00, "psll.dhs">;1324 def PSLL_DWS : RVPPairShift_rr<0b000, 0b01, "psll.dws">;1325 def PSLL_DBS : RVPPairShift_rr<0b000, 0b10, "psll.dbs">;1326 1327 def PADD_DHS : RVPPairShift_rr<0b001, 0b00, "padd.dhs">;1328 def PADD_DWS : RVPPairShift_rr<0b001, 0b01, "padd.dws">;1329 def PADD_DBS : RVPPairShift_rr<0b001, 0b10, "padd.dbs">;1330 1331 def PSSHA_DHS : RVPPairShift_rr<0b110, 0b00, "pssha.dhs">;1332 def PSSHA_DWS : RVPPairShift_rr<0b110, 0b01, "pssha.dws">;1333 1334 def PSSHAR_DHS : RVPPairShift_rr<0b111, 0b00, "psshar.dhs">;1335 def PSSHAR_DWS : RVPPairShift_rr<0b111, 0b01, "psshar.dws">;1336 1337 def PSRLI_DB : RVPPairShiftB_ri<0b000, "psrli.db", 0b1>;1338 def PSRLI_DH : RVPPairShiftH_ri<0b000, "psrli.dh", 0b1>;1339 def PSRLI_DW : RVPPairShiftW_ri<0b000, "psrli.dw", 0b1>;1340 1341 def PUSATI_DH : RVPPairShiftH_ri<0b010, "pusati.dh", 0b1>;1342 def PUSATI_DW : RVPPairShiftW_ri<0b010, "pusati.dw", 0b1>;1343 1344 def PSRAI_DB : RVPPairShiftB_ri<0b100, "psrai.db", 0b1>;1345 def PSRAI_DH : RVPPairShiftH_ri<0b100, "psrai.dh", 0b1>;1346 def PSRAI_DW : RVPPairShiftW_ri<0b100, "psrai.dw", 0b1>;1347 1348 def PSRARI_DH : RVPPairShiftH_ri<0b101, "psrari.dh", 0b1>;1349 def PSRARI_DW : RVPPairShiftW_ri<0b101, "psrari.dw", 0b1>;1350 1351 def PSATI_DH : RVPPairShiftH_ri<0b110, "psati.dh", 0b1>;1352 def PSATI_DW : RVPPairShiftW_ri<0b110, "psati.dw", 0b1>;1353 1354 def PSRL_DHS : RVPPairShift_rr<0b000, 0b00, "psrl.dhs", 0b1>;1355 def PSRL_DWS : RVPPairShift_rr<0b000, 0b01, "psrl.dws", 0b1>;1356 def PSRL_DBS : RVPPairShift_rr<0b000, 0b10, "psrl.dbs", 0b1>;1357 1358 def PSRA_DHS : RVPPairShift_rr<0b100, 0b00, "psra.dhs", 0b1>;1359 def PSRA_DWS : RVPPairShift_rr<0b100, 0b01, "psra.dws", 0b1>;1360 def PSRA_DBS : RVPPairShift_rr<0b100, 0b10, "psra.dbs", 0b1>;1361 1362 def PADD_DH : RVPPairBinary_rr<0b0000, 0b00, "padd.dh">;1363 def PADD_DW : RVPPairBinary_rr<0b0000, 0b01, "padd.dw">;1364 def PADD_DB : RVPPairBinary_rr<0b0000, 0b10, "padd.db">;1365 def ADDD : RVPPairBinary_rr<0b0000, 0b11, "addd">;1366 1367 def PSADD_DH : RVPPairBinary_rr<0b0010, 0b00, "psadd.dh">;1368 def PSADD_DW : RVPPairBinary_rr<0b0010, 0b01, "psadd.dw">;1369 def PSADD_DB : RVPPairBinary_rr<0b0010, 0b10, "psadd.db">;1370 1371 def PAADD_DH : RVPPairBinary_rr<0b0011, 0b00, "paadd.dh">;1372 def PAADD_DW : RVPPairBinary_rr<0b0011, 0b01, "paadd.dw">;1373 def PAADD_DB : RVPPairBinary_rr<0b0011, 0b10, "paadd.db">;1374 1375 def PSADDU_DH : RVPPairBinary_rr<0b0110, 0b00, "psaddu.dh">;1376 def PSADDU_DW : RVPPairBinary_rr<0b0110, 0b01, "psaddu.dw">;1377 def PSADDU_DB : RVPPairBinary_rr<0b0110, 0b10, "psaddu.db">;1378 1379 def PAADDU_DH : RVPPairBinary_rr<0b0111, 0b00, "paaddu.dh">;1380 def PAADDU_DW : RVPPairBinary_rr<0b0111, 0b01, "paaddu.dw">;1381 def PAADDU_DB : RVPPairBinary_rr<0b0111, 0b10, "paaddu.db">;1382 1383 def PSUB_DH : RVPPairBinary_rr<0b1000, 0b00, "psub.dh">;1384 def PSUB_DW : RVPPairBinary_rr<0b1000, 0b01, "psub.dw">;1385 def PSUB_DB : RVPPairBinary_rr<0b1000, 0b10, "psub.db">;1386 def SUBD : RVPPairBinary_rr<0b1000, 0b11, "subd">;1387 1388 def PDIF_DH : RVPPairBinary_rr<0b1001, 0b00, "pdif.dh">;1389 def PDIF_DB : RVPPairBinary_rr<0b1001, 0b10, "pdif.db">;1390 1391 def PSSUB_DH : RVPPairBinary_rr<0b1010, 0b00, "pssub.dh">;1392 def PSSUB_DW : RVPPairBinary_rr<0b1010, 0b01, "pssub.dw">;1393 def PSSUB_DB : RVPPairBinary_rr<0b1010, 0b10, "pssub.db">;1394 1395 def PASUB_DH : RVPPairBinary_rr<0b1011, 0b00, "pasub.dh">;1396 def PASUB_DW : RVPPairBinary_rr<0b1011, 0b01, "pasub.dw">;1397 def PASUB_DB : RVPPairBinary_rr<0b1011, 0b10, "pasub.db">;1398 1399 def PDIFU_DH : RVPPairBinary_rr<0b1101, 0b00, "pdifu.dh">;1400 def PDIFU_DB : RVPPairBinary_rr<0b1101, 0b10, "pdifu.db">;1401 1402 def PSSUBU_DH : RVPPairBinary_rr<0b1110, 0b00, "pssubu.dh">;1403 def PSSUBU_DW : RVPPairBinary_rr<0b1110, 0b01, "pssubu.dw">;1404 def PSSUBU_DB : RVPPairBinary_rr<0b1110, 0b10, "pssubu.db">;1405 1406 def PASUBU_DH : RVPPairBinary_rr<0b1111, 0b00, "pasubu.dh">;1407 def PASUBU_DW : RVPPairBinary_rr<0b1111, 0b01, "pasubu.dw">;1408 def PASUBU_DB : RVPPairBinary_rr<0b1111, 0b10, "pasubu.db">;1409 1410 def PSH1ADD_DH : RVPPairBinaryShift_rr<0b010, 0b00, "psh1add.dh">;1411 def PSH1ADD_DW : RVPPairBinaryShift_rr<0b010, 0b01, "psh1add.dw">;1412 1413 def PSSH1SADD_DH : RVPPairBinaryShift_rr<0b011, 0b00, "pssh1sadd.dh">;1414 def PSSH1SADD_DW : RVPPairBinaryShift_rr<0b011, 0b01, "pssh1sadd.dw">;1415 1416 def PPACK_DH : RVPPairBinaryPack_rr<0b000, 0b00, "ppack.dh">;1417 def PPACK_DW : RVPPairBinaryPack_rr<0b000, 0b01, "ppack.dw">;1418 1419 def PPACKBT_DH : RVPPairBinaryPack_rr<0b001, 0b00, "ppackbt.dh">;1420 def PPACKBT_DW : RVPPairBinaryPack_rr<0b001, 0b01, "ppackbt.dw">;1421 1422 def PPACKTB_DH : RVPPairBinaryPack_rr<0b010, 0b00, "ppacktb.dh">;1423 def PPACKTB_DW : RVPPairBinaryPack_rr<0b010, 0b01, "ppacktb.dw">;1424 1425 def PPACKT_DH : RVPPairBinaryPack_rr<0b011, 0b00, "ppackt.dh">;1426 def PPACKT_DW : RVPPairBinaryPack_rr<0b011, 0b01, "ppackt.dw">;1427 1428 def PAS_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b00, "pas.dhx">;1429 def PSA_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b10, "psa.dhx">;1430 1431 def PSAS_DHX : RVPPairBinaryExchanged_rr<0b0010, 0b00, "psas.dhx">;1432 def PSSA_DHX : RVPPairBinaryExchanged_rr<0b0010, 0b10, "pssa.dhx">;1433 1434 def PAAX_DHX : RVPPairBinaryExchanged_rr<0b0011, 0b00, "paax.dhx">;1435 def PASA_DHX : RVPPairBinaryExchanged_rr<0b0011, 0b10, "pasa.dhx">;1436 1437 def PMSEQ_DH : RVPPairBinaryExchanged_rr<0b1000, 0b00, "pmseq.dh">;1438 def PMSEQ_DW : RVPPairBinaryExchanged_rr<0b1000, 0b01, "pmseq.dw">;1439 def PMSEQ_DB : RVPPairBinaryExchanged_rr<0b1000, 0b10, "pmseq.db">;1440 1441 def PMSLT_DH : RVPPairBinaryExchanged_rr<0b1010, 0b00, "pmslt.dh">;1442 def PMSLT_DW : RVPPairBinaryExchanged_rr<0b1010, 0b01, "pmslt.dw">;1443 def PMSLT_DB : RVPPairBinaryExchanged_rr<0b1010, 0b10, "pmslt.db">;1444 1445 def PMSLTU_DH : RVPPairBinaryExchanged_rr<0b1011, 0b00, "pmsltu.dh">;1446 def PMSLTU_DW : RVPPairBinaryExchanged_rr<0b1011, 0b01, "pmsltu.dw">;1447 def PMSLTU_DB : RVPPairBinaryExchanged_rr<0b1011, 0b10, "pmsltu.db">;1448 1449 def PMIN_DH : RVPPairBinaryExchanged_rr<0b1100, 0b00, "pmin.dh">;1450 def PMIN_DW : RVPPairBinaryExchanged_rr<0b1100, 0b01, "pmin.dw">;1451 def PMIN_DB : RVPPairBinaryExchanged_rr<0b1100, 0b10, "pmin.db">;1452 1453 def PMINU_DH : RVPPairBinaryExchanged_rr<0b1101, 0b00, "pminu.dh">;1454 def PMINU_DW : RVPPairBinaryExchanged_rr<0b1101, 0b01, "pminu.dw">;1455 def PMINU_DB : RVPPairBinaryExchanged_rr<0b1101, 0b10, "pminu.db">;1456 1457 def PMAX_DH : RVPPairBinaryExchanged_rr<0b1110, 0b00, "pmax.dh">;1458 def PMAX_DW : RVPPairBinaryExchanged_rr<0b1110, 0b01, "pmax.dw">;1459 def PMAX_DB : RVPPairBinaryExchanged_rr<0b1110, 0b10, "pmax.db">;1460 1461 def PMAXU_DH : RVPPairBinaryExchanged_rr<0b1111, 0b00, "pmaxu.dh">;1462 def PMAXU_DW : RVPPairBinaryExchanged_rr<0b1111, 0b01, "pmaxu.dw">;1463 def PMAXU_DB : RVPPairBinaryExchanged_rr<0b1111, 0b10, "pmaxu.db">;1464} // Predicates = [HasStdExtP, IsRV32]1465 1466 1467//===----------------------------------------------------------------------===//1468// Codegen patterns1469//===----------------------------------------------------------------------===//1470 1471def riscv_absw : RVSDNode<"ABSW", SDT_RISCVIntUnaryOpW>;1472 1473def SDT_RISCVPASUB : SDTypeProfile<1, 2, [SDTCisVec<0>,1474 SDTCisInt<0>,1475 SDTCisSameAs<0, 1>,1476 SDTCisSameAs<0, 2>]>;1477def riscv_pasub : RVSDNode<"PASUB", SDT_RISCVPASUB>;1478def riscv_pasubu : RVSDNode<"PASUBU", SDT_RISCVPASUB>;1479 1480let Predicates = [HasStdExtP] in {1481 def : PatGpr<abs, ABS>;1482 1483 // Basic 8-bit arithmetic patterns1484 def: Pat<(XLenVecI8VT (add GPR:$rs1, GPR:$rs2)), (PADD_B GPR:$rs1, GPR:$rs2)>;1485 def: Pat<(XLenVecI8VT (sub GPR:$rs1, GPR:$rs2)), (PSUB_B GPR:$rs1, GPR:$rs2)>;1486 1487 // Basic 16-bit arithmetic patterns1488 def: Pat<(XLenVecI16VT (add GPR:$rs1, GPR:$rs2)), (PADD_H GPR:$rs1, GPR:$rs2)>;1489 def: Pat<(XLenVecI16VT (sub GPR:$rs1, GPR:$rs2)), (PSUB_H GPR:$rs1, GPR:$rs2)>;1490 1491 // 8-bit saturating add/sub patterns1492 def: Pat<(XLenVecI8VT (saddsat GPR:$rs1, GPR:$rs2)), (PSADD_B GPR:$rs1, GPR:$rs2)>;1493 def: Pat<(XLenVecI8VT (uaddsat GPR:$rs1, GPR:$rs2)), (PSADDU_B GPR:$rs1, GPR:$rs2)>;1494 def: Pat<(XLenVecI8VT (ssubsat GPR:$rs1, GPR:$rs2)), (PSSUB_B GPR:$rs1, GPR:$rs2)>;1495 def: Pat<(XLenVecI8VT (usubsat GPR:$rs1, GPR:$rs2)), (PSSUBU_B GPR:$rs1, GPR:$rs2)>;1496 1497 // 16-bit saturating add/sub patterns1498 def: Pat<(XLenVecI16VT (saddsat GPR:$rs1, GPR:$rs2)), (PSADD_H GPR:$rs1, GPR:$rs2)>;1499 def: Pat<(XLenVecI16VT (uaddsat GPR:$rs1, GPR:$rs2)), (PSADDU_H GPR:$rs1, GPR:$rs2)>;1500 def: Pat<(XLenVecI16VT (ssubsat GPR:$rs1, GPR:$rs2)), (PSSUB_H GPR:$rs1, GPR:$rs2)>;1501 def: Pat<(XLenVecI16VT (usubsat GPR:$rs1, GPR:$rs2)), (PSSUBU_H GPR:$rs1, GPR:$rs2)>;1502 1503 // 8-bit averaging patterns1504 def: Pat<(XLenVecI8VT (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_B GPR:$rs1, GPR:$rs2)>;1505 def: Pat<(XLenVecI8VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_B GPR:$rs1, GPR:$rs2)>;1506 def: Pat<(XLenVecI8VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_B GPR:$rs1, GPR:$rs2)>;1507 def: Pat<(XLenVecI8VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_B GPR:$rs1, GPR:$rs2)>;1508 1509 // 16-bit averaging patterns1510 def: Pat<(XLenVecI16VT (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_H GPR:$rs1, GPR:$rs2)>;1511 def: Pat<(XLenVecI16VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_H GPR:$rs1, GPR:$rs2)>;1512 def: Pat<(XLenVecI16VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_H GPR:$rs1, GPR:$rs2)>;1513 def: Pat<(XLenVecI16VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>;1514 1515 // 8-bit absolute difference patterns1516 def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PDIF_B GPR:$rs1, GPR:$rs2)>;1517 def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PDIFU_B GPR:$rs1, GPR:$rs2)>;1518 1519 // 16-bit absolute difference patterns1520 def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PDIF_H GPR:$rs1, GPR:$rs2)>;1521 def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PDIFU_H GPR:$rs1, GPR:$rs2)>;1522 1523 // 8-bit logical shift left patterns1524 def: Pat<(XLenVecI8VT (shl GPR:$rs1, (XLenVecI8VT (splat_vector uimm3:$shamt)))),1525 (PSLLI_B GPR:$rs1, uimm3:$shamt)>;1526 1527 // 16-bit logical shift left patterns1528 def: Pat<(XLenVecI16VT (shl GPR:$rs1, (XLenVecI16VT (splat_vector uimm4:$shamt)))),1529 (PSLLI_H GPR:$rs1, uimm4:$shamt)>;1530 1531 // 16-bit signed saturation shift left patterns1532 def: Pat<(XLenVecI16VT (sshlsat GPR:$rs1, (XLenVecI16VT (splat_vector uimm4:$shamt)))),1533 (PSSLAI_H GPR:$rs1, uimm4:$shamt)>;1534 1535 // 8-bit PLI SD node pattern1536 def: Pat<(XLenVecI8VT (splat_vector simm8_unsigned:$imm8)), (PLI_B simm8_unsigned:$imm8)>;1537 // 16-bit PLI SD node pattern1538 def: Pat<(XLenVecI16VT (splat_vector simm10:$imm10)), (PLI_H simm10:$imm10)>;1539 1540 // // splat pattern1541 def: Pat<(XLenVecI8VT (splat_vector (XLenVT GPR:$rs2))), (PADD_BS (XLenVT X0), GPR:$rs2)>;1542 def: Pat<(XLenVecI16VT (splat_vector (XLenVT GPR:$rs2))), (PADD_HS (XLenVT X0), GPR:$rs2)>;1543} // Predicates = [HasStdExtP]1544 1545let Predicates = [HasStdExtP, IsRV32] in {1546 // Load/Store patterns1547 def : StPat<store, SW, GPR, v4i8>;1548 def : StPat<store, SW, GPR, v2i16>;1549 def : LdPat<load, LW, v4i8>;1550 def : LdPat<load, LW, v2i16>;1551 1552 // Build vector patterns1553 def : Pat<(v2i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))),1554 (PACK GPR:$a, GPR:$b)>;1555} // Predicates = [HasStdExtP, IsRV32]1556 1557let Predicates = [HasStdExtP, IsRV64] in {1558 def : PatGpr<riscv_absw, ABSW>;1559 1560 // 32-bit PLI SD node pattern1561 def: Pat<(v2i32 (splat_vector simm10:$imm10)), (PLI_W simm10:$imm10)>;1562 1563 // Basic 32-bit arithmetic patterns1564 def: Pat<(v2i32 (add GPR:$rs1, GPR:$rs2)), (PADD_W GPR:$rs1, GPR:$rs2)>;1565 def: Pat<(v2i32 (sub GPR:$rs1, GPR:$rs2)), (PSUB_W GPR:$rs1, GPR:$rs2)>;1566 1567 // 32-bit saturating add/sub patterns1568 def: Pat<(v2i32 (saddsat GPR:$rs1, GPR:$rs2)), (PSADD_W GPR:$rs1, GPR:$rs2)>;1569 def: Pat<(v2i32 (uaddsat GPR:$rs1, GPR:$rs2)), (PSADDU_W GPR:$rs1, GPR:$rs2)>;1570 def: Pat<(v2i32 (ssubsat GPR:$rs1, GPR:$rs2)), (PSSUB_W GPR:$rs1, GPR:$rs2)>;1571 def: Pat<(v2i32 (usubsat GPR:$rs1, GPR:$rs2)), (PSSUBU_W GPR:$rs1, GPR:$rs2)>;1572 1573 // 32-bit averaging patterns1574 def: Pat<(v2i32 (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_W GPR:$rs1, GPR:$rs2)>;1575 def: Pat<(v2i32 (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_W GPR:$rs1, GPR:$rs2)>;1576 1577 // 32-bit averaging-sub patterns1578 def: Pat<(v2i32 (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_W GPR:$rs1, GPR:$rs2)>;1579 def: Pat<(v2i32 (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_W GPR:$rs1, GPR:$rs2)>;1580 1581 // splat pattern1582 def: Pat<(v2i32 (splat_vector (XLenVT GPR:$rs2))), (PADD_WS (XLenVT X0), GPR:$rs2)>;1583 1584 // 32-bit logical shift left patterns1585 def: Pat<(v2i32 (shl GPR:$rs1, (v2i32 (splat_vector uimm5:$shamt)))),1586 (PSLLI_W GPR:$rs1, uimm5:$shamt)>;1587 1588 // 32-bit signed saturation shift left patterns1589 def: Pat<(v2i32 (sshlsat GPR:$rs1, (v2i32 (splat_vector uimm5:$shamt)))),1590 (PSSLAI_W GPR:$rs1, uimm5:$shamt)>;1591 1592 // Load/Store patterns1593 def : StPat<store, SD, GPR, v8i8>;1594 def : StPat<store, SD, GPR, v4i16>;1595 def : StPat<store, SD, GPR, v2i32>;1596 def : LdPat<load, LD, v8i8>;1597 def : LdPat<load, LD, v4i16>;1598 def : LdPat<load, LD, v2i32>;1599 1600 // Build vector patterns1601 def : Pat<(v8i8 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b),1602 (XLenVT GPR:$c), (XLenVT GPR:$d),1603 (XLenVT undef), (XLenVT undef),1604 (XLenVT undef), (XLenVT undef))),1605 (PPACK_W (PPACK_H GPR:$a, GPR:$b), (PPACK_H GPR:$c, GPR:$d))>;1606 1607 def : Pat<(v8i8 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b),1608 (XLenVT GPR:$c), (XLenVT GPR:$d),1609 (XLenVT GPR:$e), (XLenVT GPR:$f),1610 (XLenVT GPR:$g), (XLenVT GPR:$h))),1611 (PACK(PPACK_W (PPACK_H GPR:$a, GPR:$b), (PPACK_H GPR:$c, GPR:$d)),1612 (PPACK_W (PPACK_H GPR:$e, GPR:$f), (PPACK_H GPR:$g, GPR:$h)))>;1613 1614 def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b),1615 (XLenVT undef), (XLenVT undef))),1616 (PPACK_W GPR:$a, GPR:$b)>;1617 1618 def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b),1619 (XLenVT GPR:$c), (XLenVT GPR:$d))),1620 (PACK (PPACK_W GPR:$a, GPR:$b), (PPACK_W GPR:$c, GPR:$d))>;1621 1622 def : Pat<(v2i32 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))),1623 (PACK GPR:$a, GPR:$b)>;1624} // Predicates = [HasStdExtP, IsRV64]1625