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1//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Q',10// Quad-Precision Floating-Point instruction set extension.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Operand and SDNode transformation definitions.16//===----------------------------------------------------------------------===//17 18def QExt : ExtInfo<"", "", [HasStdExtQ], f128, FPR128, FPR32, FPR64, ?>;19 20defvar QExts = [QExt];21defvar QExtsRV64 = [QExt];22 23//===----------------------------------------------------------------------===//24// Instructions25//===----------------------------------------------------------------------===//26 27let Predicates = [HasStdExtQ] in {28 def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;29 30 // Operands for stores are in the order srcreg, base, offset rather than31 // reflecting the order these fields are specified in the instruction32 // encoding.33 def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;34} // Predicates = [HasStdExtQ]35 36foreach Ext = QExts in {37 let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {38 defm FMADD_Q : FPFMA_rrr_frm_m<OPC_MADD, 0b11, "fmadd.q", Ext>;39 defm FMSUB_Q : FPFMA_rrr_frm_m<OPC_MSUB, 0b11, "fmsub.q", Ext>;40 defm FNMSUB_Q : FPFMA_rrr_frm_m<OPC_NMSUB, 0b11, "fnmsub.q", Ext>;41 defm FNMADD_Q : FPFMA_rrr_frm_m<OPC_NMADD, 0b11, "fnmadd.q", Ext>;42 }43 44 let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {45 defm FADD_Q : FPALU_rr_frm_m<0b0000011, "fadd.q", Ext>;46 defm FSUB_Q : FPALU_rr_frm_m<0b0000111, "fsub.q", Ext>;47 }48 49 let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in 50 defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;51 52 let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in 53 defm FDIV_Q : FPALU_rr_frm_m<0b0001111, "fdiv.q", Ext>;54 55 defm FSQRT_Q : FPUnaryOp_r_frm_m<0b0101111, 0b00000, Ext, Ext.PrimaryTy,56 Ext.PrimaryTy, "fsqrt.q">,57 Sched<[WriteFSqrt128, ReadFSqrt128]>;58 59 let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],60 mayRaiseFPException = 0 in {61 defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;62 defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;63 defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;64 }65 66 let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {67 defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;68 defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;69 }70 71 defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b0100000, 0b00011, Ext, Ext.F32Ty,72 Ext.PrimaryTy, "fcvt.s.q">,73 Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;74 75 defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00000, Ext,76 Ext.PrimaryTy, Ext.F32Ty, 77 "fcvt.q.s">,78 Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;79 80 defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b0100001, 0b00011, Ext, Ext.F64Ty,81 Ext.PrimaryTy, "fcvt.d.q">,82 Sched<[WriteFCvtF128ToF64, ReadFCvtF128ToF64]>;83 84 defm FCVT_Q_D : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b00001, Ext,85 Ext.PrimaryTy, Ext.F64Ty, 86 "fcvt.q.d">,87 Sched<[WriteFCvtF64ToF128, ReadFCvtF64ToF128]>;88 89 let SchedRW = [WriteFCmp128, ReadFCmp128, ReadFCmp128] in {90 defm FEQ_Q : FPCmp_rr_m<0b1010011, 0b010, "feq.q", Ext, Commutable = 1>;91 defm FLT_Q : FPCmp_rr_m<0b1010011, 0b001, "flt.q", Ext>;92 defm FLE_Q : FPCmp_rr_m<0b1010011, 0b000, "fle.q", Ext>;93 }94 95 let mayRaiseFPException = 0 in 96 defm FCLASS_Q : FPUnaryOp_r_m<0b1110011, 0b00000, 0b001, Ext, GPR,97 Ext.PrimaryTy, "fclass.q">,98 Sched<[WriteFClass128, ReadFClass128]>;99 100 let IsSignExtendingOpW = 1 in 101 defm FCVT_W_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00000, Ext, GPR,102 Ext.PrimaryTy, "fcvt.w.q">,103 Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;104 105 let IsSignExtendingOpW = 1 in 106 defm FCVT_WU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00001, Ext, GPR,107 Ext.PrimaryTy, "fcvt.wu.q">,108 Sched<[WriteFCvtF128ToI32, ReadFCvtF128ToI32]>;109 110 let mayRaiseFPException = 0 in 111 defm FCVT_Q_W : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00000, Ext,112 Ext.PrimaryTy, GPR, "fcvt.q.w">,113 Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;114 115 let mayRaiseFPException = 0 in 116 defm FCVT_Q_WU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00001, Ext,117 Ext.PrimaryTy, GPR, "fcvt.q.wu">,118 Sched<[WriteFCvtI32ToF128, ReadFCvtI32ToF128]>;119} // foreach Ext = QExts120 121foreach Ext = QExtsRV64 in {122 defm FCVT_L_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00010, Ext, GPR, 123 Ext.PrimaryTy, "fcvt.l.q", [IsRV64]>,124 Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>;125 126 defm FCVT_LU_Q : FPUnaryOp_r_frm_m<0b1100011, 0b00011, Ext, GPR,127 Ext.PrimaryTy, "fcvt.lu.q", [IsRV64]>,128 Sched<[WriteFCvtF128ToI64, ReadFCvtF128ToI64]>;129 130 let mayRaiseFPException = 0 in 131 defm FCVT_Q_L : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00010, Ext,132 Ext.PrimaryTy, GPR, "fcvt.q.l",133 [IsRV64]>,134 Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>;135 136 let mayRaiseFPException = 0 in 137 defm FCVT_Q_LU : FPUnaryOp_r_frmlegacy_m<0b1101011, 0b00011, Ext,138 Ext.PrimaryTy, GPR, "fcvt.q.lu",139 [IsRV64]>,140 Sched<[WriteFCvtI64ToF128, ReadFCvtI64ToF128]>;141} // foreach Ext = QExtsRV64142 143//===----------------------------------------------------------------------===//144// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)145//===----------------------------------------------------------------------===//146 147let Predicates = [HasStdExtQ] in {148 def : InstAlias<"flq $rd, (${rs1})", (FLQ FPR128:$rd, GPR:$rs1, 0), 0>;149 def : InstAlias<"fsq $rs2, (${rs1})", (FSQ FPR128:$rs2, GPR:$rs1, 0), 0>;150 151 def : InstAlias<"fmv.q $rd, $rs", (FSGNJ_Q FPR128:$rd, FPR128:$rs,152 FPR128:$rs)>;153 def : InstAlias<"fabs.q $rd, $rs", (FSGNJX_Q FPR128:$rd, FPR128:$rs,154 FPR128:$rs)>;155 def : InstAlias<"fneg.q $rd, $rs", (FSGNJN_Q FPR128:$rd, FPR128:$rs,156 FPR128:$rs)>;157 158 // fgt.q/fge.q are recognised by the GNU assembler but the canonical159 // flt.q/fle.q forms will always be printed. Therefore, set a zero weight.160 def : InstAlias<"fgt.q $rd, $rs, $rt",161 (FLT_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;162 def : InstAlias<"fge.q $rd, $rs, $rt",163 (FLE_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;164 165 def PseudoFLQ : PseudoFloatLoad<"flq", FPR128>;166 def PseudoFSQ : PseudoStore<"fsq", FPR128>;167} // Predicates = [HasStdExtQ]168