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1//===-- RISCVInstrInfoSFB.td - Pseudos for SFB -------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the pseudos for SFB (Short Forward Branch).10//11//===----------------------------------------------------------------------===//12 13let Predicates = [HasShortForwardBranchIALU], isSelect = 1,14 Constraints = "$dst = $falsev", isCommutable = 1, Size = 8 in {15// This instruction moves $truev to $dst when the condition is true. It will16// be expanded to control flow in RISCVExpandPseudoInsts.17def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst),18 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,19 GPR:$falsev, GPR:$truev),20 [(set GPR:$dst,21 (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),22 GPR:$rhs, cond,23 (XLenVT GPR:$truev),24 GPR:$falsev))]>,25 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,26 ReadSFBALU, ReadSFBALU]>;27}28 29// This should always expand to a branch+c.mv so the size is 6 or 4 if the30// branch is compressible.31let Predicates = [HasConditionalMoveFusion, NoShortForwardBranch],32 Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in {33// This instruction moves $truev to $dst when the condition is true. It will34// be expanded to control flow in RISCVExpandPseudoInsts.35// We use GPRNoX0 because c.mv cannot encode X0.36def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst),37 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,38 GPRNoX0:$falsev, GPRNoX0:$truev),39 [(set GPRNoX0:$dst,40 (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),41 (XLenVT GPR:$rhs),42 cond, (XLenVT GPRNoX0:$truev),43 (XLenVT GPRNoX0:$falsev)))]>,44 Sched<[]>;45}46 47class SFBALU_rr48 : Pseudo<(outs GPR:$dst),49 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,50 GPR:$rs2), []>,51 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU,52 ReadSFBALU]> {53 let hasSideEffects = 0;54 let mayLoad = 0;55 let mayStore = 0;56 let Size = 8;57 let Constraints = "$dst = $falsev";58}59 60class SFBALU_ri61 : Pseudo<(outs GPR:$dst),62 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,63 simm12_lo:$imm), []>,64 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]> {65 let hasSideEffects = 0;66 let mayLoad = 0;67 let mayStore = 0;68 let Size = 8;69 let Constraints = "$dst = $falsev";70}71 72class SFBLUI73 : Pseudo<(outs GPR:$dst),74 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev,75 uimm20_lui:$imm), []> {76 let hasSideEffects = 0;77 let mayLoad = 0;78 let mayStore = 0;79 let Size = 8;80 let Constraints = "$dst = $falsev";81}82 83class SFBShift_ri84 : Pseudo<(outs GPR:$dst),85 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,86 uimmlog2xlen:$imm), []>,87 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]> {88 let hasSideEffects = 0;89 let mayLoad = 0;90 let mayStore = 0;91 let Size = 8;92 let Constraints = "$dst = $falsev";93}94 95class SFBShiftW_ri96 : Pseudo<(outs GPR:$dst),97 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,98 uimm5:$imm), []>,99 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]> {100 let hasSideEffects = 0;101 let mayLoad = 0;102 let mayStore = 0;103 let Size = 8;104 let Constraints = "$dst = $falsev";105}106 107// Conditional binops, that updates update $dst to (op rs1, rs2) when condition108// is true. Returns $falsev otherwise. Selected by optimizeSelect.109// TODO: Can we use DefaultOperands on the regular binop to accomplish this more110// like how ARM does predication?111let Predicates = [HasShortForwardBranchIALU] in {112def PseudoCCADD : SFBALU_rr;113def PseudoCCSUB : SFBALU_rr;114def PseudoCCSLL : SFBALU_rr;115def PseudoCCSRL : SFBALU_rr;116def PseudoCCSRA : SFBALU_rr;117def PseudoCCAND : SFBALU_rr;118def PseudoCCOR : SFBALU_rr;119def PseudoCCXOR : SFBALU_rr;120 121def PseudoCCADDI : SFBALU_ri;122def PseudoCCANDI : SFBALU_ri;123def PseudoCCORI : SFBALU_ri;124def PseudoCCXORI : SFBALU_ri;125 126def PseudoCCLUI : SFBLUI;127 128def PseudoCCSLLI : SFBShift_ri;129def PseudoCCSRLI : SFBShift_ri;130def PseudoCCSRAI : SFBShift_ri;131 132// RV64I instructions133def PseudoCCADDW : SFBALU_rr;134def PseudoCCSUBW : SFBALU_rr;135def PseudoCCSLLW : SFBALU_rr;136def PseudoCCSRLW : SFBALU_rr;137def PseudoCCSRAW : SFBALU_rr;138 139def PseudoCCADDIW : SFBALU_ri;140 141def PseudoCCSLLIW : SFBShiftW_ri;142def PseudoCCSRLIW : SFBShiftW_ri;143def PseudoCCSRAIW : SFBShiftW_ri;144 145// Zbb/Zbkb instructions146def PseudoCCANDN : SFBALU_rr;147def PseudoCCORN : SFBALU_rr;148def PseudoCCXNOR : SFBALU_rr;149}150 151let Predicates = [HasShortForwardBranchIALU] in152def : Pat<(XLenVT (abs GPR:$rs1)),153 (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2,154 (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>;155let Predicates = [HasShortForwardBranchIALU, IsRV64] in156def : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32),157 (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2,158 (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;159 160let Predicates = [HasShortForwardBranchIMinMax] in {161def PseudoCCMAX : SFBALU_rr;162def PseudoCCMIN : SFBALU_rr;163def PseudoCCMAXU : SFBALU_rr;164def PseudoCCMINU : SFBALU_rr;165}166 167let Predicates = [HasShortForwardBranchIMul] in168def PseudoCCMUL : SFBALU_rr;169