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1//===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// This file contains the required infrastructure to support code generation10/// for the standard 'V' (Vector) extension, version 1.0.11///12/// This file is included from RISCVInstrInfoV.td13///14/// Overview of our vector instruction pseudos. Many of the instructions15/// have behavior which depends on the value of VTYPE. Several core aspects of16/// the compiler - e.g. register allocation - depend on fields in this17/// configuration register. The details of which fields matter differ by the18/// specific instruction, but the common dimensions are:19///20/// LMUL/EMUL - Most instructions can write to differently sized register groups21/// depending on LMUL.22///23/// Masked vs Unmasked - Many instructions which allow a mask disallow register24/// overlap. As a result, masked vs unmasked require different register25/// allocation constraints.26///27/// Policy - For each of mask and tail policy, there are three options:28/// * "Undisturbed" - As defined in the specification, required to preserve the29/// exact bit pattern of inactive lanes.30/// * "Agnostic" - As defined in the specification, required to either preserve31/// the exact bit pattern of inactive lanes, or produce the bit pattern -1 for32/// those lanes. Note that each lane can make this choice independently.33/// Instructions which produce masks (and only those instructions) also have the34/// option of producing a result as-if VL had been VLMAX.35/// * "Undefined" - The bit pattern of the inactive lanes is unspecified, and36/// can be changed without impacting the semantics of the program. Note that37/// this concept does not exist in the specification, and requires source38/// knowledge to be preserved.39///40/// SEW - Some instructions have semantics which depend on SEW. This is41/// relatively rare, and mostly impacts scheduling and cost estimation.42///43/// We have two techniques we use to represent the impact of these fields:44/// * For fields which don't impact register classes, we largely use45/// dummy operands on the pseudo instructions which convey information46/// about the value of VTYPE.47/// * For fields which do impact register classes (and a few bits of48/// legacy - see policy discussion below), we define a family of pseudo49/// instructions for each actual instruction. Said differently, we encode50/// each of the preceding fields which are relevant for a given instruction51/// in the opcode space.52///53/// Currently, the policy is represented via the following intrinsic families:54/// * _MASK - Can represent all three policy states for both tail and mask. If55/// passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined".56/// Otherwise, policy operand and tablegen flags drive the interpretation.57/// (If policy operand is not present - there are a couple, though we're58/// rapidly removing them - a non-undefined policy defaults to "tail59/// agnostic", and "mask undisturbed". Since this is the only variant with60/// a mask, all other variants are "mask undefined".61/// * Unsuffixed w/ both passthrough and policy operand. Can represent all62/// three policy states. If passthrough is IMPLICIT_DEF (or NoReg), then63/// represents "undefined". Otherwise, policy operand and tablegen flags64/// drive the interpretation.65/// * Unsuffixed w/o passthrough or policy operand -- Does not have a66/// passthrough operand, and thus represents the "undefined" state. Note67/// that terminology in code frequently refers to these as "TA" which is68/// confusing. We're in the process of migrating away from this69/// representation.70///71//===----------------------------------------------------------------------===//72 73// VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign74// extended from the vector element size.75def riscv_vmv_x_s : RVSDNode<"VMV_X_S",76 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,77 SDTCisInt<1>]>>;78 79// Read VLENB CSR80def riscv_read_vlenb : RVSDNode<"READ_VLENB",81 SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;82 83// Operand that is allowed to be a register other than X0, a 5 bit unsigned84// immediate, or -1. -1 means VLMAX. This allows us to pick between VSETIVLI and85// VSETVLI opcodes using the same pseudo instructions.86def AVL : RegisterOperand<GPRNoX0> {87 let OperandNamespace = "RISCVOp";88 let OperandType = "OPERAND_AVL";89}90 91def vec_policy : RISCVOp {92 let OperandType = "OPERAND_VEC_POLICY";93}94 95def sew : RISCVOp {96 let OperandType = "OPERAND_SEW";97}98 99// SEW for mask only instructions like vmand and vmsbf. Should always be 0.100def sew_mask : RISCVOp {101 let OperandType = "OPERAND_SEW_MASK";102}103 104def vec_rm : RISCVOp {105 let OperandType = "OPERAND_VEC_RM";106}107 108// X0 has special meaning for vsetvl/vsetvli.109// rd | rs1 | AVL value | Effect on vl110//--------------------------------------------------------------111// !X0 | X0 | VLMAX | Set vl to VLMAX112// X0 | X0 | Value in vl | Keep current vl, just change vtype.113def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;114// FIXME: This is labelled as handling 's32', however the ComplexPattern it115// refers to handles both i32 and i64 based on the HwMode. Currently this LLT116// parameter appears to be ignored so this pattern works for both, however we117// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead118// here.119def GIVLOp : GIComplexOperandMatcher<s32, "renderVLOp">,120 GIComplexPatternEquiv<VLOp>;121 122def DecImm : SDNodeXForm<imm, [{123 return CurDAG->getSignedTargetConstant(N->getSExtValue() - 1, SDLoc(N),124 N->getValueType(0));125}]>;126 127defvar TAIL_AGNOSTIC = 1;128defvar TU_MU = 0;129defvar TA_MU = 1;130defvar TA_MA = 3;131 132//===----------------------------------------------------------------------===//133// Utilities.134//===----------------------------------------------------------------------===//135 136class PseudoToVInst<string PseudoInst> {137 defvar AffixSubsts = [["Pseudo", ""],138 ["_E64", ""],139 ["_E32", ""],140 ["_E16", ""],141 ["_E8", ""],142 ["FPR64", "F"],143 ["FPR32", "F"],144 ["FPR16", "F"],145 ["_TIED", ""],146 ["_MASK", ""],147 ["_B64", ""],148 ["_B32", ""],149 ["_B16", ""],150 ["_B8", ""],151 ["_B4", ""],152 ["_B2", ""],153 ["_B1", ""],154 ["_MF8", ""],155 ["_MF4", ""],156 ["_MF2", ""],157 ["_M1", ""],158 ["_M2", ""],159 ["_M4", ""],160 ["_M8", ""],161 ["_SE", ""],162 ["_RM", ""],163 ["_ALT", ""]164 ];165 string VInst = !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst,166 !subst(AffixSubst[0], AffixSubst[1], Acc));167}168 169// This class describes information associated to the LMUL.170class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,171 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {172 bits<3> value = lmul; // This is encoded as the vlmul field of vtype.173 VReg vrclass = regclass;174 VReg wvrclass = wregclass;175 VReg f8vrclass = f8regclass;176 VReg f4vrclass = f4regclass;177 VReg f2vrclass = f2regclass;178 string MX = mx;179 int octuple = oct;180}181 182// Associate LMUL with tablegen records of register classes.183def V_M1 : LMULInfo<0b000, 8, VR, VRM2, VR, VR, VR, "M1">;184def V_M2 : LMULInfo<0b001, 16, VRM2, VRM4, VR, VR, VR, "M2">;185def V_M4 : LMULInfo<0b010, 32, VRM4, VRM8, VRM2, VR, VR, "M4">;186def V_M8 : LMULInfo<0b011, 64, VRM8,/*NoVReg*/VR, VRM4, VRM2, VR, "M8">;187 188def V_MF8 : LMULInfo<0b101, 1, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF8">;189def V_MF4 : LMULInfo<0b110, 2, VR, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF4">;190def V_MF2 : LMULInfo<0b111, 4, VR, VR, VR, VR,/*NoVReg*/VR, "MF2">;191 192// Used to iterate over all possible LMULs.193defvar MxList = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];194// For floating point which don't need MF8.195defvar MxListF = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];196 197// Used for widening and narrowing instructions as it doesn't contain M8.198defvar MxListW = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4];199// Used for widening reductions. It can contain M8 because wider operands are200// scalar operands.201defvar MxListWRed = MxList;202// For floating point which don't need MF8.203defvar MxListFW = [V_MF4, V_MF2, V_M1, V_M2, V_M4];204// For widening floating-point Reduction as it doesn't contain MF8. It can205// contain M8 because wider operands are scalar operands.206defvar MxListFWRed = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];207 208// Use for zext/sext.vf2209defvar MxListVF2 = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];210 211// Use for zext/sext.vf4 and vector crypto instructions212defvar MxListVF4 = [V_MF2, V_M1, V_M2, V_M4, V_M8];213 214// Use for zext/sext.vf8215defvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8];216 217class MxSet<int eew> {218 list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],219 !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],220 !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],221 !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);222}223 224class FPR_Info<int sew> {225 RegisterClass fprclass = !cast<RegisterClass>("FPR" # sew);226 string FX = "FPR" # sew;227 int SEW = sew;228 list<LMULInfo> MxList = MxSet<sew>.m;229 list<LMULInfo> MxListFW = !if(!eq(sew, 64), [], !listremove(MxList, [V_M8]));230}231 232def SCALAR_F16 : FPR_Info<16>;233def SCALAR_F32 : FPR_Info<32>;234def SCALAR_F64 : FPR_Info<64>;235 236// BF16 uses the same register class as F16.237def SCALAR_BF16 : FPR_Info<16>;238 239defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];240 241// Used for widening instructions. It excludes F64.242defvar FPListW = [SCALAR_F16, SCALAR_F32];243 244// Used for widening bf16 instructions.245defvar BFPListW = [SCALAR_BF16];246 247class NFSet<LMULInfo m> {248 defvar lmul = !shl(1, m.value);249 list<int> L = NFList<lmul>.L;250}251 252class octuple_to_str<int octuple> {253 string ret = !cond(!eq(octuple, 1): "MF8",254 !eq(octuple, 2): "MF4",255 !eq(octuple, 4): "MF2",256 !eq(octuple, 8): "M1",257 !eq(octuple, 16): "M2",258 !eq(octuple, 32): "M4",259 !eq(octuple, 64): "M8");260}261 262def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;263 264// Output pattern for X0 used to represent VLMAX in the pseudo instructions.265// We can't use X0 register because the AVL operands use GPRNoX0.266// This must be kept in sync with RISCV::VLMaxSentinel.267def VLMax : OutPatFrag<(ops), (XLenVT -1)>;268 269def SelectScalarFPAsInt : ComplexPattern<fAny, 1, "selectScalarFPAsInt", [], [],270 1>;271 272// List of EEW.273defvar EEWList = [8, 16, 32, 64];274 275class SegRegClass<LMULInfo m, int nf> {276 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,277 !eq(m.value, V_MF4.value): V_M1.MX,278 !eq(m.value, V_MF2.value): V_M1.MX,279 true: m.MX));280}281 282//===----------------------------------------------------------------------===//283// Vector register and vector group type information.284//===----------------------------------------------------------------------===//285 286class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, LMULInfo M,287 ValueType Scal = XLenVT, RegisterClass ScalarReg = GPR> {288 ValueType Vector = Vec;289 ValueType Mask = Mas;290 int SEW = Sew;291 int Log2SEW = !logtwo(Sew);292 VReg RegClass = M.vrclass;293 LMULInfo LMul = M;294 ValueType Scalar = Scal;295 RegisterClass ScalarRegClass = ScalarReg;296 // The pattern fragment which produces the AVL operand, representing the297 // "natural" vector length for this type. For scalable vectors this is VLMax.298 OutPatFrag AVL = VLMax;299 300 string ScalarSuffix = !cond(!eq(Scal, XLenVT) : "X",301 !eq(Scal, f16) : "FPR16",302 !eq(Scal, bf16) : "FPR16",303 !eq(Scal, f32) : "FPR32",304 !eq(Scal, f64) : "FPR64");305}306 307class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,308 LMULInfo M, ValueType Scal = XLenVT,309 RegisterClass ScalarReg = GPR>310 : VTypeInfo<Vec, Mas, Sew, M, Scal, ScalarReg> {311 ValueType VectorM1 = VecM1;312}313 314defset list<VTypeInfo> AllVectors = {315 defset list<VTypeInfo> AllIntegerVectors = {316 defset list<VTypeInfo> NoGroupIntegerVectors = {317 defset list<VTypeInfo> FractionalGroupIntegerVectors = {318 def VI8MF8: VTypeInfo<vint8mf8_t, vbool64_t, 8, V_MF8>;319 def VI8MF4: VTypeInfo<vint8mf4_t, vbool32_t, 8, V_MF4>;320 def VI8MF2: VTypeInfo<vint8mf2_t, vbool16_t, 8, V_MF2>;321 def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, V_MF4>;322 def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, V_MF2>;323 def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, V_MF2>;324 }325 def VI8M1: VTypeInfo<vint8m1_t, vbool8_t, 8, V_M1>;326 def VI16M1: VTypeInfo<vint16m1_t, vbool16_t, 16, V_M1>;327 def VI32M1: VTypeInfo<vint32m1_t, vbool32_t, 32, V_M1>;328 def VI64M1: VTypeInfo<vint64m1_t, vbool64_t, 64, V_M1>;329 }330 defset list<GroupVTypeInfo> GroupIntegerVectors = {331 def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, V_M2>;332 def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, V_M4>;333 def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, V_M8>;334 335 def VI16M2: GroupVTypeInfo<vint16m2_t, vint16m1_t, vbool8_t, 16, V_M2>;336 def VI16M4: GroupVTypeInfo<vint16m4_t, vint16m1_t, vbool4_t, 16, V_M4>;337 def VI16M8: GroupVTypeInfo<vint16m8_t, vint16m1_t, vbool2_t, 16, V_M8>;338 339 def VI32M2: GroupVTypeInfo<vint32m2_t, vint32m1_t, vbool16_t, 32, V_M2>;340 def VI32M4: GroupVTypeInfo<vint32m4_t, vint32m1_t, vbool8_t, 32, V_M4>;341 def VI32M8: GroupVTypeInfo<vint32m8_t, vint32m1_t, vbool4_t, 32, V_M8>;342 343 def VI64M2: GroupVTypeInfo<vint64m2_t, vint64m1_t, vbool32_t, 64, V_M2>;344 def VI64M4: GroupVTypeInfo<vint64m4_t, vint64m1_t, vbool16_t, 64, V_M4>;345 def VI64M8: GroupVTypeInfo<vint64m8_t, vint64m1_t, vbool8_t, 64, V_M8>;346 }347 }348 349 defset list<VTypeInfo> AllFloatAndBF16Vectors = {350 defset list<VTypeInfo> AllFloatVectors = {351 defset list<VTypeInfo> NoGroupFloatVectors = {352 defset list<VTypeInfo> FractionalGroupFloatVectors = {353 def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, V_MF4, f16, FPR16>;354 def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, V_MF2, f16, FPR16>;355 def VF32MF2: VTypeInfo<vfloat32mf2_t, vbool64_t, 32, V_MF2, f32, FPR32>;356 }357 def VF16M1: VTypeInfo<vfloat16m1_t, vbool16_t, 16, V_M1, f16, FPR16>;358 def VF32M1: VTypeInfo<vfloat32m1_t, vbool32_t, 32, V_M1, f32, FPR32>;359 def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, V_M1, f64, FPR64>;360 }361 362 defset list<GroupVTypeInfo> GroupFloatVectors = {363 def VF16M2: GroupVTypeInfo<vfloat16m2_t, vfloat16m1_t, vbool8_t, 16,364 V_M2, f16, FPR16>;365 def VF16M4: GroupVTypeInfo<vfloat16m4_t, vfloat16m1_t, vbool4_t, 16,366 V_M4, f16, FPR16>;367 def VF16M8: GroupVTypeInfo<vfloat16m8_t, vfloat16m1_t, vbool2_t, 16,368 V_M8, f16, FPR16>;369 370 def VF32M2: GroupVTypeInfo<vfloat32m2_t, vfloat32m1_t, vbool16_t, 32,371 V_M2, f32, FPR32>;372 def VF32M4: GroupVTypeInfo<vfloat32m4_t, vfloat32m1_t, vbool8_t, 32,373 V_M4, f32, FPR32>;374 def VF32M8: GroupVTypeInfo<vfloat32m8_t, vfloat32m1_t, vbool4_t, 32,375 V_M8, f32, FPR32>;376 377 def VF64M2: GroupVTypeInfo<vfloat64m2_t, vfloat64m1_t, vbool32_t, 64,378 V_M2, f64, FPR64>;379 def VF64M4: GroupVTypeInfo<vfloat64m4_t, vfloat64m1_t, vbool16_t, 64,380 V_M4, f64, FPR64>;381 def VF64M8: GroupVTypeInfo<vfloat64m8_t, vfloat64m1_t, vbool8_t, 64,382 V_M8, f64, FPR64>;383 }384 }385 386 defset list<VTypeInfo> AllBF16Vectors = {387 defset list<VTypeInfo> NoGroupBF16Vectors = {388 defset list<VTypeInfo> FractionalGroupBF16Vectors = {389 def VBF16MF4: VTypeInfo<vbfloat16mf4_t, vbool64_t, 16, V_MF4, bf16, FPR16>;390 def VBF16MF2: VTypeInfo<vbfloat16mf2_t, vbool32_t, 16, V_MF2, bf16, FPR16>;391 }392 def VBF16M1: VTypeInfo<vbfloat16m1_t, vbool16_t, 16, V_M1, bf16, FPR16>;393 }394 395 defset list<GroupVTypeInfo> GroupBF16Vectors = {396 def VBF16M2: GroupVTypeInfo<vbfloat16m2_t, vbfloat16m1_t, vbool8_t, 16,397 V_M2, bf16, FPR16>;398 def VBF16M4: GroupVTypeInfo<vbfloat16m4_t, vbfloat16m1_t, vbool4_t, 16,399 V_M4, bf16, FPR16>;400 def VBF16M8: GroupVTypeInfo<vbfloat16m8_t, vbfloat16m1_t, vbool2_t, 16,401 V_M8, bf16, FPR16>;402 }403 }404 }405}406 407defvar AllFP16Vectors = !filter(vti, AllFloatVectors, !eq(vti.Scalar, f16));408 409// This functor is used to obtain the int vector type that has the same SEW and410// multiplier as the input parameter type411class GetIntVTypeInfo<VTypeInfo vti> {412 // Equivalent integer vector type. Eg.413 // VI8M1 → VI8M1 (identity)414 // VF64M4 → VI64M4415 VTypeInfo Vti = !cast<VTypeInfo>(!subst("VBF", "VI",416 !subst("VF", "VI",417 !cast<string>(vti))));418}419 420class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {421 ValueType Mask = Mas;422 // {SEW, VLMul} values set a valid VType to deal with this mask type.423 // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will424 // look for SEW=1 to optimize based on surrounding instructions.425 int SEW = 1;426 int Log2SEW = 0;427 LMULInfo LMul = M;428 string BX = Bx; // Appendix of mask operations.429 // The pattern fragment which produces the AVL operand, representing the430 // "natural" vector length for this mask type. For scalable masks this is431 // VLMax.432 OutPatFrag AVL = VLMax;433}434 435defset list<MTypeInfo> AllMasks = {436 // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.437 def : MTypeInfo<vbool64_t, V_MF8, "B64">;438 def : MTypeInfo<vbool32_t, V_MF4, "B32">;439 def : MTypeInfo<vbool16_t, V_MF2, "B16">;440 def : MTypeInfo<vbool8_t, V_M1, "B8">;441 def : MTypeInfo<vbool4_t, V_M2, "B4">;442 def : MTypeInfo<vbool2_t, V_M4, "B2">;443 def : MTypeInfo<vbool1_t, V_M8, "B1">;444}445 446class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti> {447 VTypeInfo Vti = vti;448 VTypeInfo Wti = wti;449}450 451class VTypeInfoToFraction<VTypeInfo vti, VTypeInfo fti> {452 VTypeInfo Vti = vti;453 VTypeInfo Fti = fti;454}455 456defset list<VTypeInfoToWide> AllWidenableIntVectors = {457 def : VTypeInfoToWide<VI8MF8, VI16MF4>;458 def : VTypeInfoToWide<VI8MF4, VI16MF2>;459 def : VTypeInfoToWide<VI8MF2, VI16M1>;460 def : VTypeInfoToWide<VI8M1, VI16M2>;461 def : VTypeInfoToWide<VI8M2, VI16M4>;462 def : VTypeInfoToWide<VI8M4, VI16M8>;463 464 def : VTypeInfoToWide<VI16MF4, VI32MF2>;465 def : VTypeInfoToWide<VI16MF2, VI32M1>;466 def : VTypeInfoToWide<VI16M1, VI32M2>;467 def : VTypeInfoToWide<VI16M2, VI32M4>;468 def : VTypeInfoToWide<VI16M4, VI32M8>;469 470 def : VTypeInfoToWide<VI32MF2, VI64M1>;471 def : VTypeInfoToWide<VI32M1, VI64M2>;472 def : VTypeInfoToWide<VI32M2, VI64M4>;473 def : VTypeInfoToWide<VI32M4, VI64M8>;474}475 476defset list<VTypeInfoToWide> AllWidenableFloatVectors = {477 def : VTypeInfoToWide<VF16MF4, VF32MF2>;478 def : VTypeInfoToWide<VF16MF2, VF32M1>;479 def : VTypeInfoToWide<VF16M1, VF32M2>;480 def : VTypeInfoToWide<VF16M2, VF32M4>;481 def : VTypeInfoToWide<VF16M4, VF32M8>;482 483 def : VTypeInfoToWide<VF32MF2, VF64M1>;484 def : VTypeInfoToWide<VF32M1, VF64M2>;485 def : VTypeInfoToWide<VF32M2, VF64M4>;486 def : VTypeInfoToWide<VF32M4, VF64M8>;487}488 489defset list<VTypeInfoToFraction> AllFractionableVF2IntVectors = {490 def : VTypeInfoToFraction<VI16MF4, VI8MF8>;491 def : VTypeInfoToFraction<VI16MF2, VI8MF4>;492 def : VTypeInfoToFraction<VI16M1, VI8MF2>;493 def : VTypeInfoToFraction<VI16M2, VI8M1>;494 def : VTypeInfoToFraction<VI16M4, VI8M2>;495 def : VTypeInfoToFraction<VI16M8, VI8M4>;496 def : VTypeInfoToFraction<VI32MF2, VI16MF4>;497 def : VTypeInfoToFraction<VI32M1, VI16MF2>;498 def : VTypeInfoToFraction<VI32M2, VI16M1>;499 def : VTypeInfoToFraction<VI32M4, VI16M2>;500 def : VTypeInfoToFraction<VI32M8, VI16M4>;501 def : VTypeInfoToFraction<VI64M1, VI32MF2>;502 def : VTypeInfoToFraction<VI64M2, VI32M1>;503 def : VTypeInfoToFraction<VI64M4, VI32M2>;504 def : VTypeInfoToFraction<VI64M8, VI32M4>;505}506 507defset list<VTypeInfoToFraction> AllFractionableVF4IntVectors = {508 def : VTypeInfoToFraction<VI32MF2, VI8MF8>;509 def : VTypeInfoToFraction<VI32M1, VI8MF4>;510 def : VTypeInfoToFraction<VI32M2, VI8MF2>;511 def : VTypeInfoToFraction<VI32M4, VI8M1>;512 def : VTypeInfoToFraction<VI32M8, VI8M2>;513 def : VTypeInfoToFraction<VI64M1, VI16MF4>;514 def : VTypeInfoToFraction<VI64M2, VI16MF2>;515 def : VTypeInfoToFraction<VI64M4, VI16M1>;516 def : VTypeInfoToFraction<VI64M8, VI16M2>;517}518 519defset list<VTypeInfoToFraction> AllFractionableVF8IntVectors = {520 def : VTypeInfoToFraction<VI64M1, VI8MF8>;521 def : VTypeInfoToFraction<VI64M2, VI8MF4>;522 def : VTypeInfoToFraction<VI64M4, VI8MF2>;523 def : VTypeInfoToFraction<VI64M8, VI8M1>;524}525 526defset list<VTypeInfoToWide> AllWidenableIntToFloatVectors = {527 def : VTypeInfoToWide<VI8MF8, VF16MF4>;528 def : VTypeInfoToWide<VI8MF4, VF16MF2>;529 def : VTypeInfoToWide<VI8MF2, VF16M1>;530 def : VTypeInfoToWide<VI8M1, VF16M2>;531 def : VTypeInfoToWide<VI8M2, VF16M4>;532 def : VTypeInfoToWide<VI8M4, VF16M8>;533 534 def : VTypeInfoToWide<VI16MF4, VF32MF2>;535 def : VTypeInfoToWide<VI16MF2, VF32M1>;536 def : VTypeInfoToWide<VI16M1, VF32M2>;537 def : VTypeInfoToWide<VI16M2, VF32M4>;538 def : VTypeInfoToWide<VI16M4, VF32M8>;539 540 def : VTypeInfoToWide<VI32MF2, VF64M1>;541 def : VTypeInfoToWide<VI32M1, VF64M2>;542 def : VTypeInfoToWide<VI32M2, VF64M4>;543 def : VTypeInfoToWide<VI32M4, VF64M8>;544}545 546defset list<VTypeInfoToWide> AllWidenableBF16ToFloatVectors = {547 def : VTypeInfoToWide<VBF16MF4, VF32MF2>;548 def : VTypeInfoToWide<VBF16MF2, VF32M1>;549 def : VTypeInfoToWide<VBF16M1, VF32M2>;550 def : VTypeInfoToWide<VBF16M2, VF32M4>;551 def : VTypeInfoToWide<VBF16M4, VF32M8>;552}553 554// This class holds the record of the RISCVVPseudoTable below.555// This represents the information we need in codegen for each pseudo.556// The definition should be consistent with `struct PseudoInfo` in557// RISCVInstrInfo.h.558class RISCVVPseudo<dag outs, dag ins, list<dag> pattern = [],559 string opcodestr = "", string argstr = "">560 : Pseudo<outs, ins, pattern, opcodestr, argstr> {561 Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.562 Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);563 // SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown).564 bits<8> SEW = 0;565 bit IncludeInInversePseudoTable = 1;566}567 568// The actual table.569def RISCVVPseudosTable : GenericTable {570 let FilterClass = "RISCVVPseudo";571 let CppTypeName = "PseudoInfo";572 let Fields = [ "Pseudo", "BaseInstr" ];573 let PrimaryKey = [ "Pseudo" ];574 let PrimaryKeyName = "getPseudoInfo";575 let PrimaryKeyEarlyOut = true;576}577 578def RISCVVInversePseudosTable : GenericTable {579 let FilterClass = "RISCVVPseudo";580 let FilterClassField = "IncludeInInversePseudoTable";581 let CppTypeName = "PseudoInfo";582 let Fields = [ "Pseudo", "BaseInstr", "VLMul", "SEW"];583 let PrimaryKey = [ "BaseInstr", "VLMul", "SEW"];584 let PrimaryKeyName = "getBaseInfo";585 let PrimaryKeyEarlyOut = true;586}587 588def RISCVVIntrinsicsTable : GenericTable {589 let FilterClass = "RISCVVIntrinsic";590 let CppTypeName = "RISCVVIntrinsicInfo";591 let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand", "IsFPIntrinsic"];592 let PrimaryKey = ["IntrinsicID"];593 let PrimaryKeyName = "getRISCVVIntrinsicInfo";594}595 596// Describes the relation of a masked pseudo to the unmasked variants.597// Note that all masked variants (in this table) have exactly one598// unmasked variant. For all but compares, both the masked and599// unmasked variant have a passthru and policy operand. For compares,600// neither has a policy op, and only the masked version has a passthru.601class RISCVMaskedPseudo<bits<4> MaskIdx> {602 Pseudo MaskedPseudo = !cast<Pseudo>(NAME);603 Pseudo UnmaskedPseudo = !cast<Pseudo>(!subst("_MASK", "", NAME));604 bits<4> MaskOpIdx = MaskIdx;605}606 607def RISCVMaskedPseudosTable : GenericTable {608 let FilterClass = "RISCVMaskedPseudo";609 let CppTypeName = "RISCVMaskedPseudoInfo";610 let Fields = ["MaskedPseudo", "UnmaskedPseudo", "MaskOpIdx"];611 let PrimaryKey = ["MaskedPseudo"];612 let PrimaryKeyName = "getMaskedPseudoInfo";613}614 615class RISCVVLE<bit M, bit Str, bit F, bits<3> S, bits<3> L> {616 bits<1> Masked = M;617 bits<1> Strided = Str;618 bits<1> FF = F;619 bits<3> Log2SEW = S;620 bits<3> LMUL = L;621 Pseudo Pseudo = !cast<Pseudo>(NAME);622}623 624def lookupMaskedIntrinsicByUnmasked : SearchIndex {625 let Table = RISCVMaskedPseudosTable;626 let Key = ["UnmaskedPseudo"];627}628 629def RISCVVLETable : GenericTable {630 let FilterClass = "RISCVVLE";631 let CppTypeName = "VLEPseudo";632 let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];633 let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"];634 let PrimaryKeyName = "getVLEPseudo";635}636 637class RISCVVSE<bit M, bit Str, bits<3> S, bits<3> L> {638 bits<1> Masked = M;639 bits<1> Strided = Str;640 bits<3> Log2SEW = S;641 bits<3> LMUL = L;642 Pseudo Pseudo = !cast<Pseudo>(NAME);643}644 645def RISCVVSETable : GenericTable {646 let FilterClass = "RISCVVSE";647 let CppTypeName = "VSEPseudo";648 let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];649 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];650 let PrimaryKeyName = "getVSEPseudo";651}652 653class RISCVVLX_VSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> {654 bits<1> Masked = M;655 bits<1> Ordered = O;656 bits<3> Log2SEW = S;657 bits<3> LMUL = L;658 bits<3> IndexLMUL = IL;659 Pseudo Pseudo = !cast<Pseudo>(NAME);660}661 662class RISCVVLX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> :663 RISCVVLX_VSX<M, O, S, L, IL>;664class RISCVVSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> :665 RISCVVLX_VSX<M, O, S, L, IL>;666 667class RISCVVLX_VSXTable : GenericTable {668 let CppTypeName = "VLX_VSXPseudo";669 let Fields = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];670 let PrimaryKey = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];671}672 673def RISCVVLXTable : RISCVVLX_VSXTable {674 let FilterClass = "RISCVVLX";675 let PrimaryKeyName = "getVLXPseudo";676}677 678def RISCVVSXTable : RISCVVLX_VSXTable {679 let FilterClass = "RISCVVSX";680 let PrimaryKeyName = "getVSXPseudo";681}682 683class RISCVVLSEG<bits<4> N, bit M, bit Str, bit F, bits<3> S, bits<3> L> {684 bits<4> NF = N;685 bits<1> Masked = M;686 bits<1> Strided = Str;687 bits<1> FF = F;688 bits<3> Log2SEW = S;689 bits<3> LMUL = L;690 Pseudo Pseudo = !cast<Pseudo>(NAME);691}692 693def RISCVVLSEGTable : GenericTable {694 let FilterClass = "RISCVVLSEG";695 let CppTypeName = "VLSEGPseudo";696 let Fields = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];697 let PrimaryKey = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL"];698 let PrimaryKeyName = "getVLSEGPseudo";699}700 701class RISCVVLXSEG<bits<4> N, bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> {702 bits<4> NF = N;703 bits<1> Masked = M;704 bits<1> Ordered = O;705 bits<3> Log2SEW = S;706 bits<3> LMUL = L;707 bits<3> IndexLMUL = IL;708 Pseudo Pseudo = !cast<Pseudo>(NAME);709}710 711def RISCVVLXSEGTable : GenericTable {712 let FilterClass = "RISCVVLXSEG";713 let CppTypeName = "VLXSEGPseudo";714 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];715 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];716 let PrimaryKeyName = "getVLXSEGPseudo";717}718 719class RISCVVSSEG<bits<4> N, bit M, bit Str, bits<3> S, bits<3> L> {720 bits<4> NF = N;721 bits<1> Masked = M;722 bits<1> Strided = Str;723 bits<3> Log2SEW = S;724 bits<3> LMUL = L;725 Pseudo Pseudo = !cast<Pseudo>(NAME);726}727 728def RISCVVSSEGTable : GenericTable {729 let FilterClass = "RISCVVSSEG";730 let CppTypeName = "VSSEGPseudo";731 let Fields = ["NF", "Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];732 let PrimaryKey = ["NF", "Masked", "Strided", "Log2SEW", "LMUL"];733 let PrimaryKeyName = "getVSSEGPseudo";734}735 736class RISCVVSXSEG<bits<4> N, bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> {737 bits<4> NF = N;738 bits<1> Masked = M;739 bits<1> Ordered = O;740 bits<3> Log2SEW = S;741 bits<3> LMUL = L;742 bits<3> IndexLMUL = IL;743 Pseudo Pseudo = !cast<Pseudo>(NAME);744}745 746def RISCVVSXSEGTable : GenericTable {747 let FilterClass = "RISCVVSXSEG";748 let CppTypeName = "VSXSEGPseudo";749 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];750 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];751 let PrimaryKeyName = "getVSXSEGPseudo";752}753 754//===----------------------------------------------------------------------===//755// Helpers to define the different pseudo instructions.756//===----------------------------------------------------------------------===//757 758// The destination vector register group for a masked vector instruction cannot759// overlap the source mask register (v0), unless the destination vector register760// is being written with a mask value (e.g., comparisons) or the scalar result761// of a reduction.762class GetVRegNoV0<VReg VRegClass> {763 VReg R = !cond(!eq(VRegClass, VR) : VRNoV0,764 !eq(VRegClass, VRM2) : VRM2NoV0,765 !eq(VRegClass, VRM4) : VRM4NoV0,766 !eq(VRegClass, VRM8) : VRM8NoV0,767 !eq(VRegClass, VRN2M1) : VRN2M1NoV0,768 !eq(VRegClass, VRN2M2) : VRN2M2NoV0,769 !eq(VRegClass, VRN2M4) : VRN2M4NoV0,770 !eq(VRegClass, VRN3M1) : VRN3M1NoV0,771 !eq(VRegClass, VRN3M2) : VRN3M2NoV0,772 !eq(VRegClass, VRN4M1) : VRN4M1NoV0,773 !eq(VRegClass, VRN4M2) : VRN4M2NoV0,774 !eq(VRegClass, VRN5M1) : VRN5M1NoV0,775 !eq(VRegClass, VRN6M1) : VRN6M1NoV0,776 !eq(VRegClass, VRN7M1) : VRN7M1NoV0,777 !eq(VRegClass, VRN8M1) : VRN8M1NoV0,778 true : VRegClass);779}780 781class GetVTypePredicates<VTypeInfo vti> {782 list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16],783 !eq(vti.Scalar, bf16) : [HasVInstructionsBF16Minimal],784 !eq(vti.Scalar, f32) : [HasVInstructionsAnyF],785 !eq(vti.Scalar, f64) : [HasVInstructionsF64],786 !eq(vti.SEW, 64) : [HasVInstructionsI64],787 true : [HasVInstructions]);788}789 790class GetVTypeMinimalPredicates<VTypeInfo vti> {791 list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16Minimal],792 !eq(vti.Scalar, bf16) : [HasVInstructionsBF16Minimal],793 !eq(vti.Scalar, f32) : [HasVInstructionsAnyF],794 !eq(vti.Scalar, f64) : [HasVInstructionsF64],795 !eq(vti.SEW, 64) : [HasVInstructionsI64],796 true : [HasVInstructions]);797}798 799class VPseudoUSLoadNoMask<VReg RetClass,800 int EEW,801 DAGOperand sewop = sew> :802 RISCVVPseudo<(outs RetClass:$rd),803 (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,804 sewop:$sew, vec_policy:$policy)>,805 RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {806 let mayLoad = 1;807 let mayStore = 0;808 let hasSideEffects = 0;809 let HasVLOp = 1;810 let HasSEWOp = 1;811 let HasVecPolicyOp = 1;812 let Constraints = "$rd = $dest";813}814 815class VPseudoUSLoadMask<VReg RetClass,816 int EEW> :817 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),818 (ins GetVRegNoV0<RetClass>.R:$passthru,819 GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew,820 vec_policy:$policy)>,821 RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {822 let mayLoad = 1;823 let mayStore = 0;824 let hasSideEffects = 0;825 let Constraints = "$rd = $passthru";826 let HasVLOp = 1;827 let HasSEWOp = 1;828 let HasVecPolicyOp = 1;829 let UsesMaskPolicy = 1;830 let IncludeInInversePseudoTable = 0;831}832 833class VPseudoUSLoadFFNoMask<VReg RetClass,834 int EEW> :835 RISCVVPseudo<(outs RetClass:$rd, GPR:$vl),836 (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,837 sew:$sew, vec_policy:$policy)>,838 RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {839 let mayLoad = 1;840 let mayStore = 0;841 let hasSideEffects = 0;842 let HasVLOp = 1;843 let HasSEWOp = 1;844 let HasVecPolicyOp = 1;845 let Constraints = "$rd = $dest";846}847 848class VPseudoUSLoadFFMask<VReg RetClass,849 int EEW> :850 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),851 (ins GetVRegNoV0<RetClass>.R:$passthru,852 GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew,853 vec_policy:$policy)>,854 RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {855 let mayLoad = 1;856 let mayStore = 0;857 let hasSideEffects = 0;858 let Constraints = "$rd = $passthru";859 let HasVLOp = 1;860 let HasSEWOp = 1;861 let HasVecPolicyOp = 1;862 let UsesMaskPolicy = 1;863 let IncludeInInversePseudoTable = 0;864}865 866class VPseudoSLoadNoMask<VReg RetClass,867 int EEW> :868 RISCVVPseudo<(outs RetClass:$rd),869 (ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2,870 AVL:$vl, sew:$sew, vec_policy:$policy)>,871 RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {872 let mayLoad = 1;873 let mayStore = 0;874 let hasSideEffects = 0;875 let HasVLOp = 1;876 let HasSEWOp = 1;877 let HasVecPolicyOp = 1;878 let Constraints = "$rd = $dest";879}880 881class VPseudoSLoadMask<VReg RetClass,882 int EEW> :883 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),884 (ins GetVRegNoV0<RetClass>.R:$passthru,885 GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl,886 sew:$sew, vec_policy:$policy)>,887 RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {888 let mayLoad = 1;889 let mayStore = 0;890 let hasSideEffects = 0;891 let Constraints = "$rd = $passthru";892 let HasVLOp = 1;893 let HasSEWOp = 1;894 let HasVecPolicyOp = 1;895 let UsesMaskPolicy = 1;896 let IncludeInInversePseudoTable = 0;897}898 899class VPseudoILoadNoMask<VReg RetClass,900 VReg IdxClass,901 int EEW,902 bits<3> LMUL,903 bit Ordered,904 bit EarlyClobber,905 bits<2> TargetConstraintType = 1> :906 RISCVVPseudo<(outs RetClass:$rd),907 (ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2,908 AVL:$vl, sew:$sew, vec_policy:$policy)>,909 RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {910 let mayLoad = 1;911 let mayStore = 0;912 let hasSideEffects = 0;913 let HasVLOp = 1;914 let HasSEWOp = 1;915 let HasVecPolicyOp = 1;916 let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");917 let TargetOverlapConstraintType = TargetConstraintType;918}919 920class VPseudoILoadMask<VReg RetClass,921 VReg IdxClass,922 int EEW,923 bits<3> LMUL,924 bit Ordered,925 bit EarlyClobber,926 bits<2> TargetConstraintType = 1> :927 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),928 (ins GetVRegNoV0<RetClass>.R:$passthru,929 GPRMemZeroOffset:$rs1, IdxClass:$rs2, VMaskOp:$vm,930 AVL:$vl, sew:$sew, vec_policy:$policy)>,931 RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {932 let mayLoad = 1;933 let mayStore = 0;934 let hasSideEffects = 0;935 let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $passthru", "$rd = $passthru");936 let TargetOverlapConstraintType = TargetConstraintType;937 let HasVLOp = 1;938 let HasSEWOp = 1;939 let HasVecPolicyOp = 1;940 let UsesMaskPolicy = 1;941 let IncludeInInversePseudoTable = 0;942}943 944class VPseudoUSStoreNoMask<VReg StClass,945 int EEW,946 DAGOperand sewop = sew> :947 RISCVVPseudo<(outs),948 (ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl,949 sewop:$sew)>,950 RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {951 let mayLoad = 0;952 let mayStore = 1;953 let hasSideEffects = 0;954 let HasVLOp = 1;955 let HasSEWOp = 1;956}957 958class VPseudoUSStoreMask<VReg StClass,959 int EEW> :960 RISCVVPseudo<(outs),961 (ins StClass:$rd, GPRMemZeroOffset:$rs1,962 VMaskOp:$vm, AVL:$vl, sew:$sew)>,963 RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {964 let mayLoad = 0;965 let mayStore = 1;966 let hasSideEffects = 0;967 let HasVLOp = 1;968 let HasSEWOp = 1;969 let IncludeInInversePseudoTable = 0;970}971 972class VPseudoSStoreNoMask<VReg StClass,973 int EEW> :974 RISCVVPseudo<(outs),975 (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,976 AVL:$vl, sew:$sew)>,977 RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {978 let mayLoad = 0;979 let mayStore = 1;980 let hasSideEffects = 0;981 let HasVLOp = 1;982 let HasSEWOp = 1;983}984 985class VPseudoSStoreMask<VReg StClass,986 int EEW> :987 RISCVVPseudo<(outs),988 (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,989 VMaskOp:$vm, AVL:$vl, sew:$sew)>,990 RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {991 let mayLoad = 0;992 let mayStore = 1;993 let hasSideEffects = 0;994 let HasVLOp = 1;995 let HasSEWOp = 1;996 let IncludeInInversePseudoTable = 0;997}998 999class VPseudoNullaryNoMask<VReg RegClass> :1000 RISCVVPseudo<(outs RegClass:$rd),1001 (ins RegClass:$passthru,1002 AVL:$vl, sew:$sew, vec_policy:$policy)> {1003 let mayLoad = 0;1004 let mayStore = 0;1005 let hasSideEffects = 0;1006 let Constraints = "$rd = $passthru";1007 let HasVLOp = 1;1008 let HasSEWOp = 1;1009 let HasVecPolicyOp = 1;1010}1011 1012class VPseudoNullaryMask<VReg RegClass> :1013 RISCVVPseudo<(outs GetVRegNoV0<RegClass>.R:$rd),1014 (ins GetVRegNoV0<RegClass>.R:$passthru,1015 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {1016 let mayLoad = 0;1017 let mayStore = 0;1018 let hasSideEffects = 0;1019 let Constraints ="$rd = $passthru";1020 let HasVLOp = 1;1021 let HasSEWOp = 1;1022 let UsesMaskPolicy = 1;1023 let HasVecPolicyOp = 1;1024 let IncludeInInversePseudoTable = 0;1025}1026 1027// Nullary for pseudo instructions. They are expanded in1028// RISCVExpandPseudoInsts pass.1029class VPseudoNullaryPseudoM<string BaseInst> :1030 RISCVVPseudo<(outs VR:$rd), (ins AVL:$vl, sew_mask:$sew)> {1031 let mayLoad = 0;1032 let mayStore = 0;1033 let hasSideEffects = 0;1034 let HasVLOp = 1;1035 let HasSEWOp = 1;1036 let BaseInstr = !cast<Instruction>(BaseInst);1037 let IncludeInInversePseudoTable = 0;1038}1039 1040class VPseudoUnaryNoMask<DAGOperand RetClass,1041 DAGOperand OpClass,1042 string Constraint = "",1043 bits<2> TargetConstraintType = 1> :1044 RISCVVPseudo<(outs RetClass:$rd),1045 (ins RetClass:$passthru, OpClass:$rs2,1046 AVL:$vl, sew:$sew, vec_policy:$policy)> {1047 let mayLoad = 0;1048 let mayStore = 0;1049 let hasSideEffects = 0;1050 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1051 let TargetOverlapConstraintType = TargetConstraintType;1052 let HasVLOp = 1;1053 let HasSEWOp = 1;1054 let HasVecPolicyOp = 1;1055}1056 1057class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,1058 DAGOperand OpClass,1059 string Constraint = "",1060 bits<2> TargetConstraintType = 1> :1061 RISCVVPseudo<(outs RetClass:$rd),1062 (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew)> {1063 let mayLoad = 0;1064 let mayStore = 0;1065 let hasSideEffects = 0;1066 let Constraints = Constraint;1067 let TargetOverlapConstraintType = TargetConstraintType;1068 let HasVLOp = 1;1069 let HasSEWOp = 1;1070}1071 1072class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,1073 DAGOperand OpClass,1074 string Constraint = "",1075 bits<2> TargetConstraintType = 1> :1076 RISCVVPseudo<(outs RetClass:$rd),1077 (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,1078 AVL:$vl, sew:$sew, vec_policy:$policy)> {1079 let mayLoad = 0;1080 let mayStore = 0;1081 let hasSideEffects = 0;1082 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1083 let TargetOverlapConstraintType = TargetConstraintType;1084 let HasVLOp = 1;1085 let HasSEWOp = 1;1086 let HasVecPolicyOp = 1;1087 let HasRoundModeOp = 1;1088 let UsesVXRM = 0;1089 let hasPostISelHook = 1;1090}1091 1092class VPseudoUnaryMask<VReg RetClass,1093 VReg OpClass,1094 string Constraint = "",1095 bits<2> TargetConstraintType = 1,1096 DAGOperand sewop = sew> :1097 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1098 (ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,1099 VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy)> {1100 let mayLoad = 0;1101 let mayStore = 0;1102 let hasSideEffects = 0;1103 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1104 let TargetOverlapConstraintType = TargetConstraintType;1105 let HasVLOp = 1;1106 let HasSEWOp = 1;1107 let HasVecPolicyOp = 1;1108 let UsesMaskPolicy = 1;1109 let IncludeInInversePseudoTable = 0;1110}1111 1112class VPseudoUnaryMaskRoundingMode<VReg RetClass,1113 VReg OpClass,1114 string Constraint = "",1115 bits<2> TargetConstraintType = 1> :1116 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1117 (ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,1118 VMaskOp:$vm, vec_rm:$rm,1119 AVL:$vl, sew:$sew, vec_policy:$policy)> {1120 let mayLoad = 0;1121 let mayStore = 0;1122 let hasSideEffects = 0;1123 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1124 let TargetOverlapConstraintType = TargetConstraintType;1125 let HasVLOp = 1;1126 let HasSEWOp = 1;1127 let HasVecPolicyOp = 1;1128 let UsesMaskPolicy = 1;1129 let HasRoundModeOp = 1;1130 let UsesVXRM = 0;1131 let hasPostISelHook = 1;1132 let IncludeInInversePseudoTable = 0;1133}1134 1135class VPseudoUnaryMask_NoExcept<VReg RetClass,1136 VReg OpClass,1137 string Constraint = ""> :1138 Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1139 (ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,1140 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> {1141 let mayLoad = 0;1142 let mayStore = 0;1143 let hasSideEffects = 0;1144 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1145 let HasVLOp = 1;1146 let HasSEWOp = 1;1147 let HasVecPolicyOp = 1;1148 let UsesMaskPolicy = 1;1149 let usesCustomInserter = 1;1150}1151 1152class VPseudoUnaryNoMaskGPROut :1153 RISCVVPseudo<(outs GPR:$rd),1154 (ins VR:$rs2, AVL:$vl, sew_mask:$sew)> {1155 let mayLoad = 0;1156 let mayStore = 0;1157 let hasSideEffects = 0;1158 let HasVLOp = 1;1159 let HasSEWOp = 1;1160}1161 1162class VPseudoUnaryMaskGPROut :1163 RISCVVPseudo<(outs GPR:$rd),1164 (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew)> {1165 let mayLoad = 0;1166 let mayStore = 0;1167 let hasSideEffects = 0;1168 let HasVLOp = 1;1169 let HasSEWOp = 1;1170 let IncludeInInversePseudoTable = 0;1171}1172 1173// Mask can be V0~V311174class VPseudoUnaryAnyMask<VReg RetClass,1175 VReg Op1Class> :1176 RISCVVPseudo<(outs RetClass:$rd),1177 (ins RetClass:$passthru, Op1Class:$rs2,1178 VR:$vm, AVL:$vl, sew:$sew)> {1179 let mayLoad = 0;1180 let mayStore = 0;1181 let hasSideEffects = 0;1182 let Constraints = "@earlyclobber $rd, $rd = $passthru";1183 let HasVLOp = 1;1184 let HasSEWOp = 1;1185}1186 1187class VPseudoBinaryNoMask<VReg RetClass,1188 VReg Op1Class,1189 DAGOperand Op2Class,1190 string Constraint,1191 bits<2> TargetConstraintType = 1,1192 DAGOperand sewop = sew> :1193 RISCVVPseudo<(outs RetClass:$rd),1194 (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew)> {1195 let mayLoad = 0;1196 let mayStore = 0;1197 let hasSideEffects = 0;1198 let Constraints = Constraint;1199 let TargetOverlapConstraintType = TargetConstraintType;1200 let HasVLOp = 1;1201 let HasSEWOp = 1;1202}1203 1204class VPseudoBinaryNoMaskPolicy<VReg RetClass,1205 VReg Op1Class,1206 DAGOperand Op2Class,1207 string Constraint,1208 bits<2> TargetConstraintType = 1> :1209 RISCVVPseudo<(outs RetClass:$rd),1210 (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,1211 AVL:$vl, sew:$sew, vec_policy:$policy)> {1212 let mayLoad = 0;1213 let mayStore = 0;1214 let hasSideEffects = 0;1215 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1216 let TargetOverlapConstraintType = TargetConstraintType;1217 let HasVLOp = 1;1218 let HasSEWOp = 1;1219 let HasVecPolicyOp = 1;1220}1221 1222class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,1223 VReg Op1Class,1224 DAGOperand Op2Class,1225 string Constraint,1226 bit UsesVXRM_ = 1,1227 bits<2> TargetConstraintType = 1> :1228 RISCVVPseudo<(outs RetClass:$rd),1229 (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,1230 vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy)> {1231 let mayLoad = 0;1232 let mayStore = 0;1233 let hasSideEffects = 0;1234 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1235 let TargetOverlapConstraintType = TargetConstraintType;1236 let HasVLOp = 1;1237 let HasSEWOp = 1;1238 let HasVecPolicyOp = 1;1239 let HasRoundModeOp = 1;1240 let UsesVXRM = UsesVXRM_;1241 let hasPostISelHook = !not(UsesVXRM_);1242}1243 1244class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,1245 RegisterClass Op1Class,1246 DAGOperand Op2Class,1247 string Constraint,1248 bit UsesVXRM_,1249 bits<2> TargetConstraintType = 1> :1250 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1251 (ins GetVRegNoV0<RetClass>.R:$passthru,1252 Op1Class:$rs2, Op2Class:$rs1,1253 VMaskOp:$vm, vec_rm:$rm, AVL:$vl,1254 sew:$sew, vec_policy:$policy)> {1255 let mayLoad = 0;1256 let mayStore = 0;1257 let hasSideEffects = 0;1258 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1259 let TargetOverlapConstraintType = TargetConstraintType;1260 let HasVLOp = 1;1261 let HasSEWOp = 1;1262 let HasVecPolicyOp = 1;1263 let UsesMaskPolicy = 1;1264 let HasRoundModeOp = 1;1265 let UsesVXRM = UsesVXRM_;1266 let hasPostISelHook = !not(UsesVXRM_);1267 let IncludeInInversePseudoTable = 0;1268}1269 1270// Special version of VPseudoBinaryNoMask where we pretend the first source is1271// tied to the destination.1272// This allows maskedoff and rs2 to be the same register.1273class VPseudoTiedBinaryNoMask<VReg RetClass,1274 DAGOperand Op2Class,1275 string Constraint,1276 bits<2> TargetConstraintType = 1> :1277 RISCVVPseudo<(outs RetClass:$rd),1278 (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew,1279 vec_policy:$policy)> {1280 let mayLoad = 0;1281 let mayStore = 0;1282 let hasSideEffects = 0;1283 let Constraints = !interleave([Constraint, "$rd = $rs2"], ",");1284 let TargetOverlapConstraintType = TargetConstraintType;1285 let HasVLOp = 1;1286 let HasSEWOp = 1;1287 let HasVecPolicyOp = 1;1288 let isConvertibleToThreeAddress = 1;1289 let IsTiedPseudo = 1;1290 let IncludeInInversePseudoTable = 0;1291}1292 1293class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,1294 DAGOperand Op2Class,1295 string Constraint,1296 bits<2> TargetConstraintType = 1> :1297 RISCVVPseudo<(outs RetClass:$rd),1298 (ins RetClass:$rs2, Op2Class:$rs1,1299 vec_rm:$rm,1300 AVL:$vl, sew:$sew,1301 vec_policy:$policy)> {1302 let mayLoad = 0;1303 let mayStore = 0;1304 let hasSideEffects = 0;1305 let Constraints = !interleave([Constraint, "$rd = $rs2"], ",");1306 let TargetOverlapConstraintType = TargetConstraintType;1307 let HasVLOp = 1;1308 let HasSEWOp = 1;1309 let HasVecPolicyOp = 1;1310 let isConvertibleToThreeAddress = 1;1311 let IsTiedPseudo = 1;1312 let HasRoundModeOp = 1;1313 let UsesVXRM = 0;1314 let hasPostISelHook = 1;1315 let IncludeInInversePseudoTable = 0;1316}1317 1318class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,1319 bit Ordered>:1320 RISCVVPseudo<(outs),1321 (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,1322 AVL:$vl, sew:$sew)>,1323 RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {1324 let mayLoad = 0;1325 let mayStore = 1;1326 let hasSideEffects = 0;1327 let HasVLOp = 1;1328 let HasSEWOp = 1;1329}1330 1331class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,1332 bit Ordered>:1333 RISCVVPseudo<(outs),1334 (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,1335 VMaskOp:$vm, AVL:$vl, sew:$sew)>,1336 RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {1337 let mayLoad = 0;1338 let mayStore = 1;1339 let hasSideEffects = 0;1340 let HasVLOp = 1;1341 let HasSEWOp = 1;1342 let IncludeInInversePseudoTable = 0;1343}1344 1345class VPseudoBinaryMaskPolicy<VReg RetClass,1346 RegisterClass Op1Class,1347 DAGOperand Op2Class,1348 string Constraint,1349 bits<2> TargetConstraintType = 1> :1350 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1351 (ins GetVRegNoV0<RetClass>.R:$passthru,1352 Op1Class:$rs2, Op2Class:$rs1,1353 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {1354 let mayLoad = 0;1355 let mayStore = 0;1356 let hasSideEffects = 0;1357 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1358 let TargetOverlapConstraintType = TargetConstraintType;1359 let HasVLOp = 1;1360 let HasSEWOp = 1;1361 let HasVecPolicyOp = 1;1362 let UsesMaskPolicy = 1;1363 let IncludeInInversePseudoTable = 0;1364}1365 1366class VPseudoTernaryMaskPolicy<VReg RetClass,1367 RegisterClass Op1Class,1368 DAGOperand Op2Class> :1369 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1370 (ins GetVRegNoV0<RetClass>.R:$passthru,1371 Op1Class:$rs2, Op2Class:$rs1,1372 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {1373 let mayLoad = 0;1374 let mayStore = 0;1375 let hasSideEffects = 0;1376 let Constraints = "$rd = $passthru";1377 let HasVLOp = 1;1378 let HasSEWOp = 1;1379 let HasVecPolicyOp = 1;1380 let IncludeInInversePseudoTable = 0;1381}1382 1383class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,1384 RegisterClass Op1Class,1385 DAGOperand Op2Class> :1386 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1387 (ins GetVRegNoV0<RetClass>.R:$passthru,1388 Op1Class:$rs2, Op2Class:$rs1,1389 VMaskOp:$vm,1390 vec_rm:$rm,1391 AVL:$vl, sew:$sew, vec_policy:$policy)> {1392 let mayLoad = 0;1393 let mayStore = 0;1394 let hasSideEffects = 0;1395 let Constraints = "$rd = $passthru";1396 let HasVLOp = 1;1397 let HasSEWOp = 1;1398 let HasVecPolicyOp = 1;1399 let HasRoundModeOp = 1;1400 let UsesVXRM = 0;1401 let hasPostISelHook = 1;1402 let IncludeInInversePseudoTable = 0;1403}1404 1405// Like VPseudoBinaryMaskPolicy, but output can be V0.1406class VPseudoBinaryMOutMask<VReg RetClass,1407 RegisterClass Op1Class,1408 DAGOperand Op2Class,1409 string Constraint,1410 bits<2> TargetConstraintType = 1> :1411 RISCVVPseudo<(outs RetClass:$rd),1412 (ins RetClass:$passthru,1413 Op1Class:$rs2, Op2Class:$rs1,1414 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {1415 let mayLoad = 0;1416 let mayStore = 0;1417 let hasSideEffects = 0;1418 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1419 let TargetOverlapConstraintType = TargetConstraintType;1420 let HasVLOp = 1;1421 let HasSEWOp = 1;1422 let HasVecPolicyOp = 1;1423 let UsesMaskPolicy = 1;1424 let IncludeInInversePseudoTable = 0;1425}1426 1427// Special version of VPseudoBinaryMaskPolicy where we pretend the first source1428// is tied to the destination so we can workaround the earlyclobber constraint.1429// This allows maskedoff and rs2 to be the same register.1430class VPseudoTiedBinaryMask<VReg RetClass,1431 DAGOperand Op2Class,1432 string Constraint,1433 bits<2> TargetConstraintType = 1> :1434 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1435 (ins GetVRegNoV0<RetClass>.R:$passthru,1436 Op2Class:$rs1,1437 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy)> {1438 let mayLoad = 0;1439 let mayStore = 0;1440 let hasSideEffects = 0;1441 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1442 let TargetOverlapConstraintType = TargetConstraintType;1443 let HasVLOp = 1;1444 let HasSEWOp = 1;1445 let HasVecPolicyOp = 1;1446 let UsesMaskPolicy = 1;1447 let IsTiedPseudo = 1;1448 let IncludeInInversePseudoTable = 0;1449}1450 1451class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,1452 DAGOperand Op2Class,1453 string Constraint,1454 bits<2> TargetConstraintType = 1> :1455 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1456 (ins GetVRegNoV0<RetClass>.R:$passthru,1457 Op2Class:$rs1,1458 VMaskOp:$vm,1459 vec_rm:$rm,1460 AVL:$vl, sew:$sew, vec_policy:$policy)> {1461 let mayLoad = 0;1462 let mayStore = 0;1463 let hasSideEffects = 0;1464 let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");1465 let TargetOverlapConstraintType = TargetConstraintType;1466 let HasVLOp = 1;1467 let HasSEWOp = 1;1468 let HasVecPolicyOp = 1;1469 let UsesMaskPolicy = 1;1470 let IsTiedPseudo = 1;1471 let HasRoundModeOp = 1;1472 let UsesVXRM = 0;1473 let hasPostISelHook = 1;1474 let IncludeInInversePseudoTable = 0;1475}1476 1477class VPseudoBinaryCarry<VReg RetClass,1478 VReg Op1Class,1479 DAGOperand Op2Class,1480 LMULInfo MInfo,1481 bit CarryIn,1482 string Constraint,1483 bits<2> TargetConstraintType = 1> :1484 RISCVVPseudo<(outs RetClass:$rd),1485 !if(CarryIn,1486 (ins Op1Class:$rs2, Op2Class:$rs1,1487 VMV0:$carry, AVL:$vl, sew:$sew),1488 (ins Op1Class:$rs2, Op2Class:$rs1,1489 AVL:$vl, sew:$sew))> {1490 let mayLoad = 0;1491 let mayStore = 0;1492 let hasSideEffects = 0;1493 let Constraints = Constraint;1494 let TargetOverlapConstraintType = TargetConstraintType;1495 let HasVLOp = 1;1496 let HasSEWOp = 1;1497 let VLMul = MInfo.value;1498}1499 1500class VPseudoTiedBinaryCarryIn<VReg RetClass,1501 VReg Op1Class,1502 DAGOperand Op2Class,1503 LMULInfo MInfo,1504 bits<2> TargetConstraintType = 1> :1505 RISCVVPseudo<(outs RetClass:$rd),1506 (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,1507 VMV0:$carry, AVL:$vl, sew:$sew)> {1508 let mayLoad = 0;1509 let mayStore = 0;1510 let hasSideEffects = 0;1511 let Constraints = "$rd = $passthru";1512 let TargetOverlapConstraintType = TargetConstraintType;1513 let HasVLOp = 1;1514 let HasSEWOp = 1;1515 let HasVecPolicyOp = 0;1516 let VLMul = MInfo.value;1517}1518 1519class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,1520 RegisterClass Op1Class,1521 DAGOperand Op2Class,1522 string Constraint = "",1523 bits<2> TargetConstraintType = 1> :1524 RISCVVPseudo<(outs RetClass:$rd),1525 (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,1526 AVL:$vl, sew:$sew, vec_policy:$policy)> {1527 let mayLoad = 0;1528 let mayStore = 0;1529 let hasSideEffects = 0;1530 let Constraints = !interleave([Constraint, "$rd = $rs3"], ",");1531 let TargetOverlapConstraintType = TargetConstraintType;1532 let HasVecPolicyOp = 1;1533 let HasVLOp = 1;1534 let HasSEWOp = 1;1535}1536 1537class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,1538 RegisterClass Op1Class,1539 DAGOperand Op2Class,1540 string Constraint = "",1541 bits<2> TargetConstraintType = 1> :1542 RISCVVPseudo<(outs RetClass:$rd),1543 (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,1544 vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy)> {1545 let mayLoad = 0;1546 let mayStore = 0;1547 let hasSideEffects = 0;1548 let Constraints = !interleave([Constraint, "$rd = $rs3"], ",");1549 let TargetOverlapConstraintType = TargetConstraintType;1550 let HasVecPolicyOp = 1;1551 let HasVLOp = 1;1552 let HasSEWOp = 1;1553 let HasRoundModeOp = 1;1554 let UsesVXRM = 0;1555 let hasPostISelHook = 1;1556}1557 1558class VPseudoUSSegLoadNoMask<VReg RetClass,1559 int EEW,1560 bits<4> NF> :1561 RISCVVPseudo<(outs RetClass:$rd),1562 (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,1563 sew:$sew, vec_policy:$policy)>,1564 RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {1565 let mayLoad = 1;1566 let mayStore = 0;1567 let hasSideEffects = 0;1568 let HasVLOp = 1;1569 let HasSEWOp = 1;1570 let HasVecPolicyOp = 1;1571 let Constraints = "$rd = $dest";1572}1573 1574class VPseudoUSSegLoadMask<VReg RetClass,1575 int EEW,1576 bits<4> NF> :1577 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1578 (ins GetVRegNoV0<RetClass>.R:$passthru,1579 GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew,1580 vec_policy:$policy)>,1581 RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {1582 let mayLoad = 1;1583 let mayStore = 0;1584 let hasSideEffects = 0;1585 let Constraints = "$rd = $passthru";1586 let HasVLOp = 1;1587 let HasSEWOp = 1;1588 let HasVecPolicyOp = 1;1589 let UsesMaskPolicy = 1;1590 let IncludeInInversePseudoTable = 0;1591}1592 1593class VPseudoUSSegLoadFFNoMask<VReg RetClass,1594 int EEW,1595 bits<4> NF> :1596 RISCVVPseudo<(outs RetClass:$rd, GPR:$vl),1597 (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,1598 sew:$sew, vec_policy:$policy)>,1599 RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {1600 let mayLoad = 1;1601 let mayStore = 0;1602 let hasSideEffects = 0;1603 let HasVLOp = 1;1604 let HasSEWOp = 1;1605 let HasVecPolicyOp = 1;1606 let Constraints = "$rd = $dest";1607}1608 1609class VPseudoUSSegLoadFFMask<VReg RetClass,1610 int EEW,1611 bits<4> NF> :1612 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),1613 (ins GetVRegNoV0<RetClass>.R:$passthru,1614 GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew,1615 vec_policy:$policy)>,1616 RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {1617 let mayLoad = 1;1618 let mayStore = 0;1619 let hasSideEffects = 0;1620 let Constraints = "$rd = $passthru";1621 let HasVLOp = 1;1622 let HasSEWOp = 1;1623 let HasVecPolicyOp = 1;1624 let UsesMaskPolicy = 1;1625 let IncludeInInversePseudoTable = 0;1626}1627 1628class VPseudoSSegLoadNoMask<VReg RetClass,1629 int EEW,1630 bits<4> NF> :1631 RISCVVPseudo<(outs RetClass:$rd),1632 (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset,1633 AVL:$vl, sew:$sew, vec_policy:$policy)>,1634 RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {1635 let mayLoad = 1;1636 let mayStore = 0;1637 let hasSideEffects = 0;1638 let HasVLOp = 1;1639 let HasSEWOp = 1;1640 let HasVecPolicyOp = 1;1641 let Constraints = "$rd = $passthru";1642}1643 1644class VPseudoSSegLoadMask<VReg RetClass,1645 int EEW,1646 bits<4> NF> :1647 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1648 (ins GetVRegNoV0<RetClass>.R:$passthru,1649 GPRMemZeroOffset:$rs1, GPR:$offset, VMaskOp:$vm,1650 AVL:$vl, sew:$sew, vec_policy:$policy)>,1651 RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {1652 let mayLoad = 1;1653 let mayStore = 0;1654 let hasSideEffects = 0;1655 let Constraints = "$rd = $passthru";1656 let HasVLOp = 1;1657 let HasSEWOp = 1;1658 let HasVecPolicyOp = 1;1659 let UsesMaskPolicy = 1;1660 let IncludeInInversePseudoTable = 0;1661}1662 1663class VPseudoISegLoadNoMask<VReg RetClass,1664 VReg IdxClass,1665 int EEW,1666 bits<3> LMUL,1667 bits<4> NF,1668 bit Ordered> :1669 RISCVVPseudo<(outs RetClass:$rd),1670 (ins RetClass:$passthru, GPRMemZeroOffset:$rs1,1671 IdxClass:$offset, AVL:$vl, sew:$sew,1672 vec_policy:$policy)>,1673 RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {1674 let mayLoad = 1;1675 let mayStore = 0;1676 let hasSideEffects = 0;1677 // For vector indexed segment loads, the destination vector register groups1678 // cannot overlap the source vector register group1679 let Constraints = "@earlyclobber $rd, $rd = $passthru";1680 let HasVLOp = 1;1681 let HasSEWOp = 1;1682 let HasVecPolicyOp = 1;1683}1684 1685class VPseudoISegLoadMask<VReg RetClass,1686 VReg IdxClass,1687 int EEW,1688 bits<3> LMUL,1689 bits<4> NF,1690 bit Ordered> :1691 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),1692 (ins GetVRegNoV0<RetClass>.R:$passthru,1693 GPRMemZeroOffset:$rs1, IdxClass:$offset, VMaskOp:$vm,1694 AVL:$vl, sew:$sew, vec_policy:$policy)>,1695 RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {1696 let mayLoad = 1;1697 let mayStore = 0;1698 let hasSideEffects = 0;1699 // For vector indexed segment loads, the destination vector register groups1700 // cannot overlap the source vector register group1701 let Constraints = "@earlyclobber $rd, $rd = $passthru";1702 let HasVLOp = 1;1703 let HasSEWOp = 1;1704 let HasVecPolicyOp = 1;1705 let UsesMaskPolicy = 1;1706 let IncludeInInversePseudoTable = 0;1707}1708 1709class VPseudoUSSegStoreNoMask<VReg ValClass,1710 int EEW,1711 bits<4> NF> :1712 RISCVVPseudo<(outs),1713 (ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl,1714 sew:$sew)>,1715 RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {1716 let mayLoad = 0;1717 let mayStore = 1;1718 let hasSideEffects = 0;1719 let HasVLOp = 1;1720 let HasSEWOp = 1;1721}1722 1723class VPseudoUSSegStoreMask<VReg ValClass,1724 int EEW,1725 bits<4> NF> :1726 RISCVVPseudo<(outs),1727 (ins ValClass:$rd, GPRMemZeroOffset:$rs1,1728 VMaskOp:$vm, AVL:$vl, sew:$sew)>,1729 RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {1730 let mayLoad = 0;1731 let mayStore = 1;1732 let hasSideEffects = 0;1733 let HasVLOp = 1;1734 let HasSEWOp = 1;1735 let IncludeInInversePseudoTable = 0;1736}1737 1738class VPseudoSSegStoreNoMask<VReg ValClass,1739 int EEW,1740 bits<4> NF> :1741 RISCVVPseudo<(outs),1742 (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset,1743 AVL:$vl, sew:$sew)>,1744 RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {1745 let mayLoad = 0;1746 let mayStore = 1;1747 let hasSideEffects = 0;1748 let HasVLOp = 1;1749 let HasSEWOp = 1;1750}1751 1752class VPseudoSSegStoreMask<VReg ValClass,1753 int EEW,1754 bits<4> NF> :1755 RISCVVPseudo<(outs),1756 (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset,1757 VMaskOp:$vm, AVL:$vl, sew:$sew)>,1758 RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {1759 let mayLoad = 0;1760 let mayStore = 1;1761 let hasSideEffects = 0;1762 let HasVLOp = 1;1763 let HasSEWOp = 1;1764 let IncludeInInversePseudoTable = 0;1765}1766 1767class VPseudoISegStoreNoMask<VReg ValClass,1768 VReg IdxClass,1769 int EEW,1770 bits<3> LMUL,1771 bits<4> NF,1772 bit Ordered> :1773 RISCVVPseudo<(outs),1774 (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,1775 AVL:$vl, sew:$sew)>,1776 RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {1777 let mayLoad = 0;1778 let mayStore = 1;1779 let hasSideEffects = 0;1780 let HasVLOp = 1;1781 let HasSEWOp = 1;1782}1783 1784class VPseudoISegStoreMask<VReg ValClass,1785 VReg IdxClass,1786 int EEW,1787 bits<3> LMUL,1788 bits<4> NF,1789 bit Ordered> :1790 RISCVVPseudo<(outs),1791 (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,1792 VMaskOp:$vm, AVL:$vl, sew:$sew)>,1793 RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {1794 let mayLoad = 0;1795 let mayStore = 1;1796 let hasSideEffects = 0;1797 let HasVLOp = 1;1798 let HasSEWOp = 1;1799 let IncludeInInversePseudoTable = 0;1800}1801 1802multiclass VPseudoUSLoad {1803 foreach eew = EEWList in {1804 foreach lmul = MxSet<eew>.m in {1805 defvar LInfo = lmul.MX;1806 defvar vreg = lmul.vrclass;1807 let VLMul = lmul.value, SEW=eew in {1808 def "E" # eew # "_V_" # LInfo :1809 VPseudoUSLoadNoMask<vreg, eew>,1810 VLESched<LInfo>;1811 def "E" # eew # "_V_" # LInfo # "_MASK" :1812 VPseudoUSLoadMask<vreg, eew>,1813 RISCVMaskedPseudo<MaskIdx=2>,1814 VLESched<LInfo>;1815 }1816 }1817 }1818}1819 1820multiclass VPseudoFFLoad {1821 foreach eew = EEWList in {1822 foreach lmul = MxSet<eew>.m in {1823 defvar LInfo = lmul.MX;1824 defvar vreg = lmul.vrclass;1825 let VLMul = lmul.value, SEW=eew in {1826 def "E" # eew # "FF_V_" # LInfo:1827 VPseudoUSLoadFFNoMask<vreg, eew>,1828 VLFSched<LInfo>;1829 def "E" # eew # "FF_V_" # LInfo # "_MASK":1830 VPseudoUSLoadFFMask<vreg, eew>,1831 RISCVMaskedPseudo<MaskIdx=2>,1832 VLFSched<LInfo>;1833 }1834 }1835 }1836}1837 1838multiclass VPseudoLoadMask {1839 foreach mti = AllMasks in {1840 defvar mx = mti.LMul.MX;1841 defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);1842 let VLMul = mti.LMul.value in {1843 def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1, sewop=sew_mask>,1844 Sched<[WriteVLDM_MX, ReadVLDX]>;1845 }1846 }1847}1848 1849multiclass VPseudoSLoad {1850 foreach eew = EEWList in {1851 foreach lmul = MxSet<eew>.m in {1852 defvar LInfo = lmul.MX;1853 defvar vreg = lmul.vrclass;1854 let VLMul = lmul.value, SEW=eew in {1855 def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>,1856 VLSSched<eew, LInfo>;1857 def "E" # eew # "_V_" # LInfo # "_MASK" :1858 VPseudoSLoadMask<vreg, eew>,1859 RISCVMaskedPseudo<MaskIdx=3>,1860 VLSSched<eew, LInfo>;1861 }1862 }1863 }1864}1865 1866multiclass VPseudoILoad<bit Ordered> {1867 foreach idxEEW = EEWList in {1868 foreach dataEEW = EEWList in {1869 foreach dataEMUL = MxSet<dataEEW>.m in {1870 defvar dataEMULOctuple = dataEMUL.octuple;1871 // Calculate emul = eew * lmul / sew1872 defvar idxEMULOctuple =1873 !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));1874 if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {1875 defvar DataLInfo = dataEMUL.MX;1876 defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;1877 defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);1878 defvar Vreg = dataEMUL.vrclass;1879 defvar IdxVreg = idxEMUL.vrclass;1880 defvar HasConstraint = !ne(dataEEW, idxEEW);1881 defvar TypeConstraints = 1882 !if(!eq(dataEEW, idxEEW), 1, !if(!gt(dataEEW, idxEEW), !if(!ge(idxEMULOctuple, 8), 3, 1), 2));1883 let VLMul = dataEMUL.value in {1884 def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :1885 VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,1886 VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;1887 def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :1888 VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,1889 RISCVMaskedPseudo<MaskIdx=3>,1890 VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;1891 }1892 }1893 }1894 }1895 }1896}1897 1898multiclass VPseudoUSStore {1899 foreach eew = EEWList in {1900 foreach lmul = MxSet<eew>.m in {1901 defvar LInfo = lmul.MX;1902 defvar vreg = lmul.vrclass;1903 let VLMul = lmul.value, SEW=eew in {1904 def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,1905 VSESched<LInfo>;1906 def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,1907 RISCVMaskedPseudo<MaskIdx=2>,1908 VSESched<LInfo>;1909 }1910 }1911 }1912}1913 1914multiclass VPseudoStoreMask {1915 foreach mti = AllMasks in {1916 defvar mx = mti.LMul.MX;1917 defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);1918 let VLMul = mti.LMul.value in {1919 def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1, sewop=sew_mask>,1920 Sched<[WriteVSTM_MX, ReadVSTX]>;1921 }1922 }1923}1924 1925multiclass VPseudoSStore {1926 foreach eew = EEWList in {1927 foreach lmul = MxSet<eew>.m in {1928 defvar LInfo = lmul.MX;1929 defvar vreg = lmul.vrclass;1930 let VLMul = lmul.value, SEW=eew in {1931 def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,1932 VSSSched<eew, LInfo>;1933 def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,1934 RISCVMaskedPseudo<MaskIdx=3>,1935 VSSSched<eew, LInfo>;1936 }1937 }1938 }1939}1940 1941multiclass VPseudoIStore<bit Ordered> {1942 foreach idxEEW = EEWList in {1943 foreach dataEEW = EEWList in {1944 foreach dataEMUL = MxSet<dataEEW>.m in {1945 defvar dataEMULOctuple = dataEMUL.octuple;1946 // Calculate emul = eew * lmul / sew1947 defvar idxEMULOctuple =1948 !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));1949 if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {1950 defvar DataLInfo = dataEMUL.MX;1951 defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;1952 defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);1953 defvar Vreg = dataEMUL.vrclass;1954 defvar IdxVreg = idxEMUL.vrclass;1955 let VLMul = dataEMUL.value in {1956 def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :1957 VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,1958 VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;1959 def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :1960 VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,1961 RISCVMaskedPseudo<MaskIdx=3>,1962 VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;1963 }1964 }1965 }1966 }1967 }1968}1969 1970multiclass VPseudoVPOP_M {1971 foreach mti = AllMasks in {1972 defvar mx = mti.LMul.MX;1973 let VLMul = mti.LMul.value in {1974 def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut,1975 SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;1976 def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,1977 RISCVMaskedPseudo<MaskIdx=1>,1978 SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;1979 }1980 }1981}1982 1983multiclass VPseudoV1ST_M {1984 foreach mti = AllMasks in {1985 defvar mx = mti.LMul.MX;1986 let VLMul = mti.LMul.value in {1987 def "_M_" #mti.BX : VPseudoUnaryNoMaskGPROut,1988 SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;1989 def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,1990 RISCVMaskedPseudo<MaskIdx=1>,1991 SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;1992 }1993 }1994}1995 1996multiclass VPseudoVSFS_M {1997 defvar constraint = "@earlyclobber $rd";1998 foreach mti = AllMasks in {1999 defvar mx = mti.LMul.MX;2000 let VLMul = mti.LMul.value in {2001 def "_M_" # mti.BX : VPseudoUnaryNoMaskNoPolicy<VR, VR, constraint>,2002 SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,2003 forcePassthruRead=true>;2004 def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint,2005 sewop = sew_mask>,2006 SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,2007 forcePassthruRead=true>;2008 }2009 }2010}2011 2012multiclass VPseudoVID_V {2013 foreach m = MxList in {2014 defvar mx = m.MX;2015 let VLMul = m.value in {2016 def "_V_" # mx : VPseudoNullaryNoMask<m.vrclass>,2017 SchedNullary<"WriteVIdxV", mx, forcePassthruRead=true>;2018 def "_V_" # mx # "_MASK" : VPseudoNullaryMask<m.vrclass>,2019 RISCVMaskedPseudo<MaskIdx=1>,2020 SchedNullary<"WriteVIdxV", mx,2021 forcePassthruRead=true>;2022 }2023 }2024}2025 2026multiclass VPseudoNullaryPseudoM <string BaseInst> {2027 foreach mti = AllMasks in {2028 let VLMul = mti.LMul.value in {2029 def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">,2030 SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mti.LMul.MX>;2031 }2032 }2033}2034 2035multiclass VPseudoVIOTA_M {2036 defvar constraint = "@earlyclobber $rd";2037 foreach m = MxList in {2038 defvar mx = m.MX;2039 let VLMul = m.value in {2040 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,2041 SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,2042 forcePassthruRead=true>;2043 def "_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,2044 RISCVMaskedPseudo<MaskIdx=2>,2045 SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,2046 forcePassthruRead=true>;2047 }2048 }2049}2050 2051multiclass VPseudoVCPR_V {2052 foreach m = MxList in {2053 defvar mx = m.MX;2054 defvar sews = SchedSEWSet<mx>.val;2055 let VLMul = m.value in2056 foreach e = sews in {2057 defvar suffix = "_" # m.MX # "_E" # e;2058 let SEW = e in2059 def _VM # suffix2060 : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,2061 SchedBinary<"WriteVCompressV", "ReadVCompressV", "ReadVCompressV",2062 mx, e>;2063 }2064 }2065}2066 2067multiclass VPseudoBinary<VReg RetClass,2068 VReg Op1Class,2069 DAGOperand Op2Class,2070 LMULInfo MInfo,2071 string Constraint = "",2072 int sew = 0,2073 bits<2> TargetConstraintType = 1,2074 bit Commutable = 0> {2075 let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {2076 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);2077 def suffix : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,2078 Constraint, TargetConstraintType>;2079 def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,2080 Constraint, TargetConstraintType>,2081 RISCVMaskedPseudo<MaskIdx=3>;2082 }2083}2084 2085multiclass VPseudoBinaryRoundingMode<VReg RetClass,2086 VReg Op1Class,2087 DAGOperand Op2Class,2088 LMULInfo MInfo,2089 string Constraint = "",2090 int sew = 0,2091 bit UsesVXRM = 1,2092 bits<2> TargetConstraintType = 1,2093 bit Commutable = 0> {2094 let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {2095 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);2096 def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,2097 Constraint, UsesVXRM,2098 TargetConstraintType>;2099 def suffix # "_MASK" : VPseudoBinaryMaskPolicyRoundingMode<RetClass,2100 Op1Class,2101 Op2Class,2102 Constraint,2103 UsesVXRM,2104 TargetConstraintType>,2105 RISCVMaskedPseudo<MaskIdx=3>;2106 }2107}2108 2109 2110multiclass VPseudoBinaryEmul<VReg RetClass,2111 VReg Op1Class,2112 DAGOperand Op2Class,2113 LMULInfo lmul,2114 LMULInfo emul,2115 string Constraint = "",2116 int sew> {2117 let VLMul = lmul.value, SEW=sew in {2118 defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX);2119 def suffix # "_" # emul.MX : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,2120 Constraint>;2121 def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,2122 Constraint>,2123 RISCVMaskedPseudo<MaskIdx=3>;2124 }2125}2126 2127multiclass VPseudoTiedBinary<VReg RetClass,2128 DAGOperand Op2Class,2129 LMULInfo MInfo,2130 string Constraint = "",2131 bits<2> TargetConstraintType = 1> {2132 let VLMul = MInfo.value in {2133 def "_" # MInfo.MX # "_TIED": VPseudoTiedBinaryNoMask<RetClass, Op2Class,2134 Constraint, TargetConstraintType>;2135 def "_" # MInfo.MX # "_MASK_TIED" : VPseudoTiedBinaryMask<RetClass, Op2Class,2136 Constraint, TargetConstraintType>,2137 RISCVMaskedPseudo<MaskIdx=2>;2138 }2139}2140 2141multiclass VPseudoTiedBinaryRoundingMode<VReg RetClass,2142 DAGOperand Op2Class,2143 LMULInfo MInfo,2144 string Constraint = "",2145 int sew = 0,2146 bits<2> TargetConstraintType = 1> {2147 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);2148 let VLMul = MInfo.value, SEW=sew in {2149 def suffix # "_TIED":2150 VPseudoTiedBinaryNoMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>;2151 def suffix # "_MASK_TIED" :2152 VPseudoTiedBinaryMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>,2153 RISCVMaskedPseudo<MaskIdx=2>;2154 }2155}2156 2157 2158multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0, bit Commutable = 0> {2159 defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew, Commutable=Commutable>;2160}2161 2162multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = "", bit Commutable = 0> {2163 defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint,2164 Commutable=Commutable>;2165}2166 2167multiclass VPseudoBinaryFV_VV_RM<LMULInfo m, int sew> {2168 defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,2169 "", sew, UsesVXRM=0>;2170}2171 2172multiclass VPseudoVGTR_EI16_VV {2173 defvar constraint = "@earlyclobber $rd";2174 foreach m = MxList in {2175 defvar mx = m.MX;2176 foreach sew = EEWList in {2177 defvar dataEMULOctuple = m.octuple;2178 // emul = lmul * 16 / sew2179 defvar idxEMULOctuple = !srl(!mul(dataEMULOctuple, 16), !logtwo(sew));2180 if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {2181 defvar emulMX = octuple_to_str<idxEMULOctuple>.ret;2182 defvar emul = !cast<LMULInfo>("V_" # emulMX);2183 defvar sews = SchedSEWSet<mx>.val;2184 foreach e = sews in {2185 defm _VV2186 : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul,2187 constraint, e>,2188 SchedBinary<"WriteVRGatherEI16VV", "ReadVRGatherEI16VV_data",2189 "ReadVRGatherEI16VV_index", mx, e, forcePassthruRead=true>;2190 }2191 }2192 }2193 }2194}2195 2196multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = "", int sew = 0> {2197 defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint, sew>;2198}2199 2200multiclass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> {2201 defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>;2202}2203 2204multiclass VPseudoVSLD1_VX<string Constraint = ""> {2205 foreach m = MxList in {2206 defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,2207 SchedBinary<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX",2208 m.MX, forcePassthruRead=true>;2209 }2210}2211 2212multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, int sew> {2213 defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass,2214 f.fprclass, m, "", sew>;2215}2216 2217multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, int sew> {2218 defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass,2219 f.fprclass, m, "", sew,2220 UsesVXRM=0>;2221}2222 2223multiclass VPseudoVSLD1_VF<string Constraint = ""> {2224 foreach f = FPList in {2225 foreach m = f.MxList in {2226 defm "_V" #f.FX2227 : VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,2228 SchedBinary<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX,2229 forcePassthruRead=true>;2230 }2231 }2232}2233 2234multiclass VPseudoBinaryV_VI<Operand ImmType, LMULInfo m, string Constraint = ""> {2235 defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;2236}2237 2238multiclass VPseudoBinaryV_VI_RM<Operand ImmType, LMULInfo m, string Constraint = ""> {2239 defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;2240}2241 2242multiclass VPseudoVALU_MM<bit Commutable = 0> {2243 foreach mti = AllMasks in {2244 let VLMul = mti.LMul.value, isCommutable = Commutable in {2245 def "_MM_" # mti.BX : VPseudoBinaryNoMask<VR, VR, VR, "", sewop = sew_mask>,2246 SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mti.LMul.MX>;2247 }2248 }2249}2250 2251// We use earlyclobber here due to2252// * The destination EEW is smaller than the source EEW and the overlap is2253// in the lowest-numbered part of the source register group is legal.2254// Otherwise, it is illegal.2255// * The destination EEW is greater than the source EEW, the source EMUL is2256// at least 1, and the overlap is in the highest-numbered part of the2257// destination register group is legal. Otherwise, it is illegal.2258multiclass VPseudoBinaryW_VV<LMULInfo m, bit Commutable = 0> {2259 defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,2260 "@earlyclobber $rd", TargetConstraintType=3,2261 Commutable=Commutable>;2262}2263 2264multiclass VPseudoBinaryW_VV_RM<LMULInfo m, int sew> {2265 defm _VV : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,2266 "@earlyclobber $rd", sew, UsesVXRM=0,2267 TargetConstraintType=3>;2268}2269 2270multiclass VPseudoBinaryW_VX<LMULInfo m> {2271 defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,2272 "@earlyclobber $rd", TargetConstraintType=3>;2273}2274 2275multiclass VPseudoBinaryW_VI<Operand ImmType, LMULInfo m> {2276 defm "_VI" : VPseudoBinary<m.wvrclass, m.vrclass, ImmType, m,2277 "@earlyclobber $rd", TargetConstraintType=3>;2278}2279 2280multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f, int sew> {2281 defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass,2282 f.fprclass, m,2283 "@earlyclobber $rd", sew,2284 UsesVXRM=0,2285 TargetConstraintType=3>;2286}2287 2288multiclass VPseudoBinaryW_WV<LMULInfo m> {2289 defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,2290 "@earlyclobber $rd", TargetConstraintType=3>;2291 defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m,2292 "@earlyclobber $rd", TargetConstraintType=3>;2293}2294 2295multiclass VPseudoBinaryW_WV_RM<LMULInfo m, int sew> {2296 defm _WV : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, m.vrclass, m,2297 "@earlyclobber $rd", sew, UsesVXRM = 0,2298 TargetConstraintType = 3>;2299 defm _WV : VPseudoTiedBinaryRoundingMode<m.wvrclass, m.vrclass, m,2300 "@earlyclobber $rd", sew,2301 TargetConstraintType = 3>;2302}2303 2304multiclass VPseudoBinaryW_WX<LMULInfo m> {2305 defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, /*Constraint*/ "", TargetConstraintType=3>;2306}2307 2308multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f, int sew> {2309 defm "_W" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass,2310 f.fprclass, m,2311 Constraint="",2312 sew=sew,2313 UsesVXRM=0,2314 TargetConstraintType=3>;2315}2316 2317// Narrowing instructions like vnsrl/vnsra/vnclip(u) don't need @earlyclobber2318// if the source and destination have an LMUL<=1. This matches this overlap2319// exception from the spec.2320// "The destination EEW is smaller than the source EEW and the overlap is in the2321// lowest-numbered part of the source register group."2322multiclass VPseudoBinaryV_WV<LMULInfo m> {2323 defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,2324 !if(!ge(m.octuple, 8), "@earlyclobber $rd", ""),2325 TargetConstraintType=2>;2326}2327 2328multiclass VPseudoBinaryV_WV_RM<LMULInfo m> {2329 defm _WV : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, m.vrclass, m,2330 !if(!ge(m.octuple, 8),2331 "@earlyclobber $rd", ""),2332 TargetConstraintType=2>;2333}2334 2335multiclass VPseudoBinaryV_WX<LMULInfo m> {2336 defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,2337 !if(!ge(m.octuple, 8), "@earlyclobber $rd", ""),2338 TargetConstraintType=2>;2339}2340 2341multiclass VPseudoBinaryV_WX_RM<LMULInfo m> {2342 defm _WX : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, GPR, m,2343 !if(!ge(m.octuple, 8),2344 "@earlyclobber $rd", ""),2345 TargetConstraintType=2>;2346}2347 2348multiclass VPseudoBinaryV_WI<LMULInfo m> {2349 defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,2350 !if(!ge(m.octuple, 8), "@earlyclobber $rd", ""),2351 TargetConstraintType=2>;2352}2353 2354multiclass VPseudoBinaryV_WI_RM<LMULInfo m> {2355 defm _WI : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, uimm5, m,2356 !if(!ge(m.octuple, 8),2357 "@earlyclobber $rd", ""),2358 TargetConstraintType=2>;2359}2360 2361// For vadc and vsbc, the instruction encoding is reserved if the destination2362// vector register is v0.2363// For vadc and vsbc, CarryIn == 1 and CarryOut == 02364multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,2365 string Constraint = "",2366 bit Commutable = 0,2367 bits<2> TargetConstraintType = 1> {2368 let isCommutable = Commutable in2369 def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :2370 VPseudoBinaryCarry<!if(CarryOut, VR,2371 !if(!and(CarryIn, !not(CarryOut)),2372 GetVRegNoV0<m.vrclass>.R, m.vrclass)),2373 m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>;2374}2375 2376multiclass VPseudoTiedBinaryV_VM<LMULInfo m, bit Commutable = 0> {2377 let isCommutable = Commutable in2378 def "_VVM" # "_" # m.MX:2379 VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,2380 m.vrclass, m.vrclass, m>;2381}2382 2383multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,2384 string Constraint = "", bits<2> TargetConstraintType = 1> {2385 def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :2386 VPseudoBinaryCarry<!if(CarryOut, VR,2387 !if(!and(CarryIn, !not(CarryOut)),2388 GetVRegNoV0<m.vrclass>.R, m.vrclass)),2389 m.vrclass, GPR, m, CarryIn, Constraint, TargetConstraintType>;2390}2391 2392multiclass VPseudoTiedBinaryV_XM<LMULInfo m> {2393 def "_VXM" # "_" # m.MX:2394 VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,2395 m.vrclass, GPR, m>;2396}2397 2398multiclass VPseudoVMRG_FM {2399 foreach f = FPList in {2400 foreach m = f.MxList in {2401 defvar mx = m.MX;2402 def "_V" # f.FX # "M_" # mx2403 : VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, m.vrclass,2404 f.fprclass, m>,2405 SchedBinary<"WriteVFMergeV", "ReadVFMergeV", "ReadVFMergeF", mx,2406 forceMasked=1, forcePassthruRead=true>;2407 }2408 }2409}2410 2411multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,2412 string Constraint = "", bits<2> TargetConstraintType = 1> {2413 def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :2414 VPseudoBinaryCarry<!if(CarryOut, VR,2415 !if(!and(CarryIn, !not(CarryOut)),2416 GetVRegNoV0<m.vrclass>.R, m.vrclass)),2417 m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>;2418}2419 2420multiclass VPseudoTiedBinaryV_IM<LMULInfo m> {2421 def "_VIM" # "_" # m.MX:2422 VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,2423 m.vrclass, simm5, m>;2424}2425 2426multiclass VPseudoUnaryVMV_V_X_I {2427 foreach m = MxList in {2428 let VLMul = m.value in {2429 defvar mx = m.MX;2430 let VLMul = m.value in {2431 def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,2432 SchedUnary<"WriteVIMovV", "ReadVIMovV", mx,2433 forcePassthruRead=true>;2434 let isReMaterializable = 1 in2435 def "_X_" # mx : VPseudoUnaryNoMask<m.vrclass, GPR>,2436 SchedUnary<"WriteVIMovX", "ReadVIMovX", mx,2437 forcePassthruRead=true>;2438 let isReMaterializable = 1 in2439 def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>,2440 SchedNullary<"WriteVIMovI", mx,2441 forcePassthruRead=true>;2442 }2443 }2444 }2445}2446 2447multiclass VPseudoVMV_F {2448 foreach f = FPList in {2449 foreach m = f.MxList in {2450 defvar mx = m.MX;2451 let VLMul = m.value in {2452 def "_" # f.FX # "_" # mx :2453 VPseudoUnaryNoMask<m.vrclass, f.fprclass>,2454 SchedUnary<"WriteVFMovV", "ReadVFMovF", mx, forcePassthruRead=true>;2455 }2456 }2457 }2458}2459 2460multiclass VPseudoVCLS_V {2461 foreach m = MxListF in {2462 defvar mx = m.MX;2463 let VLMul = m.value in {2464 def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,2465 SchedUnary<"WriteVFClassV", "ReadVFClassV", mx,2466 forcePassthruRead=true>;2467 def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,2468 RISCVMaskedPseudo<MaskIdx=2>,2469 SchedUnary<"WriteVFClassV", "ReadVFClassV", mx,2470 forcePassthruRead=true>;2471 }2472 }2473}2474 2475multiclass VPseudoVSQR_V_RM {2476 foreach m = MxListF in {2477 defvar mx = m.MX;2478 defvar sews = SchedSEWSet<m.MX, isF=1>.val;2479 2480 let VLMul = m.value in2481 foreach e = sews in {2482 defvar suffix = "_" # mx # "_E" # e;2483 let SEW = e in {2484 def "_V" # suffix : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,2485 SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e,2486 forcePassthruRead=true>;2487 def "_V" #suffix # "_MASK"2488 : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,2489 RISCVMaskedPseudo<MaskIdx = 2>,2490 SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e,2491 forcePassthruRead=true>;2492 }2493 }2494 }2495}2496 2497multiclass VPseudoVRCP_V {2498 foreach m = MxListF in {2499 defvar mx = m.MX;2500 foreach e = SchedSEWSet<mx, isF=1>.val in {2501 let VLMul = m.value in {2502 def "_V_" # mx # "_E" # e2503 : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,2504 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forcePassthruRead=true>;2505 def "_V_" # mx # "_E" # e # "_MASK"2506 : VPseudoUnaryMask<m.vrclass, m.vrclass>,2507 RISCVMaskedPseudo<MaskIdx = 2>,2508 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forcePassthruRead=true>;2509 }2510 }2511 }2512}2513 2514multiclass VPseudoVRCP_V_RM {2515 foreach m = MxListF in {2516 defvar mx = m.MX;2517 foreach e = SchedSEWSet<mx, isF=1>.val in {2518 let VLMul = m.value in {2519 def "_V_" # mx # "_E" # e2520 : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,2521 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forcePassthruRead=true>;2522 def "_V_" # mx # "_E" # e # "_MASK"2523 : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,2524 RISCVMaskedPseudo<MaskIdx = 2>,2525 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forcePassthruRead=true>;2526 }2527 }2528 }2529}2530 2531multiclass PseudoVEXT_VF2 {2532 defvar constraints = "@earlyclobber $rd";2533 foreach m = MxListVF2 in {2534 defvar mx = m.MX;2535 defvar CurrTypeConstraints = !if(!or(!eq(mx, "MF4"), !eq(mx, "MF2"), !eq(mx, "M1")), 1, 3);2536 let VLMul = m.value in {2537 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints, CurrTypeConstraints>,2538 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forcePassthruRead=true>;2539 def "_" # mx # "_MASK" :2540 VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints, CurrTypeConstraints>,2541 RISCVMaskedPseudo<MaskIdx=2>,2542 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forcePassthruRead=true>;2543 }2544 }2545}2546 2547multiclass PseudoVEXT_VF4 {2548 defvar constraints = "@earlyclobber $rd";2549 foreach m = MxListVF4 in {2550 defvar mx = m.MX;2551 defvar CurrTypeConstraints = !if(!or(!eq(mx, "MF2"), !eq(mx, "M1"), !eq(mx, "M2")), 1, 3);2552 let VLMul = m.value in {2553 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints, CurrTypeConstraints>,2554 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forcePassthruRead=true>;2555 def "_" # mx # "_MASK" :2556 VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints, CurrTypeConstraints>,2557 RISCVMaskedPseudo<MaskIdx=2>,2558 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forcePassthruRead=true>;2559 }2560 }2561}2562 2563multiclass PseudoVEXT_VF8 {2564 defvar constraints = "@earlyclobber $rd";2565 foreach m = MxListVF8 in {2566 defvar mx = m.MX;2567 defvar CurrTypeConstraints = !if(!or(!eq(mx, "M1"), !eq(mx, "M2"), !eq(mx, "M4")), 1, 3);2568 let VLMul = m.value in {2569 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints, CurrTypeConstraints>,2570 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forcePassthruRead=true>;2571 def "_" # mx # "_MASK" :2572 VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints, CurrTypeConstraints>,2573 RISCVMaskedPseudo<MaskIdx=2>,2574 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forcePassthruRead=true>;2575 }2576 }2577}2578 2579// The destination EEW is 1 since "For the purposes of register group overlap2580// constraints, mask elements have EEW=1."2581// The source EEW is 8, 16, 32, or 64.2582// When the destination EEW is different from source EEW, we need to use2583// @earlyclobber to avoid the overlap between destination and source registers.2584// We don't need @earlyclobber for LMUL<=1 since that matches this overlap2585// exception from the spec2586// "The destination EEW is smaller than the source EEW and the overlap is in the2587// lowest-numbered part of the source register group".2588// With LMUL<=1 the source and dest occupy a single register so any overlap2589// is in the lowest-numbered part.2590multiclass VPseudoBinaryM<DAGOperand Op2Class, LMULInfo m, bit Commutable = 0> {2591 let VLMul = m.value, isCommutable = Commutable in {2592 def "_" # m.MX :2593 VPseudoBinaryNoMask<VR, m.vrclass, Op2Class,2594 !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),2595 TargetConstraintType = 2>;2596 def "_" # m.MX # "_MASK" :2597 VPseudoBinaryMOutMask<VR, m.vrclass, Op2Class,2598 !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),2599 TargetConstraintType = 2>,2600 RISCVMaskedPseudo<MaskIdx=3>;2601 }2602}2603 2604multiclass VPseudoBinaryM_VV<LMULInfo m, bit Commutable = 0> {2605 defm _VV : VPseudoBinaryM<m.vrclass, m, Commutable=Commutable>;2606}2607 2608multiclass VPseudoBinaryM_VX<LMULInfo m> {2609 defm _VX : VPseudoBinaryM<GPR, m>;2610}2611 2612multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f> {2613 defm "_V" # f.FX : VPseudoBinaryM<f.fprclass, m>;2614}2615 2616multiclass VPseudoBinaryM_VI<LMULInfo m> {2617 defm _VI : VPseudoBinaryM<simm5, m>;2618}2619 2620multiclass VPseudoVGTR_VV_VX_VI {2621 defvar constraint = "@earlyclobber $rd";2622 foreach m = MxList in {2623 defvar mx = m.MX;2624 defm "" : VPseudoBinaryV_VX<m, constraint>,2625 SchedBinary<"WriteVRGatherVX", "ReadVRGatherVX_data",2626 "ReadVRGatherVX_index", mx, forcePassthruRead=true>;2627 defm "" : VPseudoBinaryV_VI<uimm5, m, constraint>,2628 SchedUnary<"WriteVRGatherVI", "ReadVRGatherVI_data", mx,2629 forcePassthruRead=true>;2630 2631 defvar sews = SchedSEWSet<mx>.val;2632 foreach e = sews in {2633 defm "" : VPseudoBinaryV_VV<m, constraint, e>,2634 SchedBinary<"WriteVRGatherVV", "ReadVRGatherVV_data",2635 "ReadVRGatherVV_index", mx, e, forcePassthruRead=true>;2636 }2637 }2638}2639 2640multiclass VPseudoVSALU_VV_VX_VI<bit Commutable = 0> {2641 foreach m = MxList in {2642 defvar mx = m.MX;2643 defm "" : VPseudoBinaryV_VV<m, Commutable=Commutable>,2644 SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx,2645 forcePassthruRead=true>;2646 defm "" : VPseudoBinaryV_VX<m>,2647 SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx,2648 forcePassthruRead=true>;2649 defm "" : VPseudoBinaryV_VI<simm5, m>,2650 SchedUnary<"WriteVSALUI", "ReadVSALUV", mx, forcePassthruRead=true>;2651 }2652}2653 2654 2655multiclass VPseudoVSHT_VV_VX_VI {2656 foreach m = MxList in {2657 defvar mx = m.MX;2658 defm "" : VPseudoBinaryV_VV<m>,2659 SchedBinary<"WriteVShiftV", "ReadVShiftV", "ReadVShiftV", mx,2660 forcePassthruRead=true>;2661 defm "" : VPseudoBinaryV_VX<m>,2662 SchedBinary<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX", mx,2663 forcePassthruRead=true>;2664 defm "" : VPseudoBinaryV_VI<uimm5, m>,2665 SchedUnary<"WriteVShiftI", "ReadVShiftV", mx, forcePassthruRead=true>;2666 }2667}2668 2669multiclass VPseudoVSSHT_VV_VX_VI_RM {2670 foreach m = MxList in {2671 defvar mx = m.MX;2672 defm "" : VPseudoBinaryV_VV_RM<m>,2673 SchedBinary<"WriteVSShiftV", "ReadVSShiftV", "ReadVSShiftV", mx,2674 forcePassthruRead=true>;2675 defm "" : VPseudoBinaryV_VX_RM<m>,2676 SchedBinary<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX", mx,2677 forcePassthruRead=true>;2678 defm "" : VPseudoBinaryV_VI_RM<uimm5, m>,2679 SchedUnary<"WriteVSShiftI", "ReadVSShiftV", mx, forcePassthruRead=true>;2680 }2681}2682 2683multiclass VPseudoVALU_VV_VX_VI<bit Commutable = 0> {2684 foreach m = MxList in {2685 defvar mx = m.MX;2686 defm "" : VPseudoBinaryV_VV<m, Commutable=Commutable>,2687 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,2688 forcePassthruRead=true>;2689 defm "" : VPseudoBinaryV_VX<m>,2690 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,2691 forcePassthruRead=true>;2692 defm "" : VPseudoBinaryV_VI<simm5, m>,2693 SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forcePassthruRead=true>;2694 }2695}2696 2697multiclass VPseudoVSALU_VV_VX {2698 foreach m = MxList in {2699 defvar mx = m.MX;2700 defm "" : VPseudoBinaryV_VV<m>,2701 SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUV", mx,2702 forcePassthruRead=true>;2703 defm "" : VPseudoBinaryV_VX<m>,2704 SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx,2705 forcePassthruRead=true>;2706 }2707}2708 2709multiclass VPseudoVSMUL_VV_VX_RM {2710 foreach m = MxList in {2711 defvar mx = m.MX;2712 defm "" : VPseudoBinaryV_VV_RM<m, Commutable=1>,2713 SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx,2714 forcePassthruRead=true>;2715 defm "" : VPseudoBinaryV_VX_RM<m>,2716 SchedBinary<"WriteVSMulX", "ReadVSMulV", "ReadVSMulX", mx,2717 forcePassthruRead=true>;2718 }2719}2720 2721multiclass VPseudoVAALU_VV_VX_RM<bit Commutable = 0> {2722 foreach m = MxList in {2723 defvar mx = m.MX;2724 defm "" : VPseudoBinaryV_VV_RM<m, Commutable=Commutable>,2725 SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx,2726 forcePassthruRead=true>;2727 defm "" : VPseudoBinaryV_VX_RM<m>,2728 SchedBinary<"WriteVAALUX", "ReadVAALUV", "ReadVAALUX", mx,2729 forcePassthruRead=true>;2730 }2731}2732 2733multiclass VPseudoVMINMAX_VV_VX {2734 foreach m = MxList in {2735 defvar mx = m.MX;2736 defm "" : VPseudoBinaryV_VV<m, Commutable=1>,2737 SchedBinary<"WriteVIMinMaxV", "ReadVIMinMaxV", "ReadVIMinMaxV", mx>;2738 defm "" : VPseudoBinaryV_VX<m>,2739 SchedBinary<"WriteVIMinMaxX", "ReadVIMinMaxV", "ReadVIMinMaxX", mx>;2740 }2741}2742 2743multiclass VPseudoVMUL_VV_VX<bit Commutable = 0> {2744 foreach m = MxList in {2745 defvar mx = m.MX;2746 defm "" : VPseudoBinaryV_VV<m, Commutable=Commutable>,2747 SchedBinary<"WriteVIMulV", "ReadVIMulV", "ReadVIMulV", mx>;2748 defm "" : VPseudoBinaryV_VX<m>,2749 SchedBinary<"WriteVIMulX", "ReadVIMulV", "ReadVIMulX", mx>;2750 }2751}2752 2753multiclass VPseudoVDIV_VV_VX {2754 foreach m = MxList in {2755 defvar mx = m.MX;2756 defvar sews = SchedSEWSet<mx>.val;2757 foreach e = sews in {2758 defm "" : VPseudoBinaryV_VV<m, "", e>,2759 SchedBinary<"WriteVIDivV", "ReadVIDivV", "ReadVIDivV", mx, e>;2760 defm "" : VPseudoBinaryV_VX<m, "", e>,2761 SchedBinary<"WriteVIDivX", "ReadVIDivV", "ReadVIDivX", mx, e>;2762 }2763 }2764}2765 2766multiclass VPseudoVFMUL_VV_VF_RM {2767 foreach m = MxListF in {2768 foreach e = SchedSEWSet<m.MX, isF=1>.val in2769 defm "" : VPseudoBinaryFV_VV_RM<m, e>,2770 SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX, e,2771 forcePassthruRead=true>;2772 }2773 2774 foreach f = FPList in {2775 foreach m = f.MxList in {2776 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,2777 SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX,2778 f.SEW, forcePassthruRead=true>;2779 }2780 }2781}2782 2783multiclass VPseudoVFDIV_VV_VF_RM {2784 foreach m = MxListF in {2785 defvar mx = m.MX;2786 defvar sews = SchedSEWSet<mx, isF=1>.val;2787 foreach e = sews in {2788 defm "" : VPseudoBinaryFV_VV_RM<m, e>,2789 SchedBinary<"WriteVFDivV", "ReadVFDivV", "ReadVFDivV", mx, e,2790 forcePassthruRead=true>;2791 }2792 }2793 2794 foreach f = FPList in {2795 foreach m = f.MxList in {2796 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,2797 SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW,2798 forcePassthruRead=true>;2799 }2800 }2801}2802 2803multiclass VPseudoVFRDIV_VF_RM {2804 foreach f = FPList in {2805 foreach m = f.MxList in {2806 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,2807 SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW,2808 forcePassthruRead=true>;2809 }2810 }2811}2812 2813multiclass VPseudoVALU_VV_VX {2814 foreach m = MxList in {2815 defm "" : VPseudoBinaryV_VV<m>,2816 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,2817 forcePassthruRead=true>;2818 defm "" : VPseudoBinaryV_VX<m>,2819 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX,2820 forcePassthruRead=true>;2821 }2822}2823 2824multiclass VPseudoVSGNJ_VV_VF {2825 foreach m = MxListF in {2826 foreach e = SchedSEWSet<m.MX, isF=1>.val in2827 defm "" : VPseudoBinaryV_VV<m, sew=e>,2828 SchedBinary<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV", m.MX,2829 e, forcePassthruRead=true>;2830 }2831 2832 foreach f = FPList in {2833 foreach m = f.MxList in {2834 defm "" : VPseudoBinaryV_VF<m, f, sew=f.SEW>,2835 SchedBinary<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF", m.MX,2836 f.SEW, forcePassthruRead=true>;2837 }2838 }2839}2840 2841multiclass VPseudoVMAX_VV_VF {2842 foreach m = MxListF in {2843 foreach e = SchedSEWSet<m.MX, isF=1>.val in2844 defm "" : VPseudoBinaryV_VV<m, sew=e>,2845 SchedBinary<"WriteVFMinMaxV", "ReadVFMinMaxV", "ReadVFMinMaxV",2846 m.MX, e, forcePassthruRead=true>;2847 }2848 2849 foreach f = FPList in {2850 foreach m = f.MxList in {2851 defm "" : VPseudoBinaryV_VF<m, f, sew=f.SEW>,2852 SchedBinary<"WriteVFMinMaxF", "ReadVFMinMaxV", "ReadVFMinMaxF",2853 m.MX, f.SEW, forcePassthruRead=true>;2854 }2855 }2856}2857 2858multiclass VPseudoVALU_VV_VF_RM {2859 foreach m = MxListF in {2860 foreach e = SchedSEWSet<m.MX, isF=1>.val in2861 defm "" : VPseudoBinaryFV_VV_RM<m, e>,2862 SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX, e,2863 forcePassthruRead=true>;2864 }2865 2866 foreach f = FPList in {2867 foreach m = f.MxList in {2868 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,2869 SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,2870 f.SEW, forcePassthruRead=true>;2871 }2872 }2873}2874 2875multiclass VPseudoVALU_VF_RM {2876 foreach f = FPList in {2877 foreach m = f.MxList in {2878 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,2879 SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,2880 f.SEW, forcePassthruRead=true>;2881 }2882 }2883}2884 2885multiclass VPseudoVALU_VX_VI {2886 foreach m = MxList in {2887 defvar mx = m.MX;2888 defm "" : VPseudoBinaryV_VX<m>,2889 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,2890 forcePassthruRead=true>;2891 defm "" : VPseudoBinaryV_VI<simm5, m>,2892 SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forcePassthruRead=true>;2893 }2894}2895 2896multiclass VPseudoVWALU_VV_VX<bit Commutable = 0> {2897 foreach m = MxListW in {2898 defvar mx = m.MX;2899 defm "" : VPseudoBinaryW_VV<m, Commutable=Commutable>,2900 SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx,2901 forcePassthruRead=true>;2902 defm "" : VPseudoBinaryW_VX<m>, 2903 SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx,2904 forcePassthruRead=true>;2905 }2906}2907 2908multiclass VPseudoVWMUL_VV_VX<bit Commutable = 0> {2909 foreach m = MxListW in {2910 defvar mx = m.MX;2911 defm "" : VPseudoBinaryW_VV<m, Commutable=Commutable>,2912 SchedBinary<"WriteVIWMulV", "ReadVIWMulV", "ReadVIWMulV", mx,2913 forcePassthruRead=true>;2914 defm "" : VPseudoBinaryW_VX<m>,2915 SchedBinary<"WriteVIWMulX", "ReadVIWMulV", "ReadVIWMulX", mx,2916 forcePassthruRead=true>;2917 }2918}2919 2920multiclass VPseudoVWMUL_VV_VF_RM {2921 foreach m = MxListFW in {2922 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in2923 defm "" : VPseudoBinaryW_VV_RM<m, sew=e>,2924 SchedBinary<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV", m.MX,2925 e, forcePassthruRead=true>;2926 }2927 2928 foreach f = FPListW in {2929 foreach m = f.MxListFW in {2930 defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,2931 SchedBinary<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF", m.MX,2932 f.SEW, forcePassthruRead=true>;2933 }2934 }2935}2936 2937multiclass VPseudoVWALU_WV_WX {2938 foreach m = MxListW in {2939 defvar mx = m.MX;2940 defm "" : VPseudoBinaryW_WV<m>,2941 SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx,2942 forcePassthruRead=true>;2943 defm "" : VPseudoBinaryW_WX<m>,2944 SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx,2945 forcePassthruRead=true>;2946 }2947}2948 2949multiclass VPseudoVFWALU_VV_VF_RM {2950 foreach m = MxListFW in {2951 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in2952 defm "" : VPseudoBinaryW_VV_RM<m, sew=e>,2953 SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,2954 e, forcePassthruRead=true>;2955 }2956 2957 foreach f = FPListW in {2958 foreach m = f.MxListFW in {2959 defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,2960 SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,2961 f.SEW, forcePassthruRead=true>;2962 }2963 }2964}2965 2966multiclass VPseudoVFWALU_WV_WF_RM {2967 foreach m = MxListFW in {2968 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in2969 defm "" : VPseudoBinaryW_WV_RM<m, sew=e>,2970 SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,2971 e, forcePassthruRead=true>;2972 }2973 foreach f = FPListW in {2974 foreach m = f.MxListFW in {2975 defm "" : VPseudoBinaryW_WF_RM<m, f, sew=f.SEW>,2976 SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,2977 f.SEW, forcePassthruRead=true>;2978 }2979 }2980}2981 2982multiclass VPseudoVMRG_VM_XM_IM {2983 foreach m = MxList in {2984 defvar mx = m.MX;2985 def "_VVM" # "_" # m.MX:2986 VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,2987 m.vrclass, m.vrclass, m>,2988 SchedBinary<"WriteVIMergeV", "ReadVIMergeV", "ReadVIMergeV", mx,2989 forcePassthruRead=true>;2990 def "_VXM" # "_" # m.MX:2991 VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,2992 m.vrclass, GPR, m>,2993 SchedBinary<"WriteVIMergeX", "ReadVIMergeV", "ReadVIMergeX", mx,2994 forcePassthruRead=true>;2995 def "_VIM" # "_" # m.MX:2996 VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,2997 m.vrclass, simm5, m>,2998 SchedUnary<"WriteVIMergeI", "ReadVIMergeV", mx,2999 forcePassthruRead=true>;3000 }3001}3002 3003multiclass VPseudoVCALU_VM_XM_IM {3004 foreach m = MxList in {3005 defvar mx = m.MX;3006 defm "" : VPseudoTiedBinaryV_VM<m, Commutable=1>,3007 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,3008 forcePassthruRead=true>;3009 defm "" : VPseudoTiedBinaryV_XM<m>,3010 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,3011 forcePassthruRead=true>;3012 defm "" : VPseudoTiedBinaryV_IM<m>,3013 SchedUnary<"WriteVICALUI", "ReadVICALUV", mx,3014 forcePassthruRead=true>;3015 }3016}3017 3018multiclass VPseudoVCALU_VM_XM {3019 foreach m = MxList in {3020 defvar mx = m.MX;3021 defm "" : VPseudoTiedBinaryV_VM<m>,3022 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,3023 forcePassthruRead=true>;3024 defm "" : VPseudoTiedBinaryV_XM<m>,3025 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,3026 forcePassthruRead=true>;3027 }3028}3029 3030multiclass VPseudoVCALUM_VM_XM_IM {3031 defvar constraint = "@earlyclobber $rd";3032 foreach m = MxList in {3033 defvar mx = m.MX;3034 defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,3035 Commutable=1, TargetConstraintType=2>,3036 SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,3037 forcePassthruRead=true>;3038 defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,3039 SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,3040 forcePassthruRead=true>;3041 defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,3042 SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx, forceMasked=1,3043 forcePassthruRead=true>;3044 }3045}3046 3047multiclass VPseudoVCALUM_VM_XM {3048 defvar constraint = "@earlyclobber $rd";3049 foreach m = MxList in {3050 defvar mx = m.MX;3051 defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,3052 TargetConstraintType=2>,3053 SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,3054 forcePassthruRead=true>;3055 defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint,3056 TargetConstraintType=2>,3057 SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,3058 forcePassthruRead=true>;3059 }3060}3061 3062multiclass VPseudoVCALUM_V_X_I {3063 defvar constraint = "@earlyclobber $rd";3064 foreach m = MxList in {3065 defvar mx = m.MX;3066 defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint,3067 Commutable=1, TargetConstraintType=2>,3068 SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,3069 forcePassthruRead=true>;3070 defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,3071 SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,3072 forcePassthruRead=true>;3073 defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=constraint>,3074 SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx,3075 forcePassthruRead=true>;3076 }3077}3078 3079multiclass VPseudoVCALUM_V_X {3080 defvar constraint = "@earlyclobber $rd";3081 foreach m = MxList in {3082 defvar mx = m.MX;3083 defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,3084 SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,3085 forcePassthruRead=true>;3086 defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,3087 SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,3088 forcePassthruRead=true>;3089 }3090}3091 3092multiclass VPseudoVNCLP_WV_WX_WI_RM {3093 foreach m = MxListW in {3094 defvar mx = m.MX;3095 defm "" : VPseudoBinaryV_WV_RM<m>,3096 SchedBinary<"WriteVNClipV", "ReadVNClipV", "ReadVNClipV", mx,3097 forcePassthruRead=true>;3098 defm "" : VPseudoBinaryV_WX_RM<m>,3099 SchedBinary<"WriteVNClipX", "ReadVNClipV", "ReadVNClipX", mx,3100 forcePassthruRead=true>;3101 defm "" : VPseudoBinaryV_WI_RM<m>,3102 SchedUnary<"WriteVNClipI", "ReadVNClipV", mx,3103 forcePassthruRead=true>;3104 }3105}3106 3107multiclass VPseudoVNSHT_WV_WX_WI {3108 foreach m = MxListW in {3109 defvar mx = m.MX;3110 defm "" : VPseudoBinaryV_WV<m>,3111 SchedBinary<"WriteVNShiftV", "ReadVNShiftV", "ReadVNShiftV", mx,3112 forcePassthruRead=true>;3113 defm "" : VPseudoBinaryV_WX<m>,3114 SchedBinary<"WriteVNShiftX", "ReadVNShiftV", "ReadVNShiftX", mx,3115 forcePassthruRead=true>;3116 defm "" : VPseudoBinaryV_WI<m>,3117 SchedUnary<"WriteVNShiftI", "ReadVNShiftV", mx,3118 forcePassthruRead=true>;3119 }3120}3121 3122multiclass VPseudoTernaryWithTailPolicy<VReg RetClass,3123 RegisterClass Op1Class,3124 DAGOperand Op2Class,3125 LMULInfo MInfo,3126 int sew> {3127 let VLMul = MInfo.value, SEW=sew in {3128 defvar mx = MInfo.MX;3129 def "_" # mx # "_E" # sew : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class>;3130 def "_" # mx # "_E" # sew # "_MASK" : VPseudoTernaryMaskPolicy<RetClass, Op1Class, Op2Class>,3131 RISCVMaskedPseudo<MaskIdx=3>;3132 }3133}3134 3135multiclass VPseudoTernaryWithTailPolicyRoundingMode<VReg RetClass,3136 RegisterClass Op1Class,3137 DAGOperand Op2Class,3138 LMULInfo MInfo,3139 int sew> {3140 let VLMul = MInfo.value, SEW=sew in {3141 defvar mx = MInfo.MX;3142 def "_" # mx # "_E" # sew3143 : VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,3144 Op2Class>;3145 def "_" # mx # "_E" # sew # "_MASK"3146 : VPseudoTernaryMaskPolicyRoundingMode<RetClass, Op1Class,3147 Op2Class>,3148 RISCVMaskedPseudo<MaskIdx=3>;3149 }3150}3151 3152multiclass VPseudoTernaryWithPolicy<VReg RetClass,3153 RegisterClass Op1Class,3154 DAGOperand Op2Class,3155 LMULInfo MInfo,3156 string Constraint = "",3157 bit Commutable = 0,3158 bits<2> TargetConstraintType = 1> {3159 let VLMul = MInfo.value in {3160 let isCommutable = Commutable in3161 def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>;3162 def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>,3163 RISCVMaskedPseudo<MaskIdx=3>;3164 }3165}3166 3167multiclass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass,3168 RegisterClass Op1Class,3169 DAGOperand Op2Class,3170 LMULInfo MInfo,3171 string Constraint = "",3172 int sew = 0,3173 bit Commutable = 0,3174 bits<2> TargetConstraintType = 1> {3175 let VLMul = MInfo.value in {3176 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);3177 let isCommutable = Commutable in3178 def suffix :3179 VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,3180 Op2Class, Constraint,3181 TargetConstraintType>;3182 def suffix # "_MASK" :3183 VPseudoBinaryMaskPolicyRoundingMode<RetClass, Op1Class,3184 Op2Class, Constraint,3185 UsesVXRM_=0,3186 TargetConstraintType=TargetConstraintType>,3187 RISCVMaskedPseudo<MaskIdx=3>;3188 }3189}3190 3191multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m> {3192 defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,3193 Commutable=1>;3194}3195 3196multiclass VPseudoTernaryV_VV_AAXA_RM<LMULInfo m, int sew> {3197 defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,3198 sew=sew, Commutable=1>;3199}3200 3201multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m> {3202 defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,3203 Commutable=1>;3204}3205 3206multiclass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f,3207 int sew> {3208 defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, f.fprclass,3209 m.vrclass, m,3210 sew=sew, Commutable=1>;3211}3212 3213multiclass VPseudoTernaryW_VV<LMULInfo m, bit Commutable = 0> {3214 defvar constraint = "@earlyclobber $rd";3215 defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,3216 constraint, Commutable=Commutable, TargetConstraintType=3>;3217}3218 3219multiclass VPseudoTernaryW_VV_RM<LMULInfo m, int sew> {3220 defvar constraint = "@earlyclobber $rd";3221 defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,3222 constraint, sew,3223 TargetConstraintType=3>;3224}3225 3226multiclass VPseudoTernaryW_VX<LMULInfo m> {3227 defvar constraint = "@earlyclobber $rd";3228 defm "_VX" : VPseudoTernaryWithPolicy<m.wvrclass, GPR, m.vrclass, m,3229 constraint, TargetConstraintType=3>;3230}3231 3232multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f, int sew> {3233 defvar constraint = "@earlyclobber $rd";3234 defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass,3235 m.vrclass, m, constraint,3236 sew=sew,3237 TargetConstraintType=3>;3238}3239 3240multiclass VPseudoVSLDVWithPolicy<VReg RetClass,3241 RegisterClass Op1Class,3242 DAGOperand Op2Class,3243 LMULInfo MInfo,3244 string Constraint = ""> {3245 let VLMul = MInfo.value in {3246 def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;3247 def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,3248 RISCVMaskedPseudo<MaskIdx=3>;3249 }3250}3251 3252multiclass VPseudoVSLDV_VX<LMULInfo m, string Constraint = ""> {3253 defm _VX : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;3254}3255 3256multiclass VPseudoVSLDV_VI<LMULInfo m, string Constraint = ""> {3257 defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, uimm5, m, Constraint>;3258}3259 3260multiclass VPseudoVMAC_VV_VX_AAXA {3261 foreach m = MxList in {3262 defvar mx = m.MX;3263 defm "" : VPseudoTernaryV_VV_AAXA<m>,3264 SchedTernary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV",3265 "ReadVIMulAddV", mx>;3266 defm "" : VPseudoTernaryV_VX_AAXA<m>,3267 SchedTernary<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX",3268 "ReadVIMulAddV", mx>;3269 }3270}3271 3272multiclass VPseudoVMAC_VV_VF_AAXA_RM {3273 foreach m = MxListF in {3274 foreach e = SchedSEWSet<m.MX, isF=1>.val in3275 defm "" : VPseudoTernaryV_VV_AAXA_RM<m, sew=e>,3276 SchedTernary<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV",3277 "ReadVFMulAddV", m.MX, e>;3278 }3279 3280 foreach f = FPList in {3281 foreach m = f.MxList in {3282 defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, sew=f.SEW>,3283 SchedTernary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF",3284 "ReadVFMulAddV", m.MX, f.SEW>;3285 }3286 }3287}3288 3289multiclass VPseudoVSLD_VX_VI<bit slidesUp = false, string Constraint = ""> {3290 defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");3291 foreach m = MxList in {3292 defvar mx = m.MX;3293 defm "" : VPseudoVSLDV_VX<m, Constraint>,3294 SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",3295 "ReadVISlideX", mx>;3296 defm "" : VPseudoVSLDV_VI<m, Constraint>,3297 SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;3298 }3299}3300 3301multiclass VPseudoVWMAC_VV_VX<bit Commutable = 0> {3302 foreach m = MxListW in {3303 defvar mx = m.MX;3304 defm "" : VPseudoTernaryW_VV<m, Commutable=Commutable>,3305 SchedTernary<"WriteVIWMulAddV", "ReadVIWMulAddV", "ReadVIWMulAddV",3306 "ReadVIWMulAddV", mx>;3307 defm "" : VPseudoTernaryW_VX<m>,3308 SchedTernary<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddX",3309 "ReadVIWMulAddV", mx>;3310 }3311}3312 3313multiclass VPseudoVWMAC_VX {3314 foreach m = MxListW in {3315 defm "" : VPseudoTernaryW_VX<m>,3316 SchedTernary<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddX",3317 "ReadVIWMulAddV", m.MX>;3318 }3319}3320 3321multiclass VPseudoVWMAC_VV_VF_RM {3322 foreach m = MxListFW in {3323 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in3324 defm "" : VPseudoTernaryW_VV_RM<m, sew=e>,3325 SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",3326 "ReadVFWMulAddV", "ReadVFWMulAddV", m.MX, e>;3327 }3328 3329 foreach f = FPListW in {3330 foreach m = f.MxListFW in {3331 defm "" : VPseudoTernaryW_VF_RM<m, f, sew=f.SEW>,3332 SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV",3333 "ReadVFWMulAddF", "ReadVFWMulAddV", m.MX, f.SEW>;3334 }3335 }3336}3337 3338multiclass VPseudoVWMAC_VV_VF_BF_RM {3339 foreach m = MxListFW in {3340 defvar mx = m.MX;3341 foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in3342 defm "" : VPseudoTernaryW_VV_RM<m, sew=e>,3343 SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",3344 "ReadVFWMulAddV", "ReadVFWMulAddV", mx, e>;3345 }3346 3347 foreach f = BFPListW in {3348 foreach m = f.MxListFW in {3349 defvar mx = m.MX;3350 defm "" : VPseudoTernaryW_VF_RM<m, f, sew=f.SEW>,3351 SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV",3352 "ReadVFWMulAddF", "ReadVFWMulAddV", mx, f.SEW>;3353 }3354 }3355}3356 3357multiclass VPseudoVCMPM_VV_VX_VI<bit Commutable = 0> {3358 foreach m = MxList in {3359 defvar mx = m.MX;3360 defm "" : VPseudoBinaryM_VV<m, Commutable=Commutable>,3361 SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;3362 defm "" : VPseudoBinaryM_VX<m>,3363 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;3364 defm "" : VPseudoBinaryM_VI<m>,3365 SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;3366 }3367}3368 3369multiclass VPseudoVCMPM_VV_VX {3370 foreach m = MxList in {3371 defvar mx = m.MX;3372 defm "" : VPseudoBinaryM_VV<m>,3373 SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;3374 defm "" : VPseudoBinaryM_VX<m>,3375 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;3376 }3377}3378 3379multiclass VPseudoVCMPM_VX_VI {3380 foreach m = MxList in {3381 defvar mx = m.MX;3382 defm "" : VPseudoBinaryM_VX<m>,3383 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;3384 defm "" : VPseudoBinaryM_VI<m>,3385 SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;3386 }3387}3388 3389multiclass VPseudoVCMPM_VV_VF {3390 foreach m = MxListF in {3391 defm "" : VPseudoBinaryM_VV<m>,3392 SchedBinary<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV", m.MX>;3393 }3394 3395 foreach f = FPList in {3396 foreach m = f.MxList in {3397 defm "" : VPseudoBinaryM_VF<m, f>,3398 SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;3399 }3400 }3401}3402 3403multiclass VPseudoVCMPM_VF {3404 foreach f = FPList in {3405 foreach m = f.MxList in {3406 defm "" : VPseudoBinaryM_VF<m, f>,3407 SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;3408 }3409 }3410}3411 3412multiclass VPseudoVRED_VS {3413 foreach m = MxList in {3414 defvar mx = m.MX;3415 foreach e = SchedSEWSet<mx>.val in {3416 defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,3417 SchedReduction<"WriteVIRedV_From", "ReadVIRedV", mx, e>;3418 }3419 }3420}3421 3422multiclass VPseudoVREDMINMAX_VS {3423 foreach m = MxList in {3424 defvar mx = m.MX;3425 foreach e = SchedSEWSet<mx>.val in {3426 defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,3427 SchedReduction<"WriteVIRedMinMaxV_From", "ReadVIRedV", mx, e>;3428 }3429 }3430}3431 3432multiclass VPseudoVWRED_VS {3433 foreach m = MxListWRed in {3434 defvar mx = m.MX;3435 foreach e = SchedSEWSet<mx, isWidening=1>.val in {3436 defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,3437 SchedReduction<"WriteVIWRedV_From", "ReadVIWRedV", mx, e>;3438 }3439 }3440}3441 3442multiclass VPseudoVFRED_VS_RM {3443 foreach m = MxListF in {3444 defvar mx = m.MX;3445 foreach e = SchedSEWSet<mx, isF=1>.val in {3446 defm _VS3447 : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,3448 V_M1.vrclass, m, e>,3449 SchedReduction<"WriteVFRedV_From", "ReadVFRedV", mx, e>;3450 }3451 }3452}3453 3454multiclass VPseudoVFREDMINMAX_VS {3455 foreach m = MxListF in {3456 defvar mx = m.MX;3457 foreach e = SchedSEWSet<mx, isF=1>.val in {3458 defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,3459 SchedReduction<"WriteVFRedMinMaxV_From", "ReadVFRedV", mx, e>;3460 }3461 }3462}3463 3464multiclass VPseudoVFREDO_VS_RM {3465 foreach m = MxListF in {3466 defvar mx = m.MX;3467 foreach e = SchedSEWSet<mx, isF=1>.val in {3468 defm _VS : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,3469 V_M1.vrclass, m, e>,3470 SchedReduction<"WriteVFRedOV_From", "ReadVFRedOV", mx, e>;3471 }3472 }3473}3474 3475multiclass VPseudoVFWRED_VS_RM {3476 foreach m = MxListFWRed in {3477 defvar mx = m.MX;3478 foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in {3479 defm _VS3480 : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,3481 V_M1.vrclass, m, e>,3482 SchedReduction<"WriteVFWRedV_From", "ReadVFWRedV", mx, e>;3483 }3484 }3485}3486 3487multiclass VPseudoVFWREDO_VS_RM {3488 foreach m = MxListFWRed in {3489 defvar mx = m.MX;3490 foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in {3491 defm _VS3492 : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,3493 V_M1.vrclass, m, e>,3494 SchedReduction<"WriteVFWRedOV_From", "ReadVFWRedV", mx, e>;3495 }3496 }3497}3498 3499multiclass VPseudoConversion<VReg RetClass,3500 VReg Op1Class,3501 LMULInfo MInfo,3502 string Constraint = "",3503 int sew = 0,3504 bits<2> TargetConstraintType = 1> {3505 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);3506 let VLMul = MInfo.value, SEW=sew in {3507 def suffix : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint, TargetConstraintType>;3508 def suffix # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,3509 Constraint, TargetConstraintType>,3510 RISCVMaskedPseudo<MaskIdx=2>;3511 }3512}3513 3514multiclass VPseudoConversionRoundingMode<VReg RetClass,3515 VReg Op1Class,3516 LMULInfo MInfo,3517 string Constraint = "",3518 int sew = 0,3519 bits<2> TargetConstraintType = 1> {3520 let VLMul = MInfo.value, SEW=sew in {3521 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);3522 def suffix : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint, TargetConstraintType>;3523 def suffix # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,3524 Constraint,3525 TargetConstraintType>,3526 RISCVMaskedPseudo<MaskIdx=2>;3527 }3528}3529 3530multiclass VPseudoConversionNoExcept<VReg RetClass,3531 VReg Op1Class,3532 LMULInfo MInfo,3533 string Constraint = ""> {3534 let VLMul = MInfo.value in {3535 def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_NoExcept<RetClass, Op1Class, Constraint>;3536 }3537}3538 3539multiclass VPseudoVCVTI_V {3540 foreach m = MxListF in {3541 defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,3542 SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,3543 forcePassthruRead=true>;3544 }3545}3546 3547multiclass VPseudoVCVTI_V_RM {3548 foreach m = MxListF in {3549 defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>,3550 SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,3551 forcePassthruRead=true>;3552 }3553}3554 3555multiclass VPseudoVFROUND_NOEXCEPT_V {3556 foreach m = MxListF in {3557 defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m>,3558 SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,3559 forcePassthruRead=true>;3560 }3561}3562 3563multiclass VPseudoVCVTF_V_RM {3564 foreach m = MxListF in {3565 foreach e = SchedSEWSet<m.MX, isF=1>.val in3566 defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m, sew=e>,3567 SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,3568 forcePassthruRead=true>;3569 }3570}3571 3572multiclass VPseudoVWCVTI_V {3573 defvar constraint = "@earlyclobber $rd";3574 foreach m = MxListFW in {3575 defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,3576 SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,3577 forcePassthruRead=true>;3578 }3579}3580 3581multiclass VPseudoVWCVTI_V_RM {3582 defvar constraint = "@earlyclobber $rd";3583 foreach m = MxListFW in {3584 defm _V : VPseudoConversionRoundingMode<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,3585 SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,3586 forcePassthruRead=true>;3587 }3588}3589 3590multiclass VPseudoVWCVTF_V {3591 defvar constraint = "@earlyclobber $rd";3592 foreach m = MxListW in {3593 foreach e = SchedSEWSet<m.MX, isF=0, isWidening=1>.val in3594 defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=e,3595 TargetConstraintType=3>,3596 SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX, e,3597 forcePassthruRead=true>;3598 }3599}3600 3601multiclass VPseudoVWCVTD_V {3602 defvar constraint = "@earlyclobber $rd";3603 foreach m = MxListFW in {3604 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in3605 defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=e,3606 TargetConstraintType=3>,3607 SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX, e,3608 forcePassthruRead=true>;3609 }3610}3611 3612multiclass VPseudoVNCVTI_W {3613 defvar constraint = "@earlyclobber $rd";3614 foreach m = MxListW in {3615 defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,3616 SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,3617 forcePassthruRead=true>;3618 }3619}3620 3621multiclass VPseudoVNCVTI_W_RM {3622 defvar constraint = "@earlyclobber $rd";3623 foreach m = MxListW in {3624 defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,3625 SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,3626 forcePassthruRead=true>;3627 }3628}3629 3630multiclass VPseudoVNCVTF_W_RM {3631 defvar constraint = "@earlyclobber $rd";3632 foreach m = MxListFW in {3633 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in3634 defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,3635 constraint, sew=e,3636 TargetConstraintType=2>,3637 SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,3638 forcePassthruRead=true>;3639 }3640}3641 3642multiclass VPseudoVNCVTD_W {3643 defvar constraint = "@earlyclobber $rd";3644 foreach m = MxListFW in {3645 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in3646 defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, sew=e,3647 TargetConstraintType=2>,3648 SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, e,3649 forcePassthruRead=true>;3650 }3651}3652 3653multiclass VPseudoVNCVTD_W_RM {3654 defvar constraint = "@earlyclobber $rd";3655 foreach m = MxListFW in {3656 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in3657 defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,3658 constraint, sew=e,3659 TargetConstraintType=2>,3660 SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, e,3661 forcePassthruRead=true>;3662 }3663}3664 3665multiclass VPseudoUSSegLoad {3666 foreach eew = EEWList in {3667 foreach lmul = MxSet<eew>.m in {3668 defvar LInfo = lmul.MX;3669 let VLMul = lmul.value, SEW=eew in {3670 foreach nf = NFSet<lmul>.L in {3671 defvar vreg = SegRegClass<lmul, nf>.RC;3672 def nf # "E" # eew # "_V_" # LInfo :3673 VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;3674 def nf # "E" # eew # "_V_" # LInfo # "_MASK" :3675 VPseudoUSSegLoadMask<vreg, eew, nf>, RISCVMaskedPseudo<MaskIdx=2>,3676 VLSEGSched<nf, eew, LInfo>;3677 }3678 }3679 }3680 }3681}3682 3683multiclass VPseudoUSSegLoadFF {3684 foreach eew = EEWList in {3685 foreach lmul = MxSet<eew>.m in {3686 defvar LInfo = lmul.MX;3687 let VLMul = lmul.value, SEW=eew in {3688 foreach nf = NFSet<lmul>.L in {3689 defvar vreg = SegRegClass<lmul, nf>.RC;3690 def nf # "E" # eew # "FF_V_" # LInfo :3691 VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;3692 def nf # "E" # eew # "FF_V_" # LInfo # "_MASK" :3693 VPseudoUSSegLoadFFMask<vreg, eew, nf>, RISCVMaskedPseudo<MaskIdx=2>,3694 VLSEGFFSched<nf, eew, LInfo>;3695 }3696 }3697 }3698 }3699}3700 3701multiclass VPseudoSSegLoad {3702 foreach eew = EEWList in {3703 foreach lmul = MxSet<eew>.m in {3704 defvar LInfo = lmul.MX;3705 let VLMul = lmul.value, SEW=eew in {3706 foreach nf = NFSet<lmul>.L in {3707 defvar vreg = SegRegClass<lmul, nf>.RC;3708 def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,3709 VLSSEGSched<nf, eew, LInfo>;3710 def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>,3711 RISCVMaskedPseudo<MaskIdx=3>,3712 VLSSEGSched<nf, eew, LInfo>;3713 }3714 }3715 }3716 }3717}3718 3719multiclass VPseudoISegLoad<bit Ordered> {3720 foreach idxEEW = EEWList in {3721 foreach dataEEW = EEWList in {3722 foreach dataEMUL = MxSet<dataEEW>.m in {3723 defvar dataEMULOctuple = dataEMUL.octuple;3724 // Calculate emul = eew * lmul / sew3725 defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));3726 if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {3727 defvar DataLInfo = dataEMUL.MX;3728 defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;3729 defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);3730 defvar DataVreg = dataEMUL.vrclass;3731 defvar IdxVreg = idxEMUL.vrclass;3732 let VLMul = dataEMUL.value in {3733 foreach nf = NFSet<dataEMUL>.L in {3734 defvar Vreg = SegRegClass<dataEMUL, nf>.RC;3735 def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :3736 VPseudoISegLoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,3737 nf, Ordered>,3738 VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;3739 def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :3740 VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,3741 nf, Ordered>,3742 RISCVMaskedPseudo<MaskIdx=3>,3743 VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;3744 }3745 }3746 }3747 }3748 }3749 }3750}3751 3752multiclass VPseudoUSSegStore {3753 foreach eew = EEWList in {3754 foreach lmul = MxSet<eew>.m in {3755 defvar LInfo = lmul.MX;3756 let VLMul = lmul.value, SEW=eew in {3757 foreach nf = NFSet<lmul>.L in {3758 defvar vreg = SegRegClass<lmul, nf>.RC;3759 def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,3760 VSSEGSched<nf, eew, LInfo>;3761 def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,3762 RISCVMaskedPseudo<MaskIdx=2>,3763 VSSEGSched<nf, eew, LInfo>;3764 }3765 }3766 }3767 }3768}3769 3770multiclass VPseudoSSegStore {3771 foreach eew = EEWList in {3772 foreach lmul = MxSet<eew>.m in {3773 defvar LInfo = lmul.MX;3774 let VLMul = lmul.value, SEW=eew in {3775 foreach nf = NFSet<lmul>.L in {3776 defvar vreg = SegRegClass<lmul, nf>.RC;3777 def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,3778 VSSSEGSched<nf, eew, LInfo>;3779 def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,3780 RISCVMaskedPseudo<MaskIdx=3>,3781 VSSSEGSched<nf, eew, LInfo>;3782 }3783 }3784 }3785 }3786}3787 3788multiclass VPseudoISegStore<bit Ordered> {3789 foreach idxEEW = EEWList in {3790 foreach dataEEW = EEWList in {3791 foreach dataEMUL = MxSet<dataEEW>.m in {3792 defvar dataEMULOctuple = dataEMUL.octuple;3793 // Calculate emul = eew * lmul / sew3794 defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));3795 if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {3796 defvar DataLInfo = dataEMUL.MX;3797 defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;3798 defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);3799 defvar DataVreg = dataEMUL.vrclass;3800 defvar IdxVreg = idxEMUL.vrclass;3801 let VLMul = dataEMUL.value in {3802 foreach nf = NFSet<dataEMUL>.L in {3803 defvar Vreg = SegRegClass<dataEMUL, nf>.RC;3804 def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :3805 VPseudoISegStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,3806 nf, Ordered>,3807 VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;3808 def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :3809 VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,3810 nf, Ordered>,3811 RISCVMaskedPseudo<MaskIdx=3>,3812 VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;3813 }3814 }3815 }3816 }3817 }3818 }3819}3820 3821//===----------------------------------------------------------------------===//3822// Helpers to define the intrinsic patterns.3823//===----------------------------------------------------------------------===//3824 3825class VPatUnaryNoMask<string intrinsic_name,3826 string inst,3827 string kind,3828 ValueType result_type,3829 ValueType op2_type,3830 int log2sew,3831 LMULInfo vlmul,3832 VReg result_reg_class,3833 VReg op2_reg_class,3834 bit isSEWAware = 0> :3835 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)3836 (result_type result_reg_class:$passthru),3837 (op2_type op2_reg_class:$rs2),3838 VLOpFrag)),3839 (!cast<Instruction>(3840 !if(isSEWAware,3841 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),3842 inst#"_"#kind#"_"#vlmul.MX))3843 (result_type result_reg_class:$passthru),3844 (op2_type op2_reg_class:$rs2),3845 GPR:$vl, log2sew, TU_MU)>;3846 3847class VPatUnaryNoMaskRoundingMode<string intrinsic_name,3848 string inst,3849 string kind,3850 ValueType result_type,3851 ValueType op2_type,3852 int log2sew,3853 LMULInfo vlmul,3854 VReg result_reg_class,3855 VReg op2_reg_class,3856 bit isSEWAware = 0> :3857 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)3858 (result_type result_reg_class:$passthru),3859 (op2_type op2_reg_class:$rs2),3860 (XLenVT timm:$round),3861 VLOpFrag)),3862 (!cast<Instruction>(3863 !if(isSEWAware,3864 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),3865 inst#"_"#kind#"_"#vlmul.MX))3866 (result_type result_reg_class:$passthru),3867 (op2_type op2_reg_class:$rs2),3868 (XLenVT timm:$round),3869 GPR:$vl, log2sew, TU_MU)>;3870 3871class VPatUnaryNoMaskRTZ<string intrinsic_name,3872 string inst,3873 string kind,3874 ValueType result_type,3875 ValueType op2_type,3876 int log2sew,3877 LMULInfo vlmul,3878 VReg result_reg_class,3879 VReg op2_reg_class,3880 bit isSEWAware = 0> :3881 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)3882 (result_type result_reg_class:$passthru),3883 (op2_type op2_reg_class:$rs2),3884 (XLenVT 0b001),3885 VLOpFrag)),3886 (!cast<Instruction>(3887 !if(isSEWAware,3888 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),3889 inst#"_"#kind#"_"#vlmul.MX))3890 (result_type result_reg_class:$passthru),3891 (op2_type op2_reg_class:$rs2),3892 GPR:$vl, log2sew, TU_MU)>;3893 3894class VPatUnaryMask<string intrinsic_name,3895 string inst,3896 string kind,3897 ValueType result_type,3898 ValueType op2_type,3899 ValueType mask_type,3900 int log2sew,3901 LMULInfo vlmul,3902 VReg result_reg_class,3903 VReg op2_reg_class,3904 bit isSEWAware = 0> :3905 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")3906 (result_type result_reg_class:$passthru),3907 (op2_type op2_reg_class:$rs2),3908 (mask_type VMV0:$vm),3909 VLOpFrag, (XLenVT timm:$policy))),3910 (!cast<Instruction>(3911 !if(isSEWAware,3912 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",3913 inst#"_"#kind#"_"#vlmul.MX#"_MASK"))3914 (result_type result_reg_class:$passthru),3915 (op2_type op2_reg_class:$rs2),3916 (mask_type VMV0:$vm), GPR:$vl, log2sew, (XLenVT timm:$policy))>;3917 3918class VPatUnaryMaskRoundingMode<string intrinsic_name,3919 string inst,3920 string kind,3921 ValueType result_type,3922 ValueType op2_type,3923 ValueType mask_type,3924 int log2sew,3925 LMULInfo vlmul,3926 VReg result_reg_class,3927 VReg op2_reg_class,3928 bit isSEWAware = 0> :3929 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")3930 (result_type result_reg_class:$passthru),3931 (op2_type op2_reg_class:$rs2),3932 (mask_type VMV0:$vm),3933 (XLenVT timm:$round),3934 VLOpFrag, (XLenVT timm:$policy))),3935 (!cast<Instruction>(3936 !if(isSEWAware,3937 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",3938 inst#"_"#kind#"_"#vlmul.MX#"_MASK"))3939 (result_type result_reg_class:$passthru),3940 (op2_type op2_reg_class:$rs2),3941 (mask_type VMV0:$vm),3942 (XLenVT timm:$round),3943 GPR:$vl, log2sew, (XLenVT timm:$policy))>;3944 3945class VPatUnaryMaskRTZ<string intrinsic_name,3946 string inst,3947 string kind,3948 ValueType result_type,3949 ValueType op2_type,3950 ValueType mask_type,3951 int log2sew,3952 LMULInfo vlmul,3953 VReg result_reg_class,3954 VReg op2_reg_class,3955 bit isSEWAware = 0> :3956 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")3957 (result_type result_reg_class:$passthru),3958 (op2_type op2_reg_class:$rs2),3959 (mask_type VMV0:$vm),3960 (XLenVT 0b001),3961 VLOpFrag, (XLenVT timm:$policy))),3962 (!cast<Instruction>(3963 !if(isSEWAware,3964 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",3965 inst#"_"#kind#"_"#vlmul.MX#"_MASK"))3966 (result_type result_reg_class:$passthru),3967 (op2_type op2_reg_class:$rs2),3968 (mask_type VMV0:$vm),3969 GPR:$vl, log2sew, (XLenVT timm:$policy))>;3970 3971class VPatMaskUnaryNoMask<string intrinsic_name,3972 string inst,3973 MTypeInfo mti> :3974 Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name)3975 (mti.Mask VR:$rs2),3976 VLOpFrag)),3977 (!cast<Instruction>(inst#"_M_"#mti.BX)3978 (mti.Mask VR:$rs2),3979 GPR:$vl, mti.Log2SEW)>;3980 3981class VPatMaskUnaryMask<string intrinsic_name,3982 string inst,3983 MTypeInfo mti> :3984 Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask")3985 (mti.Mask VR:$passthru),3986 (mti.Mask VR:$rs2),3987 (mti.Mask VMV0:$vm),3988 VLOpFrag)),3989 (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK")3990 (mti.Mask VR:$passthru),3991 (mti.Mask VR:$rs2),3992 (mti.Mask VMV0:$vm), GPR:$vl, mti.Log2SEW, TA_MU)>;3993 3994class VPatUnaryAnyMask<string intrinsic,3995 string inst,3996 string kind,3997 ValueType result_type,3998 ValueType op1_type,3999 ValueType mask_type,4000 int log2sew,4001 LMULInfo vlmul,4002 VReg result_reg_class,4003 VReg op1_reg_class> :4004 Pat<(result_type (!cast<Intrinsic>(intrinsic)4005 (result_type result_reg_class:$passthru),4006 (op1_type op1_reg_class:$rs1),4007 (mask_type VR:$rs2),4008 VLOpFrag)),4009 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew))4010 (result_type result_reg_class:$passthru),4011 (op1_type op1_reg_class:$rs1),4012 (mask_type VR:$rs2),4013 GPR:$vl, log2sew)>;4014 4015class VPatBinaryM<string intrinsic_name,4016 string inst,4017 ValueType result_type,4018 ValueType op1_type,4019 ValueType op2_type,4020 int sew,4021 VReg op1_reg_class,4022 DAGOperand op2_kind> :4023 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4024 (op1_type op1_reg_class:$rs1),4025 (op2_type op2_kind:$rs2),4026 VLOpFrag)),4027 (!cast<Instruction>(inst)4028 (op1_type op1_reg_class:$rs1),4029 (op2_type op2_kind:$rs2),4030 GPR:$vl, sew)>;4031 4032class VPatBinaryNoMaskTU<string intrinsic_name,4033 string inst,4034 ValueType result_type,4035 ValueType op1_type,4036 ValueType op2_type,4037 int sew,4038 VReg result_reg_class,4039 VReg op1_reg_class,4040 DAGOperand op2_kind> :4041 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4042 (result_type result_reg_class:$passthru),4043 (op1_type op1_reg_class:$rs1),4044 (op2_type op2_kind:$rs2),4045 VLOpFrag)),4046 (!cast<Instruction>(inst)4047 (result_type result_reg_class:$passthru),4048 (op1_type op1_reg_class:$rs1),4049 (op2_type op2_kind:$rs2),4050 GPR:$vl, sew, TU_MU)>;4051 4052class VPatBinaryNoMaskTURoundingMode<string intrinsic_name,4053 string inst,4054 ValueType result_type,4055 ValueType op1_type,4056 ValueType op2_type,4057 int sew,4058 VReg result_reg_class,4059 VReg op1_reg_class,4060 DAGOperand op2_kind> :4061 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4062 (result_type result_reg_class:$passthru),4063 (op1_type op1_reg_class:$rs1),4064 (op2_type op2_kind:$rs2),4065 (XLenVT timm:$round),4066 VLOpFrag)),4067 (!cast<Instruction>(inst)4068 (result_type result_reg_class:$passthru),4069 (op1_type op1_reg_class:$rs1),4070 (op2_type op2_kind:$rs2),4071 (XLenVT timm:$round),4072 GPR:$vl, sew, TU_MU)>;4073 4074 4075// Same as VPatBinaryM but source operands are swapped.4076class VPatBinaryMSwapped<string intrinsic_name,4077 string inst,4078 ValueType result_type,4079 ValueType op1_type,4080 ValueType op2_type,4081 int sew,4082 VReg op1_reg_class,4083 DAGOperand op2_kind> :4084 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4085 (op2_type op2_kind:$rs2),4086 (op1_type op1_reg_class:$rs1),4087 VLOpFrag)),4088 (!cast<Instruction>(inst)4089 (op1_type op1_reg_class:$rs1),4090 (op2_type op2_kind:$rs2),4091 GPR:$vl, sew)>;4092 4093class VPatBinaryMask<string intrinsic_name,4094 string inst,4095 ValueType result_type,4096 ValueType op1_type,4097 ValueType op2_type,4098 ValueType mask_type,4099 int sew,4100 VReg result_reg_class,4101 VReg op1_reg_class,4102 DAGOperand op2_kind> :4103 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")4104 (result_type result_reg_class:$passthru),4105 (op1_type op1_reg_class:$rs1),4106 (op2_type op2_kind:$rs2),4107 (mask_type VMV0:$vm),4108 VLOpFrag)),4109 (!cast<Instruction>(inst#"_MASK")4110 (result_type result_reg_class:$passthru),4111 (op1_type op1_reg_class:$rs1),4112 (op2_type op2_kind:$rs2),4113 (mask_type VMV0:$vm), GPR:$vl, sew, TA_MU)>;4114 4115class VPatBinaryMaskPolicy<string intrinsic_name,4116 string inst,4117 ValueType result_type,4118 ValueType op1_type,4119 ValueType op2_type,4120 ValueType mask_type,4121 int sew,4122 VReg result_reg_class,4123 VReg op1_reg_class,4124 DAGOperand op2_kind> :4125 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")4126 (result_type result_reg_class:$passthru),4127 (op1_type op1_reg_class:$rs1),4128 (op2_type op2_kind:$rs2),4129 (mask_type VMV0:$vm),4130 VLOpFrag, (XLenVT timm:$policy))),4131 (!cast<Instruction>(inst#"_MASK")4132 (result_type result_reg_class:$passthru),4133 (op1_type op1_reg_class:$rs1),4134 (op2_type op2_kind:$rs2),4135 (mask_type VMV0:$vm), GPR:$vl, sew, (XLenVT timm:$policy))>;4136 4137class VPatBinaryMaskPolicyRoundingMode<string intrinsic_name,4138 string inst,4139 ValueType result_type,4140 ValueType op1_type,4141 ValueType op2_type,4142 ValueType mask_type,4143 int sew,4144 VReg result_reg_class,4145 VReg op1_reg_class,4146 DAGOperand op2_kind> :4147 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")4148 (result_type result_reg_class:$passthru),4149 (op1_type op1_reg_class:$rs1),4150 (op2_type op2_kind:$rs2),4151 (mask_type VMV0:$vm),4152 (XLenVT timm:$round),4153 VLOpFrag, (XLenVT timm:$policy))),4154 (!cast<Instruction>(inst#"_MASK")4155 (result_type result_reg_class:$passthru),4156 (op1_type op1_reg_class:$rs1),4157 (op2_type op2_kind:$rs2),4158 (mask_type VMV0:$vm),4159 (XLenVT timm:$round),4160 GPR:$vl, sew, (XLenVT timm:$policy))>;4161 4162// Same as VPatBinaryMask but source operands are swapped.4163class VPatBinaryMaskSwapped<string intrinsic_name,4164 string inst,4165 ValueType result_type,4166 ValueType op1_type,4167 ValueType op2_type,4168 ValueType mask_type,4169 int sew,4170 VReg result_reg_class,4171 VReg op1_reg_class,4172 DAGOperand op2_kind> :4173 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")4174 (result_type result_reg_class:$passthru),4175 (op2_type op2_kind:$rs2),4176 (op1_type op1_reg_class:$rs1),4177 (mask_type VMV0:$vm),4178 VLOpFrag)),4179 (!cast<Instruction>(inst#"_MASK")4180 (result_type result_reg_class:$passthru),4181 (op1_type op1_reg_class:$rs1),4182 (op2_type op2_kind:$rs2),4183 (mask_type VMV0:$vm), GPR:$vl, sew, TA_MU)>;4184 4185class VPatTiedBinaryNoMask<string intrinsic_name,4186 string inst,4187 ValueType result_type,4188 ValueType op2_type,4189 int sew,4190 VReg result_reg_class,4191 DAGOperand op2_kind> :4192 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4193 (result_type (undef)),4194 (result_type result_reg_class:$rs1),4195 (op2_type op2_kind:$rs2),4196 VLOpFrag)),4197 (!cast<Instruction>(inst#"_TIED")4198 (result_type result_reg_class:$rs1),4199 (op2_type op2_kind:$rs2),4200 GPR:$vl, sew, TAIL_AGNOSTIC)>;4201 4202class VPatTiedBinaryNoMaskRoundingMode<string intrinsic_name,4203 string inst,4204 ValueType result_type,4205 ValueType op2_type,4206 int sew,4207 VReg result_reg_class,4208 DAGOperand op2_kind> :4209 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4210 (result_type (undef)),4211 (result_type result_reg_class:$rs1),4212 (op2_type op2_kind:$rs2),4213 (XLenVT timm:$round),4214 VLOpFrag)),4215 (!cast<Instruction>(inst#"_TIED")4216 (result_type result_reg_class:$rs1),4217 (op2_type op2_kind:$rs2),4218 (XLenVT timm:$round),4219 GPR:$vl, sew, TAIL_AGNOSTIC)>;4220 4221class VPatTiedBinaryNoMaskTU<string intrinsic_name,4222 string inst,4223 ValueType result_type,4224 ValueType op2_type,4225 int sew,4226 VReg result_reg_class,4227 DAGOperand op2_kind> :4228 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4229 (result_type result_reg_class:$passthru),4230 (result_type result_reg_class:$passthru),4231 (op2_type op2_kind:$rs2),4232 VLOpFrag)),4233 (!cast<Instruction>(inst#"_TIED")4234 (result_type result_reg_class:$passthru),4235 (op2_type op2_kind:$rs2),4236 GPR:$vl, sew, TU_MU)>;4237 4238class VPatTiedBinaryNoMaskTURoundingMode<string intrinsic_name,4239 string inst,4240 ValueType result_type,4241 ValueType op2_type,4242 int sew,4243 VReg result_reg_class,4244 DAGOperand op2_kind> :4245 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)4246 (result_type result_reg_class:$passthru),4247 (result_type result_reg_class:$passthru),4248 (op2_type op2_kind:$rs2),4249 (XLenVT timm:$round),4250 VLOpFrag)),4251 (!cast<Instruction>(inst#"_TIED")4252 (result_type result_reg_class:$passthru),4253 (op2_type op2_kind:$rs2),4254 (XLenVT timm:$round),4255 GPR:$vl, sew, TU_MU)>;4256 4257class VPatTiedBinaryMask<string intrinsic_name,4258 string inst,4259 ValueType result_type,4260 ValueType op2_type,4261 ValueType mask_type,4262 int sew,4263 VReg result_reg_class,4264 DAGOperand op2_kind> :4265 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")4266 (result_type result_reg_class:$passthru),4267 (result_type result_reg_class:$passthru),4268 (op2_type op2_kind:$rs2),4269 (mask_type VMV0:$vm),4270 VLOpFrag, (XLenVT timm:$policy))),4271 (!cast<Instruction>(inst#"_MASK_TIED")4272 (result_type result_reg_class:$passthru),4273 (op2_type op2_kind:$rs2),4274 (mask_type VMV0:$vm), GPR:$vl, sew, (XLenVT timm:$policy))>;4275 4276class VPatTiedBinaryMaskRoundingMode<string intrinsic_name,4277 string inst,4278 ValueType result_type,4279 ValueType op2_type,4280 ValueType mask_type,4281 int sew,4282 VReg result_reg_class,4283 DAGOperand op2_kind> :4284 Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")4285 (result_type result_reg_class:$passthru),4286 (result_type result_reg_class:$passthru),4287 (op2_type op2_kind:$rs2),4288 (mask_type VMV0:$vm),4289 (XLenVT timm:$round),4290 VLOpFrag, (XLenVT timm:$policy))),4291 (!cast<Instruction>(inst#"_MASK_TIED")4292 (result_type result_reg_class:$passthru),4293 (op2_type op2_kind:$rs2),4294 (mask_type VMV0:$vm),4295 (XLenVT timm:$round),4296 GPR:$vl, sew, (XLenVT timm:$policy))>;4297 4298class VPatTernaryNoMaskTU<string intrinsic,4299 string inst,4300 string kind,4301 ValueType result_type,4302 ValueType op1_type,4303 ValueType op2_type,4304 int log2sew,4305 LMULInfo vlmul,4306 VReg result_reg_class,4307 RegisterClass op1_reg_class,4308 DAGOperand op2_kind> :4309 Pat<(result_type (!cast<Intrinsic>(intrinsic)4310 (result_type result_reg_class:$rs3),4311 (op1_type op1_reg_class:$rs1),4312 (op2_type op2_kind:$rs2),4313 VLOpFrag)),4314 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew))4315 result_reg_class:$rs3,4316 (op1_type op1_reg_class:$rs1),4317 op2_kind:$rs2,4318 GPR:$vl, log2sew, TU_MU)>;4319 4320class VPatTernaryNoMaskTURoundingMode<string intrinsic,4321 string inst,4322 string kind,4323 ValueType result_type,4324 ValueType op1_type,4325 ValueType op2_type,4326 int log2sew,4327 LMULInfo vlmul,4328 VReg result_reg_class,4329 RegisterClass op1_reg_class,4330 DAGOperand op2_kind> :4331 Pat<(result_type (!cast<Intrinsic>(intrinsic)4332 (result_type result_reg_class:$rs3),4333 (op1_type op1_reg_class:$rs1),4334 (op2_type op2_kind:$rs2),4335 (XLenVT timm:$round),4336 VLOpFrag)),4337 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew))4338 result_reg_class:$rs3,4339 (op1_type op1_reg_class:$rs1),4340 op2_kind:$rs2,4341 (XLenVT timm:$round),4342 GPR:$vl, log2sew, TU_MU)>;4343 4344class VPatTernaryNoMaskWithPolicy<string intrinsic,4345 string inst,4346 string kind,4347 ValueType result_type,4348 ValueType op1_type,4349 ValueType op2_type,4350 int log2sew,4351 LMULInfo vlmul,4352 VReg result_reg_class,4353 RegisterClass op1_reg_class,4354 DAGOperand op2_kind,4355 bit isSEWAware = false> :4356 Pat<(result_type (!cast<Intrinsic>(intrinsic)4357 (result_type result_reg_class:$rs3),4358 (op1_type op1_reg_class:$rs1),4359 (op2_type op2_kind:$rs2),4360 VLOpFrag, (XLenVT timm:$policy))),4361 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#!if(isSEWAware, "_E"#!shl(1, log2sew), ""))4362 result_reg_class:$rs3,4363 (op1_type op1_reg_class:$rs1),4364 op2_kind:$rs2,4365 GPR:$vl, log2sew, (XLenVT timm:$policy))>;4366 4367class VPatTernaryNoMaskWithPolicyRoundingMode<string intrinsic,4368 string inst,4369 string kind,4370 ValueType result_type,4371 ValueType op1_type,4372 ValueType op2_type,4373 int log2sew,4374 LMULInfo vlmul,4375 VReg result_reg_class,4376 RegisterClass op1_reg_class,4377 DAGOperand op2_kind,4378 bit isSEWAware = 0> :4379 Pat<(result_type (!cast<Intrinsic>(intrinsic)4380 (result_type result_reg_class:$rs3),4381 (op1_type op1_reg_class:$rs1),4382 (op2_type op2_kind:$rs2),4383 (XLenVT timm:$round),4384 VLOpFrag, (XLenVT timm:$policy))),4385 (!cast<Instruction>(!if(isSEWAware,4386 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),4387 inst#"_"#kind#"_"#vlmul.MX))4388 result_reg_class:$rs3,4389 (op1_type op1_reg_class:$rs1),4390 op2_kind:$rs2,4391 (XLenVT timm:$round),4392 GPR:$vl, log2sew, (XLenVT timm:$policy))>;4393 4394class VPatTernaryMaskPolicy<string intrinsic,4395 string inst,4396 string kind,4397 ValueType result_type,4398 ValueType op1_type,4399 ValueType op2_type,4400 ValueType mask_type,4401 int sew,4402 LMULInfo vlmul,4403 VReg result_reg_class,4404 RegisterClass op1_reg_class,4405 DAGOperand op2_kind> :4406 Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")4407 (result_type result_reg_class:$rs3),4408 (op1_type op1_reg_class:$rs1),4409 (op2_type op2_kind:$rs2),4410 (mask_type VMV0:$vm),4411 VLOpFrag, (XLenVT timm:$policy))),4412 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK")4413 result_reg_class:$rs3,4414 (op1_type op1_reg_class:$rs1),4415 op2_kind:$rs2,4416 (mask_type VMV0:$vm),4417 GPR:$vl, sew, (XLenVT timm:$policy))>;4418 4419class VPatTernaryMaskPolicyRoundingMode<string intrinsic,4420 string inst,4421 string kind,4422 ValueType result_type,4423 ValueType op1_type,4424 ValueType op2_type,4425 ValueType mask_type,4426 int log2sew,4427 LMULInfo vlmul,4428 VReg result_reg_class,4429 RegisterClass op1_reg_class,4430 DAGOperand op2_kind,4431 bit isSEWAware = 0> :4432 Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")4433 (result_type result_reg_class:$rs3),4434 (op1_type op1_reg_class:$rs1),4435 (op2_type op2_kind:$rs2),4436 (mask_type VMV0:$vm),4437 (XLenVT timm:$round),4438 VLOpFrag, (XLenVT timm:$policy))),4439 (!cast<Instruction>(!if(isSEWAware,4440 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew) # "_MASK",4441 inst#"_"#kind#"_"#vlmul.MX # "_MASK"))4442 result_reg_class:$rs3,4443 (op1_type op1_reg_class:$rs1),4444 op2_kind:$rs2,4445 (mask_type VMV0:$vm),4446 (XLenVT timm:$round),4447 GPR:$vl, log2sew, (XLenVT timm:$policy))>;4448 4449class VPatTernaryMaskTU<string intrinsic,4450 string inst,4451 string kind,4452 ValueType result_type,4453 ValueType op1_type,4454 ValueType op2_type,4455 ValueType mask_type,4456 int log2sew,4457 LMULInfo vlmul,4458 VReg result_reg_class,4459 RegisterClass op1_reg_class,4460 DAGOperand op2_kind> :4461 Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")4462 (result_type result_reg_class:$rs3),4463 (op1_type op1_reg_class:$rs1),4464 (op2_type op2_kind:$rs2),4465 (mask_type VMV0:$vm),4466 VLOpFrag)),4467 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)# "_MASK")4468 result_reg_class:$rs3,4469 (op1_type op1_reg_class:$rs1),4470 op2_kind:$rs2,4471 (mask_type VMV0:$vm),4472 GPR:$vl, log2sew, TU_MU)>;4473 4474class VPatTernaryMaskTURoundingMode<string intrinsic,4475 string inst,4476 string kind,4477 ValueType result_type,4478 ValueType op1_type,4479 ValueType op2_type,4480 ValueType mask_type,4481 int log2sew,4482 LMULInfo vlmul,4483 VReg result_reg_class,4484 RegisterClass op1_reg_class,4485 DAGOperand op2_kind> :4486 Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")4487 (result_type result_reg_class:$rs3),4488 (op1_type op1_reg_class:$rs1),4489 (op2_type op2_kind:$rs2),4490 (mask_type VMV0:$vm),4491 (XLenVT timm:$round),4492 VLOpFrag)),4493 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)# "_MASK")4494 result_reg_class:$rs3,4495 (op1_type op1_reg_class:$rs1),4496 op2_kind:$rs2,4497 (mask_type VMV0:$vm),4498 (XLenVT timm:$round),4499 GPR:$vl, log2sew, TU_MU)>;4500 4501multiclass VPatUnaryS_M<string intrinsic_name,4502 string inst> {4503 foreach mti = AllMasks in {4504 def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name)4505 (mti.Mask VR:$rs1), VLOpFrag)),4506 (!cast<Instruction>(inst#"_M_"#mti.BX) $rs1,4507 GPR:$vl, mti.Log2SEW)>;4508 def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name # "_mask")4509 (mti.Mask VR:$rs1), (mti.Mask VMV0:$vm), VLOpFrag)),4510 (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK") $rs1,4511 (mti.Mask VMV0:$vm), GPR:$vl, mti.Log2SEW)>;4512 }4513}4514 4515multiclass VPatUnaryV_V_AnyMask<string intrinsic, string instruction,4516 list<VTypeInfo> vtilist> {4517 foreach vti = vtilist in {4518 defvar ivti = GetIntVTypeInfo<vti>.Vti;4519 let Predicates = GetVTypePredicates<ivti>.Predicates in4520 def : VPatUnaryAnyMask<intrinsic, instruction, "VM",4521 vti.Vector, vti.Vector, vti.Mask,4522 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>;4523 }4524}4525 4526multiclass VPatUnaryM_M<string intrinsic,4527 string inst> {4528 foreach mti = AllMasks in {4529 def : VPatMaskUnaryNoMask<intrinsic, inst, mti>;4530 def : VPatMaskUnaryMask<intrinsic, inst, mti>;4531 }4532}4533 4534multiclass VPatUnaryV_M<string intrinsic, string instruction> {4535 foreach vti = AllIntegerVectors in {4536 let Predicates = GetVTypePredicates<vti>.Predicates in {4537 def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,4538 vti.Log2SEW, vti.LMul, vti.RegClass, VR>;4539 def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,4540 vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;4541 }4542 }4543}4544 4545multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,4546 list<VTypeInfoToFraction> fractionList> {4547 foreach vtiTofti = fractionList in {4548 defvar vti = vtiTofti.Vti;4549 defvar fti = vtiTofti.Fti;4550 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,4551 GetVTypePredicates<fti>.Predicates) in {4552 def : VPatUnaryNoMask<intrinsic, instruction, suffix,4553 vti.Vector, fti.Vector,4554 vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;4555 def : VPatUnaryMask<intrinsic, instruction, suffix,4556 vti.Vector, fti.Vector, vti.Mask,4557 vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;4558 }4559 }4560}4561 4562multiclass VPatUnaryV_V<string intrinsic, string instruction,4563 list<VTypeInfo> vtilist, bit isSEWAware = 0> {4564 foreach vti = vtilist in {4565 let Predicates = GetVTypePredicates<vti>.Predicates in {4566 def : VPatUnaryNoMask<intrinsic, instruction, "V",4567 vti.Vector, vti.Vector, vti.Log2SEW,4568 vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;4569 def : VPatUnaryMask<intrinsic, instruction, "V",4570 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,4571 vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;4572 }4573 }4574}4575 4576multiclass VPatUnaryV_V_RM<string intrinsic, string instruction,4577 list<VTypeInfo> vtilist, bit isSEWAware = 0> {4578 foreach vti = vtilist in {4579 let Predicates = GetVTypePredicates<vti>.Predicates in {4580 def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "V",4581 vti.Vector, vti.Vector, vti.Log2SEW,4582 vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;4583 def : VPatUnaryMaskRoundingMode<intrinsic, instruction, "V",4584 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,4585 vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;4586 }4587 }4588}4589 4590multiclass VPatNullaryV<string intrinsic, string instruction> {4591 foreach vti = AllIntegerVectors in {4592 let Predicates = GetVTypePredicates<vti>.Predicates in {4593 def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)4594 (vti.Vector vti.RegClass:$passthru),4595 VLOpFrag)),4596 (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)4597 vti.RegClass:$passthru, GPR:$vl, vti.Log2SEW, TU_MU)>;4598 def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")4599 (vti.Vector vti.RegClass:$passthru),4600 (vti.Mask VMV0:$vm), VLOpFrag, (XLenVT timm:$policy))),4601 (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK")4602 vti.RegClass:$passthru, (vti.Mask VMV0:$vm),4603 GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;4604 }4605 }4606}4607 4608multiclass VPatNullaryM<string intrinsic, string inst> {4609 foreach mti = AllMasks in4610 def : Pat<(mti.Mask (!cast<Intrinsic>(intrinsic)4611 VLOpFrag)),4612 (!cast<Instruction>(inst#"_M_"#mti.BX)4613 GPR:$vl, mti.Log2SEW)>;4614}4615 4616multiclass VPatBinaryM<string intrinsic,4617 string inst,4618 ValueType result_type,4619 ValueType op1_type,4620 ValueType op2_type,4621 ValueType mask_type,4622 int sew,4623 VReg result_reg_class,4624 VReg op1_reg_class,4625 DAGOperand op2_kind> {4626 def : VPatBinaryM<intrinsic, inst, result_type, op1_type, op2_type,4627 sew, op1_reg_class, op2_kind>;4628 def : VPatBinaryMask<intrinsic, inst, result_type, op1_type, op2_type,4629 mask_type, sew, result_reg_class, op1_reg_class,4630 op2_kind>;4631}4632 4633multiclass VPatBinary<string intrinsic,4634 string inst,4635 ValueType result_type,4636 ValueType op1_type,4637 ValueType op2_type,4638 ValueType mask_type,4639 int sew,4640 VReg result_reg_class,4641 VReg op1_reg_class,4642 DAGOperand op2_kind> {4643 def : VPatBinaryNoMaskTU<intrinsic, inst, result_type, op1_type, op2_type,4644 sew, result_reg_class, op1_reg_class, op2_kind>;4645 def : VPatBinaryMaskPolicy<intrinsic, inst, result_type, op1_type, op2_type,4646 mask_type, sew, result_reg_class, op1_reg_class,4647 op2_kind>;4648}4649 4650multiclass VPatBinaryRoundingMode<string intrinsic,4651 string inst,4652 ValueType result_type,4653 ValueType op1_type,4654 ValueType op2_type,4655 ValueType mask_type,4656 int sew,4657 VReg result_reg_class,4658 VReg op1_reg_class,4659 DAGOperand op2_kind> {4660 def : VPatBinaryNoMaskTURoundingMode<intrinsic, inst, result_type, op1_type, op2_type,4661 sew, result_reg_class, op1_reg_class, op2_kind>;4662 def : VPatBinaryMaskPolicyRoundingMode<intrinsic, inst, result_type, op1_type, op2_type,4663 mask_type, sew, result_reg_class, op1_reg_class,4664 op2_kind>;4665}4666 4667multiclass VPatBinaryMSwapped<string intrinsic,4668 string inst,4669 ValueType result_type,4670 ValueType op1_type,4671 ValueType op2_type,4672 ValueType mask_type,4673 int sew,4674 VReg result_reg_class,4675 VReg op1_reg_class,4676 DAGOperand op2_kind> {4677 def : VPatBinaryMSwapped<intrinsic, inst, result_type, op1_type, op2_type,4678 sew, op1_reg_class, op2_kind>;4679 def : VPatBinaryMaskSwapped<intrinsic, inst, result_type, op1_type, op2_type,4680 mask_type, sew, result_reg_class, op1_reg_class,4681 op2_kind>;4682}4683 4684multiclass VPatBinaryCarryInTAIL<string intrinsic,4685 string inst,4686 string kind,4687 ValueType result_type,4688 ValueType op1_type,4689 ValueType op2_type,4690 ValueType mask_type,4691 int sew,4692 LMULInfo vlmul,4693 VReg result_reg_class,4694 VReg op1_reg_class,4695 DAGOperand op2_kind> {4696 def : Pat<(result_type (!cast<Intrinsic>(intrinsic)4697 (result_type result_reg_class:$passthru),4698 (op1_type op1_reg_class:$rs1),4699 (op2_type op2_kind:$rs2),4700 (mask_type VMV0:$vm),4701 VLOpFrag)),4702 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)4703 (result_type result_reg_class:$passthru),4704 (op1_type op1_reg_class:$rs1),4705 (op2_type op2_kind:$rs2),4706 (mask_type VMV0:$vm), GPR:$vl, sew)>;4707}4708 4709multiclass VPatBinaryCarryIn<string intrinsic,4710 string inst,4711 string kind,4712 ValueType result_type,4713 ValueType op1_type,4714 ValueType op2_type,4715 ValueType mask_type,4716 int sew,4717 LMULInfo vlmul,4718 VReg op1_reg_class,4719 DAGOperand op2_kind> {4720 def : Pat<(result_type (!cast<Intrinsic>(intrinsic)4721 (op1_type op1_reg_class:$rs1),4722 (op2_type op2_kind:$rs2),4723 (mask_type VMV0:$vm),4724 VLOpFrag)),4725 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)4726 (op1_type op1_reg_class:$rs1),4727 (op2_type op2_kind:$rs2),4728 (mask_type VMV0:$vm), GPR:$vl, sew)>;4729}4730 4731multiclass VPatBinaryMaskOut<string intrinsic,4732 string inst,4733 string kind,4734 ValueType result_type,4735 ValueType op1_type,4736 ValueType op2_type,4737 int sew,4738 LMULInfo vlmul,4739 VReg op1_reg_class,4740 DAGOperand op2_kind> {4741 def : Pat<(result_type (!cast<Intrinsic>(intrinsic)4742 (op1_type op1_reg_class:$rs1),4743 (op2_type op2_kind:$rs2),4744 VLOpFrag)),4745 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)4746 (op1_type op1_reg_class:$rs1),4747 (op2_type op2_kind:$rs2),4748 GPR:$vl, sew)>;4749}4750 4751multiclass VPatConversion<string intrinsic,4752 string inst,4753 string kind,4754 ValueType result_type,4755 ValueType op1_type,4756 ValueType mask_type,4757 int log2sew,4758 LMULInfo vlmul,4759 VReg result_reg_class,4760 VReg op1_reg_class,4761 bit isSEWAware = 0> {4762 def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type,4763 log2sew, vlmul, result_reg_class, op1_reg_class,4764 isSEWAware>;4765 def : VPatUnaryMask<intrinsic, inst, kind, result_type, op1_type,4766 mask_type, log2sew, vlmul, result_reg_class, op1_reg_class,4767 isSEWAware>;4768}4769 4770multiclass VPatConversionRoundingMode<string intrinsic,4771 string inst,4772 string kind,4773 ValueType result_type,4774 ValueType op1_type,4775 ValueType mask_type,4776 int log2sew,4777 LMULInfo vlmul,4778 VReg result_reg_class,4779 VReg op1_reg_class,4780 bit isSEWAware = 0> {4781 def : VPatUnaryNoMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type,4782 log2sew, vlmul, result_reg_class,4783 op1_reg_class, isSEWAware>;4784 def : VPatUnaryMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type,4785 mask_type, log2sew, vlmul, result_reg_class,4786 op1_reg_class, isSEWAware>;4787}4788 4789multiclass VPatConversionRTZ<string intrinsic,4790 string inst,4791 string kind,4792 ValueType result_type,4793 ValueType op1_type,4794 ValueType mask_type,4795 int log2sew,4796 LMULInfo vlmul,4797 VReg result_reg_class,4798 VReg op1_reg_class,4799 bit isSEWAware = 0> {4800 def : VPatUnaryNoMaskRTZ<intrinsic, inst, kind, result_type, op1_type,4801 log2sew, vlmul, result_reg_class,4802 op1_reg_class, isSEWAware>;4803 def : VPatUnaryMaskRTZ<intrinsic, inst, kind, result_type, op1_type,4804 mask_type, log2sew, vlmul, result_reg_class,4805 op1_reg_class, isSEWAware>;4806}4807 4808multiclass VPatBinaryV_VV<string intrinsic, string instruction,4809 list<VTypeInfo> vtilist, bit isSEWAware = 0> {4810 foreach vti = vtilist in4811 let Predicates = GetVTypePredicates<vti>.Predicates in4812 defm : VPatBinary<intrinsic,4813 !if(isSEWAware,4814 instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,4815 instruction # "_VV_" # vti.LMul.MX),4816 vti.Vector, vti.Vector, vti.Vector,vti.Mask,4817 vti.Log2SEW, vti.RegClass,4818 vti.RegClass, vti.RegClass>;4819}4820 4821multiclass VPatBinaryV_VV_RM<string intrinsic, string instruction,4822 list<VTypeInfo> vtilist, bit isSEWAware = 0> {4823 foreach vti = vtilist in4824 let Predicates = GetVTypePredicates<vti>.Predicates in4825 defm : VPatBinaryRoundingMode<intrinsic,4826 !if(isSEWAware,4827 instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,4828 instruction # "_VV_" # vti.LMul.MX),4829 vti.Vector, vti.Vector, vti.Vector,vti.Mask,4830 vti.Log2SEW, vti.RegClass,4831 vti.RegClass, vti.RegClass>;4832}4833 4834multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction,4835 list<VTypeInfo> vtilist> {4836 foreach vti = vtilist in {4837 defvar ivti = GetIntVTypeInfo<vti>.Vti;4838 let Predicates = GetVTypePredicates<ivti>.Predicates in4839 defm : VPatBinary<intrinsic,4840 instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,4841 vti.Vector, vti.Vector, ivti.Vector, vti.Mask,4842 vti.Log2SEW, vti.RegClass,4843 vti.RegClass, vti.RegClass>;4844 }4845}4846 4847multiclass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction,4848 int eew, list<VTypeInfo> vtilist> {4849 foreach vti = vtilist in {4850 // emul = lmul * eew / sew4851 defvar vlmul = vti.LMul;4852 defvar octuple_lmul = vlmul.octuple;4853 defvar octuple_emul = !srl(!mul(octuple_lmul, eew), vti.Log2SEW);4854 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {4855 defvar ivti = GetIntVTypeInfo<vti>.Vti;4856 defvar emul_str = octuple_to_str<octuple_emul>.ret;4857 defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;4858 defvar eivti = !cast<VTypeInfo>("VI" # eew # emul_str);4859 let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates,4860 GetVTypePredicates<eivti>.Predicates) in4861 defm : VPatBinary<intrinsic, inst,4862 vti.Vector, vti.Vector, eivti.Vector, vti.Mask,4863 vti.Log2SEW, vti.RegClass,4864 vti.RegClass, eivti.RegClass>;4865 }4866 }4867}4868 4869multiclass VPatBinaryV_VX<string intrinsic, string instruction,4870 list<VTypeInfo> vtilist, bit isSEWAware = 0> {4871 foreach vti = vtilist in {4872 defvar kind = "V"#vti.ScalarSuffix;4873 let Predicates = GetVTypePredicates<vti>.Predicates in4874 defm : VPatBinary<intrinsic,4875 !if(isSEWAware,4876 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,4877 instruction#"_"#kind#"_"#vti.LMul.MX),4878 vti.Vector, vti.Vector, vti.Scalar, vti.Mask,4879 vti.Log2SEW, vti.RegClass,4880 vti.RegClass, vti.ScalarRegClass>;4881 }4882}4883 4884multiclass VPatBinaryV_VX_RM<string intrinsic, string instruction,4885 list<VTypeInfo> vtilist, bit isSEWAware = 0> {4886 foreach vti = vtilist in {4887 defvar kind = "V"#vti.ScalarSuffix;4888 let Predicates = GetVTypePredicates<vti>.Predicates in4889 defm : VPatBinaryRoundingMode<intrinsic,4890 !if(isSEWAware,4891 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,4892 instruction#"_"#kind#"_"#vti.LMul.MX),4893 vti.Vector, vti.Vector, vti.Scalar, vti.Mask,4894 vti.Log2SEW, vti.RegClass,4895 vti.RegClass, vti.ScalarRegClass>;4896 }4897}4898 4899multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,4900 list<VTypeInfo> vtilist> {4901 foreach vti = vtilist in {4902 defvar ivti = GetIntVTypeInfo<vti>.Vti;4903 let Predicates = GetVTypePredicates<ivti>.Predicates in4904 defm : VPatBinary<intrinsic, instruction # "_VX_" # vti.LMul.MX,4905 vti.Vector, vti.Vector, XLenVT, vti.Mask,4906 vti.Log2SEW, vti.RegClass,4907 vti.RegClass, GPR>;4908 }4909}4910 4911multiclass VPatBinaryV_VI<string intrinsic, string instruction,4912 list<VTypeInfo> vtilist, Operand imm_type> {4913 foreach vti = vtilist in4914 let Predicates = GetVTypePredicates<vti>.Predicates in4915 defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX,4916 vti.Vector, vti.Vector, XLenVT, vti.Mask,4917 vti.Log2SEW, vti.RegClass,4918 vti.RegClass, imm_type>;4919}4920 4921multiclass VPatBinaryV_VI_RM<string intrinsic, string instruction,4922 list<VTypeInfo> vtilist,4923 Operand imm_type> {4924 foreach vti = vtilist in4925 let Predicates = GetVTypePredicates<vti>.Predicates in4926 defm : VPatBinaryRoundingMode<intrinsic,4927 instruction # "_VI_" # vti.LMul.MX,4928 vti.Vector, vti.Vector, XLenVT, vti.Mask,4929 vti.Log2SEW, vti.RegClass,4930 vti.RegClass, imm_type>;4931}4932 4933multiclass VPatBinaryV_VI_INT<string intrinsic, string instruction,4934 list<VTypeInfo> vtilist, Operand imm_type> {4935 foreach vti = vtilist in {4936 defvar ivti = GetIntVTypeInfo<vti>.Vti;4937 let Predicates = GetVTypePredicates<ivti>.Predicates in4938 defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX,4939 vti.Vector, vti.Vector, XLenVT, vti.Mask,4940 vti.Log2SEW, vti.RegClass,4941 vti.RegClass, imm_type>;4942 }4943}4944 4945multiclass VPatBinaryM_MM<string intrinsic, string instruction> {4946 foreach mti = AllMasks in4947 let Predicates = [HasVInstructions] in4948 def : VPatBinaryM<intrinsic, instruction # "_MM_" # mti.BX,4949 mti.Mask, mti.Mask, mti.Mask,4950 mti.Log2SEW, VR, VR>;4951}4952 4953multiclass VPatBinaryW_VV<string intrinsic, string instruction,4954 list<VTypeInfoToWide> vtilist> {4955 foreach VtiToWti = vtilist in {4956 defvar Vti = VtiToWti.Vti;4957 defvar Wti = VtiToWti.Wti;4958 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,4959 GetVTypePredicates<Wti>.Predicates) in4960 defm : VPatBinary<intrinsic, instruction # "_VV_" # Vti.LMul.MX,4961 Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask,4962 Vti.Log2SEW, Wti.RegClass,4963 Vti.RegClass, Vti.RegClass>;4964 }4965}4966 4967multiclass VPatBinaryW_VV_RM<string intrinsic, string instruction,4968 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {4969 foreach VtiToWti = vtilist in {4970 defvar Vti = VtiToWti.Vti;4971 defvar Wti = VtiToWti.Wti;4972 defvar name = !if(isSEWAware,4973 instruction # "_VV_" # Vti.LMul.MX # "_E" # Vti.SEW,4974 instruction # "_VV_" # Vti.LMul.MX);4975 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,4976 GetVTypePredicates<Wti>.Predicates) in4977 defm : VPatBinaryRoundingMode<intrinsic, name,4978 Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask,4979 Vti.Log2SEW, Wti.RegClass,4980 Vti.RegClass, Vti.RegClass>;4981 }4982}4983 4984multiclass VPatBinaryW_VX<string intrinsic, string instruction,4985 list<VTypeInfoToWide> vtilist> {4986 foreach VtiToWti = vtilist in {4987 defvar Vti = VtiToWti.Vti;4988 defvar Wti = VtiToWti.Wti;4989 defvar kind = "V"#Vti.ScalarSuffix;4990 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,4991 GetVTypePredicates<Wti>.Predicates) in4992 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,4993 Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask,4994 Vti.Log2SEW, Wti.RegClass,4995 Vti.RegClass, Vti.ScalarRegClass>;4996 }4997}4998 4999multiclass VPatBinaryW_VX_RM<string intrinsic, string instruction,5000 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {5001 foreach VtiToWti = vtilist in {5002 defvar Vti = VtiToWti.Vti;5003 defvar Wti = VtiToWti.Wti;5004 defvar kind = "V"#Vti.ScalarSuffix;5005 defvar name = !if(isSEWAware,5006 instruction#"_"#kind#"_"#Vti.LMul.MX # "_E" # Vti.SEW,5007 instruction#"_"#kind#"_"#Vti.LMul.MX);5008 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5009 GetVTypePredicates<Wti>.Predicates) in5010 defm : VPatBinaryRoundingMode<intrinsic, name,5011 Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask,5012 Vti.Log2SEW, Wti.RegClass,5013 Vti.RegClass, Vti.ScalarRegClass>;5014 }5015}5016 5017multiclass VPatBinaryW_WV<string intrinsic, string instruction,5018 list<VTypeInfoToWide> vtilist> {5019 foreach VtiToWti = vtilist in {5020 defvar Vti = VtiToWti.Vti;5021 defvar Wti = VtiToWti.Wti;5022 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5023 GetVTypePredicates<Wti>.Predicates) in {5024 def : VPatTiedBinaryNoMask<intrinsic, instruction # "_WV_" # Vti.LMul.MX,5025 Wti.Vector, Vti.Vector,5026 Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;5027 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_WV_" # Vti.LMul.MX,5028 Wti.Vector, Wti.Vector, Vti.Vector, Vti.Log2SEW,5029 Wti.RegClass, Wti.RegClass, Vti.RegClass>;5030 let AddedComplexity = 1 in {5031 def : VPatTiedBinaryNoMaskTU<intrinsic, instruction # "_WV_" # Vti.LMul.MX,5032 Wti.Vector, Vti.Vector,5033 Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;5034 def : VPatTiedBinaryMask<intrinsic, instruction # "_WV_" # Vti.LMul.MX,5035 Wti.Vector, Vti.Vector, Vti.Mask,5036 Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;5037 }5038 def : VPatBinaryMaskPolicy<intrinsic, instruction # "_WV_" # Vti.LMul.MX,5039 Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,5040 Vti.Log2SEW, Wti.RegClass,5041 Wti.RegClass, Vti.RegClass>;5042 }5043 }5044}5045 5046multiclass VPatBinaryW_WV_RM<string intrinsic, string instruction,5047 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {5048 foreach VtiToWti = vtilist in {5049 defvar Vti = VtiToWti.Vti;5050 defvar Wti = VtiToWti.Wti;5051 defvar name = !if(isSEWAware,5052 instruction # "_WV_" # Vti.LMul.MX # "_E" # Vti.SEW,5053 instruction # "_WV_" # Vti.LMul.MX);5054 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5055 GetVTypePredicates<Wti>.Predicates) in {5056 def : VPatTiedBinaryNoMaskRoundingMode<intrinsic, name,5057 Wti.Vector, Vti.Vector,5058 Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;5059 def : VPatBinaryNoMaskTURoundingMode<intrinsic, name,5060 Wti.Vector, Wti.Vector, Vti.Vector, Vti.Log2SEW,5061 Wti.RegClass, Wti.RegClass, Vti.RegClass>;5062 let AddedComplexity = 1 in {5063 def : VPatTiedBinaryNoMaskTURoundingMode<intrinsic, name,5064 Wti.Vector, Vti.Vector,5065 Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;5066 def : VPatTiedBinaryMaskRoundingMode<intrinsic, name,5067 Wti.Vector, Vti.Vector, Vti.Mask,5068 Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;5069 }5070 def : VPatBinaryMaskPolicyRoundingMode<intrinsic, name,5071 Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,5072 Vti.Log2SEW, Wti.RegClass,5073 Wti.RegClass, Vti.RegClass>;5074 }5075 }5076}5077 5078multiclass VPatBinaryW_WX<string intrinsic, string instruction,5079 list<VTypeInfoToWide> vtilist> {5080 foreach VtiToWti = vtilist in {5081 defvar Vti = VtiToWti.Vti;5082 defvar Wti = VtiToWti.Wti;5083 defvar kind = "W"#Vti.ScalarSuffix;5084 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5085 GetVTypePredicates<Wti>.Predicates) in5086 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,5087 Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,5088 Vti.Log2SEW, Wti.RegClass,5089 Wti.RegClass, Vti.ScalarRegClass>;5090 }5091}5092 5093multiclass VPatBinaryW_WX_RM<string intrinsic, string instruction,5094 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {5095 foreach VtiToWti = vtilist in {5096 defvar Vti = VtiToWti.Vti;5097 defvar Wti = VtiToWti.Wti;5098 defvar kind = "W"#Vti.ScalarSuffix;5099 defvar name = !if(isSEWAware,5100 instruction#"_"#kind#"_"#Vti.LMul.MX#"_E"#Vti.SEW,5101 instruction#"_"#kind#"_"#Vti.LMul.MX);5102 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5103 GetVTypePredicates<Wti>.Predicates) in5104 defm : VPatBinaryRoundingMode<intrinsic, name,5105 Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,5106 Vti.Log2SEW, Wti.RegClass,5107 Wti.RegClass, Vti.ScalarRegClass>;5108 }5109}5110 5111multiclass VPatBinaryV_WV<string intrinsic, string instruction,5112 list<VTypeInfoToWide> vtilist> {5113 foreach VtiToWti = vtilist in {5114 defvar Vti = VtiToWti.Vti;5115 defvar Wti = VtiToWti.Wti;5116 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5117 GetVTypePredicates<Wti>.Predicates) in5118 defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX,5119 Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,5120 Vti.Log2SEW, Vti.RegClass,5121 Wti.RegClass, Vti.RegClass>;5122 }5123}5124 5125multiclass VPatBinaryV_WV_RM<string intrinsic, string instruction,5126 list<VTypeInfoToWide> vtilist> {5127 foreach VtiToWti = vtilist in {5128 defvar Vti = VtiToWti.Vti;5129 defvar Wti = VtiToWti.Wti;5130 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5131 GetVTypePredicates<Wti>.Predicates) in5132 defm : VPatBinaryRoundingMode<intrinsic,5133 instruction # "_WV_" # Vti.LMul.MX,5134 Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,5135 Vti.Log2SEW, Vti.RegClass,5136 Wti.RegClass, Vti.RegClass>;5137 }5138}5139 5140multiclass VPatBinaryV_WX<string intrinsic, string instruction,5141 list<VTypeInfoToWide> vtilist> {5142 foreach VtiToWti = vtilist in {5143 defvar Vti = VtiToWti.Vti;5144 defvar Wti = VtiToWti.Wti;5145 defvar kind = "W"#Vti.ScalarSuffix;5146 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5147 GetVTypePredicates<Wti>.Predicates) in5148 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,5149 Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,5150 Vti.Log2SEW, Vti.RegClass,5151 Wti.RegClass, Vti.ScalarRegClass>;5152 }5153}5154 5155multiclass VPatBinaryV_WX_RM<string intrinsic, string instruction,5156 list<VTypeInfoToWide> vtilist> {5157 foreach VtiToWti = vtilist in {5158 defvar Vti = VtiToWti.Vti;5159 defvar Wti = VtiToWti.Wti;5160 defvar kind = "W"#Vti.ScalarSuffix;5161 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5162 GetVTypePredicates<Wti>.Predicates) in5163 defm : VPatBinaryRoundingMode<intrinsic,5164 instruction#"_"#kind#"_"#Vti.LMul.MX,5165 Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,5166 Vti.Log2SEW, Vti.RegClass,5167 Wti.RegClass, Vti.ScalarRegClass>;5168 }5169}5170 5171 5172multiclass VPatBinaryV_WI<string intrinsic, string instruction,5173 list<VTypeInfoToWide> vtilist> {5174 foreach VtiToWti = vtilist in {5175 defvar Vti = VtiToWti.Vti;5176 defvar Wti = VtiToWti.Wti;5177 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5178 GetVTypePredicates<Wti>.Predicates) in5179 defm : VPatBinary<intrinsic, instruction # "_WI_" # Vti.LMul.MX,5180 Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,5181 Vti.Log2SEW, Vti.RegClass,5182 Wti.RegClass, uimm5>;5183 }5184}5185 5186multiclass VPatBinaryV_WI_RM<string intrinsic, string instruction,5187 list<VTypeInfoToWide> vtilist> {5188 foreach VtiToWti = vtilist in {5189 defvar Vti = VtiToWti.Vti;5190 defvar Wti = VtiToWti.Wti;5191 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,5192 GetVTypePredicates<Wti>.Predicates) in5193 defm : VPatBinaryRoundingMode<intrinsic,5194 instruction # "_WI_" # Vti.LMul.MX,5195 Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,5196 Vti.Log2SEW, Vti.RegClass,5197 Wti.RegClass, uimm5>;5198 }5199}5200 5201multiclass VPatBinaryV_VM<string intrinsic, string instruction,5202 bit CarryOut = 0,5203 list<VTypeInfo> vtilist = AllIntegerVectors> {5204 foreach vti = vtilist in5205 let Predicates = GetVTypePredicates<vti>.Predicates in5206 defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM",5207 !if(CarryOut, vti.Mask, vti.Vector),5208 vti.Vector, vti.Vector, vti.Mask,5209 vti.Log2SEW, vti.LMul,5210 vti.RegClass, vti.RegClass>;5211}5212 5213multiclass VPatBinaryV_XM<string intrinsic, string instruction,5214 bit CarryOut = 0,5215 list<VTypeInfo> vtilist = AllIntegerVectors> {5216 foreach vti = vtilist in5217 let Predicates = GetVTypePredicates<vti>.Predicates in5218 defm : VPatBinaryCarryIn<intrinsic, instruction,5219 "V"#vti.ScalarSuffix#"M",5220 !if(CarryOut, vti.Mask, vti.Vector),5221 vti.Vector, vti.Scalar, vti.Mask,5222 vti.Log2SEW, vti.LMul,5223 vti.RegClass, vti.ScalarRegClass>;5224}5225 5226multiclass VPatBinaryV_IM<string intrinsic, string instruction,5227 bit CarryOut = 0> {5228 foreach vti = AllIntegerVectors in5229 let Predicates = GetVTypePredicates<vti>.Predicates in5230 defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM",5231 !if(CarryOut, vti.Mask, vti.Vector),5232 vti.Vector, XLenVT, vti.Mask,5233 vti.Log2SEW, vti.LMul,5234 vti.RegClass, simm5>;5235}5236 5237multiclass VPatBinaryV_VM_TAIL<string intrinsic, string instruction> {5238 foreach vti = AllIntegerVectors in5239 let Predicates = GetVTypePredicates<vti>.Predicates in5240 defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VVM",5241 vti.Vector,5242 vti.Vector, vti.Vector, vti.Mask,5243 vti.Log2SEW, vti.LMul, vti.RegClass,5244 vti.RegClass, vti.RegClass>;5245}5246 5247multiclass VPatBinaryV_XM_TAIL<string intrinsic, string instruction> {5248 foreach vti = AllIntegerVectors in5249 let Predicates = GetVTypePredicates<vti>.Predicates in5250 defm : VPatBinaryCarryInTAIL<intrinsic, instruction,5251 "V"#vti.ScalarSuffix#"M",5252 vti.Vector,5253 vti.Vector, vti.Scalar, vti.Mask,5254 vti.Log2SEW, vti.LMul, vti.RegClass,5255 vti.RegClass, vti.ScalarRegClass>;5256}5257 5258multiclass VPatBinaryV_IM_TAIL<string intrinsic, string instruction> {5259 foreach vti = AllIntegerVectors in5260 let Predicates = GetVTypePredicates<vti>.Predicates in5261 defm : VPatBinaryCarryInTAIL<intrinsic, instruction, "VIM",5262 vti.Vector,5263 vti.Vector, XLenVT, vti.Mask,5264 vti.Log2SEW, vti.LMul,5265 vti.RegClass, vti.RegClass, simm5>;5266}5267 5268multiclass VPatBinaryV_V<string intrinsic, string instruction> {5269 foreach vti = AllIntegerVectors in5270 let Predicates = GetVTypePredicates<vti>.Predicates in5271 defm : VPatBinaryMaskOut<intrinsic, instruction, "VV",5272 vti.Mask, vti.Vector, vti.Vector,5273 vti.Log2SEW, vti.LMul,5274 vti.RegClass, vti.RegClass>;5275}5276 5277multiclass VPatBinaryV_X<string intrinsic, string instruction> {5278 foreach vti = AllIntegerVectors in5279 let Predicates = GetVTypePredicates<vti>.Predicates in5280 defm : VPatBinaryMaskOut<intrinsic, instruction, "VX",5281 vti.Mask, vti.Vector, XLenVT,5282 vti.Log2SEW, vti.LMul,5283 vti.RegClass, GPR>;5284}5285 5286multiclass VPatBinaryV_I<string intrinsic, string instruction> {5287 foreach vti = AllIntegerVectors in5288 let Predicates = GetVTypePredicates<vti>.Predicates in5289 defm : VPatBinaryMaskOut<intrinsic, instruction, "VI",5290 vti.Mask, vti.Vector, XLenVT,5291 vti.Log2SEW, vti.LMul,5292 vti.RegClass, simm5>;5293}5294 5295multiclass VPatBinaryM_VV<string intrinsic, string instruction,5296 list<VTypeInfo> vtilist> {5297 foreach vti = vtilist in5298 let Predicates = GetVTypePredicates<vti>.Predicates in5299 defm : VPatBinaryM<intrinsic, instruction # "_VV_" # vti.LMul.MX,5300 vti.Mask, vti.Vector, vti.Vector, vti.Mask,5301 vti.Log2SEW, VR,5302 vti.RegClass, vti.RegClass>;5303}5304 5305multiclass VPatBinarySwappedM_VV<string intrinsic, string instruction,5306 list<VTypeInfo> vtilist> {5307 foreach vti = vtilist in5308 let Predicates = GetVTypePredicates<vti>.Predicates in5309 defm : VPatBinaryMSwapped<intrinsic, instruction # "_VV_" # vti.LMul.MX,5310 vti.Mask, vti.Vector, vti.Vector, vti.Mask,5311 vti.Log2SEW, VR,5312 vti.RegClass, vti.RegClass>;5313}5314 5315multiclass VPatBinaryM_VX<string intrinsic, string instruction,5316 list<VTypeInfo> vtilist> {5317 foreach vti = vtilist in {5318 defvar kind = "V"#vti.ScalarSuffix;5319 let Predicates = GetVTypePredicates<vti>.Predicates in5320 defm : VPatBinaryM<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX,5321 vti.Mask, vti.Vector, vti.Scalar, vti.Mask,5322 vti.Log2SEW, VR,5323 vti.RegClass, vti.ScalarRegClass>;5324 }5325}5326 5327multiclass VPatBinaryM_VI<string intrinsic, string instruction,5328 list<VTypeInfo> vtilist> {5329 foreach vti = vtilist in5330 let Predicates = GetVTypePredicates<vti>.Predicates in5331 defm : VPatBinaryM<intrinsic, instruction # "_VI_" # vti.LMul.MX,5332 vti.Mask, vti.Vector, XLenVT, vti.Mask,5333 vti.Log2SEW, VR,5334 vti.RegClass, simm5>;5335}5336 5337multiclass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction,5338 list<VTypeInfo> vtilist, Operand ImmType = simm5>5339 : VPatBinaryV_VV<intrinsic, instruction, vtilist>,5340 VPatBinaryV_VX<intrinsic, instruction, vtilist>,5341 VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;5342 5343multiclass VPatBinaryV_VV_VX_VI_RM<string intrinsic, string instruction,5344 list<VTypeInfo> vtilist, Operand ImmType>5345 : VPatBinaryV_VV_RM<intrinsic, instruction, vtilist>,5346 VPatBinaryV_VX_RM<intrinsic, instruction, vtilist>,5347 VPatBinaryV_VI_RM<intrinsic, instruction, vtilist, ImmType>;5348 5349multiclass VPatBinaryV_VV_VX<string intrinsic, string instruction,5350 list<VTypeInfo> vtilist, bit isSEWAware = 0>5351 : VPatBinaryV_VV<intrinsic, instruction, vtilist, isSEWAware>,5352 VPatBinaryV_VX<intrinsic, instruction, vtilist, isSEWAware>;5353 5354multiclass VPatBinaryV_VV_VX_RM<string intrinsic, string instruction,5355 list<VTypeInfo> vtilist, bit isSEWAware = 0>5356 : VPatBinaryV_VV_RM<intrinsic, instruction, vtilist, isSEWAware>,5357 VPatBinaryV_VX_RM<intrinsic, instruction, vtilist, isSEWAware>;5358 5359multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction,5360 list<VTypeInfo> vtilist>5361 : VPatBinaryV_VX<intrinsic, instruction, vtilist>,5362 VPatBinaryV_VI<intrinsic, instruction, vtilist, simm5>;5363 5364multiclass VPatBinaryW_VV_VX<string intrinsic, string instruction,5365 list<VTypeInfoToWide> vtilist>5366 : VPatBinaryW_VV<intrinsic, instruction, vtilist>,5367 VPatBinaryW_VX<intrinsic, instruction, vtilist>;5368 5369multiclass5370 VPatBinaryW_VV_VX_RM<string intrinsic, string instruction,5371 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0>5372 : VPatBinaryW_VV_RM<intrinsic, instruction, vtilist, isSEWAware>,5373 VPatBinaryW_VX_RM<intrinsic, instruction, vtilist, isSEWAware>;5374 5375multiclass VPatBinaryW_WV_WX<string intrinsic, string instruction,5376 list<VTypeInfoToWide> vtilist>5377 : VPatBinaryW_WV<intrinsic, instruction, vtilist>,5378 VPatBinaryW_WX<intrinsic, instruction, vtilist>;5379 5380multiclass5381 VPatBinaryW_WV_WX_RM<string intrinsic, string instruction,5382 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0>5383 : VPatBinaryW_WV_RM<intrinsic, instruction, vtilist, isSEWAware>,5384 VPatBinaryW_WX_RM<intrinsic, instruction, vtilist, isSEWAware>;5385 5386multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction,5387 list<VTypeInfoToWide> vtilist>5388 : VPatBinaryV_WV<intrinsic, instruction, vtilist>,5389 VPatBinaryV_WX<intrinsic, instruction, vtilist>,5390 VPatBinaryV_WI<intrinsic, instruction, vtilist>;5391 5392multiclass VPatBinaryV_WV_WX_WI_RM<string intrinsic, string instruction,5393 list<VTypeInfoToWide> vtilist>5394 : VPatBinaryV_WV_RM<intrinsic, instruction, vtilist>,5395 VPatBinaryV_WX_RM<intrinsic, instruction, vtilist>,5396 VPatBinaryV_WI_RM<intrinsic, instruction, vtilist>;5397 5398multiclass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction>5399 : VPatBinaryV_VM_TAIL<intrinsic, instruction>,5400 VPatBinaryV_XM_TAIL<intrinsic, instruction>,5401 VPatBinaryV_IM_TAIL<intrinsic, instruction>;5402 5403multiclass VPatBinaryM_VM_XM_IM<string intrinsic, string instruction>5404 : VPatBinaryV_VM<intrinsic, instruction, CarryOut=1>,5405 VPatBinaryV_XM<intrinsic, instruction, CarryOut=1>,5406 VPatBinaryV_IM<intrinsic, instruction, CarryOut=1>;5407 5408multiclass VPatBinaryM_V_X_I<string intrinsic, string instruction>5409 : VPatBinaryV_V<intrinsic, instruction>,5410 VPatBinaryV_X<intrinsic, instruction>,5411 VPatBinaryV_I<intrinsic, instruction>;5412 5413multiclass VPatBinaryV_VM_XM<string intrinsic, string instruction>5414 : VPatBinaryV_VM_TAIL<intrinsic, instruction>,5415 VPatBinaryV_XM_TAIL<intrinsic, instruction>;5416 5417multiclass VPatBinaryM_VM_XM<string intrinsic, string instruction>5418 : VPatBinaryV_VM<intrinsic, instruction, CarryOut=1>,5419 VPatBinaryV_XM<intrinsic, instruction, CarryOut=1>;5420 5421multiclass VPatBinaryM_V_X<string intrinsic, string instruction>5422 : VPatBinaryV_V<intrinsic, instruction>,5423 VPatBinaryV_X<intrinsic, instruction>;5424 5425multiclass VPatTernaryWithPolicy<string intrinsic,5426 string inst,5427 string kind,5428 ValueType result_type,5429 ValueType op1_type,5430 ValueType op2_type,5431 ValueType mask_type,5432 int sew,5433 LMULInfo vlmul,5434 VReg result_reg_class,5435 RegisterClass op1_reg_class,5436 DAGOperand op2_kind> {5437 def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type,5438 op2_type, sew, vlmul, result_reg_class,5439 op1_reg_class, op2_kind>;5440 def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type,5441 mask_type, sew, vlmul, result_reg_class, op1_reg_class,5442 op2_kind>;5443}5444 5445multiclass VPatTernaryWithPolicyRoundingMode<string intrinsic,5446 string inst,5447 string kind,5448 ValueType result_type,5449 ValueType op1_type,5450 ValueType op2_type,5451 ValueType mask_type,5452 int sew,5453 LMULInfo vlmul,5454 VReg result_reg_class,5455 RegisterClass op1_reg_class,5456 DAGOperand op2_kind,5457 bit isSEWAware = 0> {5458 def : VPatTernaryNoMaskWithPolicyRoundingMode<intrinsic, inst, kind, result_type,5459 op1_type, op2_type, sew, vlmul,5460 result_reg_class, op1_reg_class,5461 op2_kind, isSEWAware>;5462 def : VPatTernaryMaskPolicyRoundingMode<intrinsic, inst, kind, result_type, op1_type,5463 op2_type, mask_type, sew, vlmul,5464 result_reg_class, op1_reg_class,5465 op2_kind, isSEWAware>;5466}5467 5468multiclass VPatTernaryTU<string intrinsic,5469 string inst,5470 string kind,5471 ValueType result_type,5472 ValueType op1_type,5473 ValueType op2_type,5474 ValueType mask_type,5475 int log2sew,5476 LMULInfo vlmul,5477 VReg result_reg_class,5478 RegisterClass op1_reg_class,5479 DAGOperand op2_kind> {5480 def : VPatTernaryNoMaskTU<intrinsic, inst, kind, result_type, op1_type,5481 op2_type, log2sew, vlmul, result_reg_class,5482 op1_reg_class, op2_kind>;5483 def : VPatTernaryMaskTU<intrinsic, inst, kind, result_type, op1_type,5484 op2_type, mask_type, log2sew, vlmul,5485 result_reg_class, op1_reg_class, op2_kind>;5486}5487 5488multiclass VPatTernaryTURoundingMode<string intrinsic,5489 string inst,5490 string kind,5491 ValueType result_type,5492 ValueType op1_type,5493 ValueType op2_type,5494 ValueType mask_type,5495 int log2sew,5496 LMULInfo vlmul,5497 VReg result_reg_class,5498 RegisterClass op1_reg_class,5499 DAGOperand op2_kind> {5500 def : VPatTernaryNoMaskTURoundingMode<intrinsic, inst, kind, result_type, op1_type,5501 op2_type, log2sew, vlmul, result_reg_class,5502 op1_reg_class, op2_kind>;5503 def : VPatTernaryMaskTURoundingMode<intrinsic, inst, kind, result_type, op1_type,5504 op2_type, mask_type, log2sew, vlmul,5505 result_reg_class, op1_reg_class, op2_kind>;5506}5507 5508multiclass VPatTernaryV_VV_AAXA<string intrinsic, string instruction,5509 list<VTypeInfo> vtilist> {5510 foreach vti = vtilist in5511 let Predicates = GetVTypePredicates<vti>.Predicates in5512 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",5513 vti.Vector, vti.Vector, vti.Vector, vti.Mask,5514 vti.Log2SEW, vti.LMul, vti.RegClass,5515 vti.RegClass, vti.RegClass>;5516}5517 5518multiclass VPatTernaryV_VV_AAXA_RM<string intrinsic, string instruction,5519 list<VTypeInfo> vtilist, bit isSEWAware = 0> {5520 foreach vti = vtilist in5521 let Predicates = GetVTypePredicates<vti>.Predicates in5522 defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, "VV",5523 vti.Vector, vti.Vector, vti.Vector, vti.Mask,5524 vti.Log2SEW, vti.LMul, vti.RegClass,5525 vti.RegClass, vti.RegClass, isSEWAware>;5526}5527 5528multiclass VPatTernaryV_VX<string intrinsic, string instruction,5529 list<VTypeInfo> vtilist> {5530 foreach vti = vtilist in {5531 defvar ivti = GetIntVTypeInfo<vti>.Vti;5532 let Predicates = GetVTypePredicates<ivti>.Predicates in5533 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VX",5534 vti.Vector, vti.Vector, XLenVT, vti.Mask,5535 vti.Log2SEW, vti.LMul, vti.RegClass,5536 vti.RegClass, GPR>;5537 }5538}5539 5540multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction,5541 list<VTypeInfo> vtilist> {5542 foreach vti = vtilist in5543 let Predicates = GetVTypePredicates<vti>.Predicates in5544 defm : VPatTernaryWithPolicy<intrinsic, instruction,5545 "V"#vti.ScalarSuffix,5546 vti.Vector, vti.Scalar, vti.Vector, vti.Mask,5547 vti.Log2SEW, vti.LMul, vti.RegClass,5548 vti.ScalarRegClass, vti.RegClass>;5549}5550 5551multiclass VPatTernaryV_VX_AAXA_RM<string intrinsic, string instruction,5552 list<VTypeInfo> vtilist, bit isSEWAware = 0> {5553 foreach vti = vtilist in5554 let Predicates = GetVTypePredicates<vti>.Predicates in5555 defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction,5556 "V"#vti.ScalarSuffix,5557 vti.Vector, vti.Scalar, vti.Vector, vti.Mask,5558 vti.Log2SEW, vti.LMul, vti.RegClass,5559 vti.ScalarRegClass, vti.RegClass, isSEWAware>;5560}5561 5562multiclass VPatTernaryV_VI<string intrinsic, string instruction,5563 list<VTypeInfo> vtilist, Operand Imm_type> {5564 foreach vti = vtilist in {5565 defvar ivti = GetIntVTypeInfo<vti>.Vti;5566 let Predicates = GetVTypePredicates<ivti>.Predicates in5567 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VI",5568 vti.Vector, vti.Vector, XLenVT, vti.Mask,5569 vti.Log2SEW, vti.LMul, vti.RegClass,5570 vti.RegClass, Imm_type>;5571 }5572}5573 5574multiclass VPatTernaryW_VV<string intrinsic, string instruction,5575 list<VTypeInfoToWide> vtilist> {5576 foreach vtiToWti = vtilist in {5577 defvar vti = vtiToWti.Vti;5578 defvar wti = vtiToWti.Wti;5579 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5580 GetVTypePredicates<wti>.Predicates) in5581 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",5582 wti.Vector, vti.Vector, vti.Vector,5583 vti.Mask, vti.Log2SEW, vti.LMul,5584 wti.RegClass, vti.RegClass, vti.RegClass>;5585 }5586}5587 5588multiclass VPatTernaryW_VV_RM<string intrinsic, string instruction,5589 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {5590 foreach vtiToWti = vtilist in {5591 defvar vti = vtiToWti.Vti;5592 defvar wti = vtiToWti.Wti;5593 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5594 GetVTypePredicates<wti>.Predicates) in5595 defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, "VV",5596 wti.Vector, vti.Vector, vti.Vector,5597 vti.Mask, vti.Log2SEW, vti.LMul,5598 wti.RegClass, vti.RegClass,5599 vti.RegClass, isSEWAware>;5600 }5601}5602 5603multiclass VPatTernaryW_VX<string intrinsic, string instruction,5604 list<VTypeInfoToWide> vtilist> {5605 foreach vtiToWti = vtilist in {5606 defvar vti = vtiToWti.Vti;5607 defvar wti = vtiToWti.Wti;5608 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5609 GetVTypePredicates<wti>.Predicates) in5610 defm : VPatTernaryWithPolicy<intrinsic, instruction,5611 "V"#vti.ScalarSuffix,5612 wti.Vector, vti.Scalar, vti.Vector,5613 vti.Mask, vti.Log2SEW, vti.LMul,5614 wti.RegClass, vti.ScalarRegClass, vti.RegClass>;5615 }5616}5617 5618multiclass5619 VPatTernaryW_VX_RM<string intrinsic, string instruction,5620 list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {5621 foreach vtiToWti = vtilist in {5622 defvar vti = vtiToWti.Vti;5623 defvar wti = vtiToWti.Wti;5624 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5625 GetVTypePredicates<wti>.Predicates) in defm5626 : VPatTernaryWithPolicyRoundingMode<5627 intrinsic, instruction, "V" #vti.ScalarSuffix, wti.Vector,5628 vti.Scalar, vti.Vector, vti.Mask, vti.Log2SEW, vti.LMul,5629 wti.RegClass, vti.ScalarRegClass, vti.RegClass, isSEWAware>;5630 }5631}5632 5633multiclass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction,5634 list<VTypeInfo> vtilist>5635 : VPatTernaryV_VV_AAXA<intrinsic, instruction, vtilist>,5636 VPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>;5637 5638multiclass VPatTernaryV_VV_VX_AAXA_RM<string intrinsic, string instruction,5639 list<VTypeInfo> vtilist, bit isSEWAware = 0>5640 : VPatTernaryV_VV_AAXA_RM<intrinsic, instruction, vtilist, isSEWAware>,5641 VPatTernaryV_VX_AAXA_RM<intrinsic, instruction, vtilist, isSEWAware>;5642 5643multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction,5644 list<VTypeInfo> vtilist, Operand Imm_type>5645 : VPatTernaryV_VX<intrinsic, instruction, vtilist>,5646 VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>;5647 5648 5649multiclass VPatBinaryM_VV_VX_VI<string intrinsic, string instruction,5650 list<VTypeInfo> vtilist>5651 : VPatBinaryM_VV<intrinsic, instruction, vtilist>,5652 VPatBinaryM_VX<intrinsic, instruction, vtilist>,5653 VPatBinaryM_VI<intrinsic, instruction, vtilist>;5654 5655multiclass VPatTernaryW_VV_VX<string intrinsic, string instruction,5656 list<VTypeInfoToWide> vtilist>5657 : VPatTernaryW_VV<intrinsic, instruction, vtilist>,5658 VPatTernaryW_VX<intrinsic, instruction, vtilist>;5659 5660multiclass VPatTernaryW_VV_VX_RM<string intrinsic, string instruction,5661 list<VTypeInfoToWide> vtilist, bit isSEWAware = 1>5662 : VPatTernaryW_VV_RM<intrinsic, instruction, vtilist, isSEWAware>,5663 VPatTernaryW_VX_RM<intrinsic, instruction, vtilist, isSEWAware>;5664 5665multiclass VPatBinaryM_VV_VX<string intrinsic, string instruction,5666 list<VTypeInfo> vtilist>5667 : VPatBinaryM_VV<intrinsic, instruction, vtilist>,5668 VPatBinaryM_VX<intrinsic, instruction, vtilist>;5669 5670multiclass VPatBinaryM_VX_VI<string intrinsic, string instruction,5671 list<VTypeInfo> vtilist>5672 : VPatBinaryM_VX<intrinsic, instruction, vtilist>,5673 VPatBinaryM_VI<intrinsic, instruction, vtilist>;5674 5675multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,5676 list<VTypeInfo> vtilist, Operand ImmType>5677 : VPatBinaryV_VV_INT<intrinsic#"_vv", instruction, vtilist>,5678 VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>,5679 VPatBinaryV_VI_INT<intrinsic#"_vx", instruction, vtilist, ImmType>;5680 5681multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat = 0> {5682 foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in {5683 defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1");5684 let Predicates = GetVTypePredicates<vti>.Predicates in5685 defm : VPatTernaryTU<intrinsic, instruction, "VS",5686 vectorM1.Vector, vti.Vector,5687 vectorM1.Vector, vti.Mask,5688 vti.Log2SEW, vti.LMul,5689 VR, vti.RegClass, VR>;5690 }5691 foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in {5692 let Predicates = GetVTypePredicates<gvti>.Predicates in5693 defm : VPatTernaryTU<intrinsic, instruction, "VS",5694 gvti.VectorM1, gvti.Vector,5695 gvti.VectorM1, gvti.Mask,5696 gvti.Log2SEW, gvti.LMul,5697 VR, gvti.RegClass, VR>;5698 }5699}5700 5701multiclass VPatReductionV_VS_RM<string intrinsic, string instruction, bit IsFloat = 0> {5702 foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in {5703 defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1");5704 let Predicates = GetVTypePredicates<vti>.Predicates in5705 defm : VPatTernaryTURoundingMode<intrinsic, instruction, "VS",5706 vectorM1.Vector, vti.Vector,5707 vectorM1.Vector, vti.Mask,5708 vti.Log2SEW, vti.LMul,5709 VR, vti.RegClass, VR>;5710 }5711 foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in {5712 let Predicates = GetVTypePredicates<gvti>.Predicates in5713 defm : VPatTernaryTURoundingMode<intrinsic, instruction, "VS",5714 gvti.VectorM1, gvti.Vector,5715 gvti.VectorM1, gvti.Mask,5716 gvti.Log2SEW, gvti.LMul,5717 VR, gvti.RegClass, VR>;5718 }5719}5720 5721multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> {5722 foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in {5723 defvar wtiSEW = !mul(vti.SEW, 2);5724 if !le(wtiSEW, 64) then {5725 defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1");5726 let Predicates = GetVTypePredicates<vti>.Predicates in5727 defm : VPatTernaryTU<intrinsic, instruction, "VS",5728 wtiM1.Vector, vti.Vector,5729 wtiM1.Vector, vti.Mask,5730 vti.Log2SEW, vti.LMul,5731 wtiM1.RegClass, vti.RegClass,5732 wtiM1.RegClass>;5733 }5734 }5735}5736 5737multiclass VPatReductionW_VS_RM<string intrinsic, string instruction, bit IsFloat = 0> {5738 foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in {5739 defvar wtiSEW = !mul(vti.SEW, 2);5740 if !le(wtiSEW, 64) then {5741 defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1");5742 let Predicates = GetVTypePredicates<vti>.Predicates in5743 defm : VPatTernaryTURoundingMode<intrinsic, instruction, "VS",5744 wtiM1.Vector, vti.Vector,5745 wtiM1.Vector, vti.Mask,5746 vti.Log2SEW, vti.LMul,5747 wtiM1.RegClass, vti.RegClass,5748 wtiM1.RegClass>;5749 }5750 }5751}5752 5753multiclass VPatConversionVI_VF<string intrinsic,5754 string instruction> {5755 foreach fvti = AllFloatVectors in {5756 defvar ivti = GetIntVTypeInfo<fvti>.Vti;5757 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5758 GetVTypePredicates<ivti>.Predicates) in5759 defm : VPatConversion<intrinsic, instruction, "V",5760 ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,5761 fvti.LMul, ivti.RegClass, fvti.RegClass>;5762 }5763}5764 5765multiclass VPatConversionVI_VF_RM<string intrinsic,5766 string instruction> {5767 foreach fvti = AllFloatVectors in {5768 defvar ivti = GetIntVTypeInfo<fvti>.Vti;5769 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5770 GetVTypePredicates<ivti>.Predicates) in5771 defm : VPatConversionRoundingMode<intrinsic, instruction, "V",5772 ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,5773 fvti.LMul, ivti.RegClass, fvti.RegClass>;5774 }5775}5776 5777multiclass VPatConversionVI_VF_RTZ<string intrinsic, 5778 string instruction> {5779 foreach fvti = AllFloatVectors in {5780 defvar ivti = GetIntVTypeInfo<fvti>.Vti;5781 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5782 GetVTypePredicates<ivti>.Predicates) in5783 defm : VPatConversionRTZ<intrinsic, instruction, "V",5784 ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,5785 fvti.LMul, ivti.RegClass, fvti.RegClass>;5786 }5787}5788 5789multiclass VPatConversionVF_VI_RM<string intrinsic, string instruction,5790 bit isSEWAware = 0> {5791 foreach fvti = AllFloatVectors in {5792 defvar ivti = GetIntVTypeInfo<fvti>.Vti;5793 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5794 GetVTypePredicates<ivti>.Predicates) in5795 defm : VPatConversionRoundingMode<intrinsic, instruction, "V",5796 fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,5797 ivti.LMul, fvti.RegClass, ivti.RegClass,5798 isSEWAware>;5799 }5800}5801 5802multiclass VPatConversionWI_VF<string intrinsic, string instruction> {5803 foreach fvtiToFWti = AllWidenableFloatVectors in {5804 defvar fvti = fvtiToFWti.Vti;5805 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;5806 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5807 GetVTypePredicates<iwti>.Predicates) in5808 defm : VPatConversion<intrinsic, instruction, "V",5809 iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,5810 fvti.LMul, iwti.RegClass, fvti.RegClass>;5811 }5812}5813 5814multiclass VPatConversionWI_VF_RM<string intrinsic, string instruction> {5815 foreach fvtiToFWti = AllWidenableFloatVectors in {5816 defvar fvti = fvtiToFWti.Vti;5817 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;5818 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5819 GetVTypePredicates<iwti>.Predicates) in5820 defm : VPatConversionRoundingMode<intrinsic, instruction, "V",5821 iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,5822 fvti.LMul, iwti.RegClass, fvti.RegClass>;5823 }5824}5825 5826multiclass VPatConversionWI_VF_RTZ<string intrinsic, string instruction> {5827 foreach fvtiToFWti = AllWidenableFloatVectors in {5828 defvar fvti = fvtiToFWti.Vti;5829 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;5830 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5831 GetVTypePredicates<iwti>.Predicates) in5832 defm : VPatConversionRTZ<intrinsic, instruction, "V",5833 iwti.Vector, fvti.Vector, iwti.Mask, fvti.Log2SEW,5834 fvti.LMul, iwti.RegClass, fvti.RegClass>;5835 }5836}5837 5838multiclass VPatConversionWF_VI<string intrinsic, string instruction,5839 bit isSEWAware = 0> {5840 foreach vtiToWti = AllWidenableIntToFloatVectors in {5841 defvar vti = vtiToWti.Vti;5842 defvar fwti = vtiToWti.Wti;5843 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5844 GetVTypePredicates<fwti>.Predicates) in5845 defm : VPatConversion<intrinsic, instruction, "V",5846 fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,5847 vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;5848 }5849}5850 5851multiclass VPatConversionWF_VF<string intrinsic, string instruction,5852 bit isSEWAware = 0> {5853 foreach fvtiToFWti = AllWidenableFloatVectors in {5854 defvar fvti = fvtiToFWti.Vti;5855 defvar fwti = fvtiToFWti.Wti;5856 // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.5857 let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,5858 GetVTypeMinimalPredicates<fwti>.Predicates) in5859 defm : VPatConversion<intrinsic, instruction, "V",5860 fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,5861 fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;5862 }5863}5864 5865multiclass VPatConversionVI_WF<string intrinsic, string instruction> {5866 foreach vtiToWti = AllWidenableIntToFloatVectors in {5867 defvar vti = vtiToWti.Vti;5868 defvar fwti = vtiToWti.Wti;5869 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5870 GetVTypePredicates<fwti>.Predicates) in5871 defm : VPatConversion<intrinsic, instruction, "W",5872 vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,5873 vti.LMul, vti.RegClass, fwti.RegClass>;5874 }5875}5876 5877multiclass VPatConversionVI_WF_RM <string intrinsic, string instruction> {5878 foreach vtiToWti = AllWidenableIntToFloatVectors in {5879 defvar vti = vtiToWti.Vti;5880 defvar fwti = vtiToWti.Wti;5881 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5882 GetVTypePredicates<fwti>.Predicates) in5883 defm : VPatConversionRoundingMode<intrinsic, instruction, "W",5884 vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,5885 vti.LMul, vti.RegClass, fwti.RegClass>;5886 }5887}5888 5889multiclass VPatConversionVI_WF_RTZ <string intrinsic, string instruction> {5890 foreach vtiToWti = AllWidenableIntToFloatVectors in {5891 defvar vti = vtiToWti.Vti;5892 defvar fwti = vtiToWti.Wti;5893 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,5894 GetVTypePredicates<fwti>.Predicates) in5895 defm : VPatConversionRTZ<intrinsic, instruction, "W",5896 vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,5897 vti.LMul, vti.RegClass, fwti.RegClass>;5898 }5899}5900 5901multiclass VPatConversionVF_WI_RM <string intrinsic, string instruction,5902 bit isSEWAware = 0> {5903 foreach fvtiToFWti = AllWidenableFloatVectors in {5904 defvar fvti = fvtiToFWti.Vti;5905 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;5906 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5907 GetVTypePredicates<iwti>.Predicates) in5908 defm : VPatConversionRoundingMode<intrinsic, instruction, "W",5909 fvti.Vector, iwti.Vector, fvti.Mask, fvti.Log2SEW,5910 fvti.LMul, fvti.RegClass, iwti.RegClass,5911 isSEWAware>;5912 }5913}5914 5915multiclass VPatConversionVF_WF<string intrinsic, string instruction,5916 bit isSEWAware = 0> {5917 foreach fvtiToFWti = AllWidenableFloatVectors in {5918 defvar fvti = fvtiToFWti.Vti;5919 defvar fwti = fvtiToFWti.Wti;5920 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5921 GetVTypePredicates<fwti>.Predicates) in5922 defm : VPatConversion<intrinsic, instruction, "W",5923 fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,5924 fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;5925 }5926}5927 5928multiclass VPatConversionVF_WF_RM<string intrinsic, string instruction,5929 list<VTypeInfoToWide> wlist = AllWidenableFloatVectors,5930 bit isSEWAware = 0> {5931 foreach fvtiToFWti = wlist in {5932 defvar fvti = fvtiToFWti.Vti;5933 defvar fwti = fvtiToFWti.Wti;5934 // Define vfncvt.f.f.w for f16 when Zvfhmin is enable.5935 let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,5936 GetVTypeMinimalPredicates<fwti>.Predicates) in5937 defm : VPatConversionRoundingMode<intrinsic, instruction, "W",5938 fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,5939 fvti.LMul, fvti.RegClass, fwti.RegClass,5940 isSEWAware>;5941 }5942}5943 5944multiclass VPatConversionVF_WF_RTZ<string intrinsic, string instruction,5945 list<VTypeInfoToWide> wlist = AllWidenableFloatVectors,5946 bit isSEWAware = 0> {5947 foreach fvtiToFWti = wlist in {5948 defvar fvti = fvtiToFWti.Vti;5949 defvar fwti = fvtiToFWti.Wti;5950 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,5951 GetVTypePredicates<fwti>.Predicates) in5952 defm : VPatConversionRTZ<intrinsic, instruction, "W",5953 fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,5954 fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;5955 }5956}5957 5958multiclass VPatCompare_VI<string intrinsic, string inst,5959 ImmLeaf ImmType> {5960 foreach vti = AllIntegerVectors in {5961 defvar Intr = !cast<Intrinsic>(intrinsic);5962 defvar Pseudo = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX);5963 let Predicates = GetVTypePredicates<vti>.Predicates in5964 def : Pat<(vti.Mask (Intr (vti.Vector vti.RegClass:$rs1),5965 (vti.Scalar ImmType:$rs2),5966 VLOpFrag)),5967 (Pseudo vti.RegClass:$rs1, (DecImm ImmType:$rs2),5968 GPR:$vl, vti.Log2SEW)>;5969 defvar IntrMask = !cast<Intrinsic>(intrinsic # "_mask");5970 defvar PseudoMask = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX#"_MASK");5971 let Predicates = GetVTypePredicates<vti>.Predicates in5972 def : Pat<(vti.Mask (IntrMask (vti.Mask VR:$passthru),5973 (vti.Vector vti.RegClass:$rs1),5974 (vti.Scalar ImmType:$rs2),5975 (vti.Mask VMV0:$vm),5976 VLOpFrag)),5977 (PseudoMask VR:$passthru, vti.RegClass:$rs1, (DecImm ImmType:$rs2),5978 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MU)>;5979 }5980}5981 5982//===----------------------------------------------------------------------===//5983// Pseudo instructions5984//===----------------------------------------------------------------------===//5985 5986let Predicates = [HasVInstructions] in {5987 5988//===----------------------------------------------------------------------===//5989// Pseudo Instructions for CodeGen5990//===----------------------------------------------------------------------===//5991 5992let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {5993 def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins),5994 [(set GPR:$rd, (riscv_read_vlenb))]>,5995 PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVLENB.Encoding, X0)>,5996 Sched<[WriteRdVLENB]>;5997 let Defs = [VL, VTYPE] in {5998 def PseudoReadVLENBViaVSETVLIX0 : Pseudo<(outs GPRNoX0:$rd),5999 (ins uimm5:$shamt), []>,6000 Sched<[WriteVSETVLI, ReadVSETVLI]>;6001 }6002}6003 6004let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,6005 Uses = [VL] in6006def PseudoReadVL : Pseudo<(outs GPR:$rd), (ins), []>,6007 PseudoInstExpansion<(CSRRS GPR:$rd, SysRegVL.Encoding, X0)>;6008 6009foreach lmul = MxList in {6010 foreach nf = NFSet<lmul>.L in {6011 defvar vreg = SegRegClass<lmul, nf>.RC;6012 let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1,6013 Size = !mul(4, !sub(!mul(nf, 2), 1)) in {6014 def "PseudoVSPILL" # nf # "_" # lmul.MX :6015 Pseudo<(outs), (ins vreg:$rs1, GPR:$rs2), []>;6016 }6017 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1,6018 Size = !mul(4, !sub(!mul(nf, 2), 1)) in {6019 def "PseudoVRELOAD" # nf # "_" # lmul.MX :6020 Pseudo<(outs vreg:$rs1), (ins GPR:$rs2), []>;6021 }6022 }6023}6024 6025//===----------------------------------------------------------------------===//6026// 6. Configuration-Setting Instructions6027//===----------------------------------------------------------------------===//6028 6029// Pseudos.6030let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in {6031// Due to rs1=X0 having special meaning, we need a GPRNoX0 register class for6032// the when we aren't using one of the special X0 encodings. Otherwise it could6033// be accidentally be made X0 by MachineIR optimizations. To satisfy the6034// verifier, we also need a GPRX0 instruction for the special encodings.6035def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$rs1, VTypeIOp11:$vtypei), []>,6036 PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,6037 Sched<[WriteVSETVLI, ReadVSETVLI]>;6038def PseudoVSETVLIX0 : Pseudo<(outs GPRNoX0:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>,6039 PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,6040 Sched<[WriteVSETVLI, ReadVSETVLI]>;6041def PseudoVSETVLIX0X0 : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>,6042 PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,6043 Sched<[WriteVSETVLI, ReadVSETVLI]>;6044def PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp10:$vtypei), []>,6045 PseudoInstExpansion<(VSETIVLI GPR:$rd, uimm5:$rs1, VTypeIOp10:$vtypei)>,6046 Sched<[WriteVSETIVLI]>;6047}6048 6049//===----------------------------------------------------------------------===//6050// 7. Vector Loads and Stores6051//===----------------------------------------------------------------------===//6052 6053//===----------------------------------------------------------------------===//6054// 7.4 Vector Unit-Stride Instructions6055//===----------------------------------------------------------------------===//6056 6057// Pseudos Unit-Stride Loads and Stores6058defm PseudoVL : VPseudoUSLoad;6059defm PseudoVS : VPseudoUSStore;6060 6061defm PseudoVLM : VPseudoLoadMask;6062defm PseudoVSM : VPseudoStoreMask;6063 6064//===----------------------------------------------------------------------===//6065// 7.5 Vector Strided Instructions6066//===----------------------------------------------------------------------===//6067 6068// Vector Strided Loads and Stores6069defm PseudoVLS : VPseudoSLoad;6070defm PseudoVSS : VPseudoSStore;6071 6072//===----------------------------------------------------------------------===//6073// 7.6 Vector Indexed Instructions6074//===----------------------------------------------------------------------===//6075 6076// Vector Indexed Loads and Stores6077defm PseudoVLUX : VPseudoILoad<Ordered=false>;6078defm PseudoVLOX : VPseudoILoad<Ordered=true>;6079defm PseudoVSOX : VPseudoIStore<Ordered=true>;6080defm PseudoVSUX : VPseudoIStore<Ordered=false>;6081 6082//===----------------------------------------------------------------------===//6083// 7.7. Unit-stride Fault-Only-First Loads6084//===----------------------------------------------------------------------===//6085 6086defm PseudoVL : VPseudoFFLoad;6087 6088//===----------------------------------------------------------------------===//6089// 7.8. Vector Load/Store Segment Instructions6090//===----------------------------------------------------------------------===//6091defm PseudoVLSEG : VPseudoUSSegLoad;6092defm PseudoVLSSEG : VPseudoSSegLoad;6093defm PseudoVLOXSEG : VPseudoISegLoad<Ordered=true>;6094defm PseudoVLUXSEG : VPseudoISegLoad<Ordered=false>;6095defm PseudoVSSEG : VPseudoUSSegStore;6096defm PseudoVSSSEG : VPseudoSSegStore;6097defm PseudoVSOXSEG : VPseudoISegStore<Ordered=true>;6098defm PseudoVSUXSEG : VPseudoISegStore<Ordered=false>;6099defm PseudoVLSEG : VPseudoUSSegLoadFF;6100 6101//===----------------------------------------------------------------------===//6102// 11. Vector Integer Arithmetic Instructions6103//===----------------------------------------------------------------------===//6104 6105//===----------------------------------------------------------------------===//6106// 11.1. Vector Single-Width Integer Add and Subtract6107//===----------------------------------------------------------------------===//6108defm PseudoVADD : VPseudoVALU_VV_VX_VI<Commutable=1>;6109defm PseudoVSUB : VPseudoVALU_VV_VX;6110defm PseudoVRSUB : VPseudoVALU_VX_VI;6111 6112foreach vti = AllIntegerVectors in {6113 // Match vrsub with 2 vector operands to vsub.vv by swapping operands. This6114 // Occurs when legalizing vrsub.vx intrinsics for i64 on RV32 since we need6115 // to use a more complex splat sequence. Add the pattern for all VTs for6116 // consistency.6117 let Predicates = GetVTypePredicates<vti>.Predicates in {6118 def : Pat<(vti.Vector (int_riscv_vrsub (vti.Vector vti.RegClass:$passthru),6119 (vti.Vector vti.RegClass:$rs2),6120 (vti.Vector vti.RegClass:$rs1),6121 VLOpFrag)),6122 (!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX)6123 vti.RegClass:$passthru,6124 vti.RegClass:$rs1,6125 vti.RegClass:$rs2,6126 GPR:$vl,6127 vti.Log2SEW, TU_MU)>;6128 def : Pat<(vti.Vector (int_riscv_vrsub_mask (vti.Vector vti.RegClass:$passthru),6129 (vti.Vector vti.RegClass:$rs2),6130 (vti.Vector vti.RegClass:$rs1),6131 (vti.Mask VMV0:$vm),6132 VLOpFrag,6133 (XLenVT timm:$policy))),6134 (!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX#"_MASK")6135 vti.RegClass:$passthru,6136 vti.RegClass:$rs1,6137 vti.RegClass:$rs2,6138 (vti.Mask VMV0:$vm),6139 GPR:$vl,6140 vti.Log2SEW,6141 (XLenVT timm:$policy))>;6142 6143 // Match VSUB with a small immediate to vadd.vi by negating the immediate.6144 def : Pat<(vti.Vector (int_riscv_vsub (vti.Vector vti.RegClass:$passthru),6145 (vti.Vector vti.RegClass:$rs1),6146 (vti.Scalar simm5_plus1:$rs2),6147 VLOpFrag)),6148 (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX)6149 vti.RegClass:$passthru,6150 vti.RegClass:$rs1,6151 (NegImm simm5_plus1:$rs2),6152 GPR:$vl,6153 vti.Log2SEW, TU_MU)>;6154 def : Pat<(vti.Vector (int_riscv_vsub_mask (vti.Vector vti.RegClass:$passthru),6155 (vti.Vector vti.RegClass:$rs1),6156 (vti.Scalar simm5_plus1:$rs2),6157 (vti.Mask VMV0:$vm),6158 VLOpFrag,6159 (XLenVT timm:$policy))),6160 (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX#"_MASK")6161 vti.RegClass:$passthru,6162 vti.RegClass:$rs1,6163 (NegImm simm5_plus1:$rs2),6164 (vti.Mask VMV0:$vm),6165 GPR:$vl,6166 vti.Log2SEW,6167 (XLenVT timm:$policy))>;6168 }6169}6170 6171// (add v, C) -> (sub v, -C) if -C cheaper to materialize6172defvar I64IntegerVectors = !filter(vti, AllIntegerVectors, !eq(vti.SEW, 64));6173foreach vti = I64IntegerVectors in {6174 let Predicates = [HasVInstructionsI64] in {6175 def : Pat<(vti.Vector (int_riscv_vadd (vti.Vector vti.RegClass:$passthru),6176 (vti.Vector vti.RegClass:$rs1),6177 (i64 negImm:$rs2),6178 VLOpFrag)),6179 (!cast<Instruction>("PseudoVSUB_VX_"#vti.LMul.MX)6180 vti.RegClass:$passthru,6181 vti.RegClass:$rs1,6182 negImm:$rs2,6183 GPR:$vl, vti.Log2SEW, TU_MU)>;6184 def : Pat<(vti.Vector (int_riscv_vadd_mask (vti.Vector vti.RegClass:$passthru),6185 (vti.Vector vti.RegClass:$rs1),6186 (i64 negImm:$rs2),6187 (vti.Mask VMV0:$vm),6188 VLOpFrag,6189 (i64 timm:$policy))),6190 (!cast<Instruction>("PseudoVSUB_VX_"#vti.LMul.MX#"_MASK")6191 vti.RegClass:$passthru,6192 vti.RegClass:$rs1,6193 negImm:$rs2,6194 (vti.Mask VMV0:$vm),6195 GPR:$vl,6196 vti.Log2SEW,6197 (i64 timm:$policy))>;6198 }6199}6200 6201//===----------------------------------------------------------------------===//6202// 11.2. Vector Widening Integer Add/Subtract6203//===----------------------------------------------------------------------===//6204defm PseudoVWADDU : VPseudoVWALU_VV_VX<Commutable=1>;6205defm PseudoVWSUBU : VPseudoVWALU_VV_VX;6206defm PseudoVWADD : VPseudoVWALU_VV_VX<Commutable=1>;6207defm PseudoVWSUB : VPseudoVWALU_VV_VX;6208defm PseudoVWADDU : VPseudoVWALU_WV_WX;6209defm PseudoVWSUBU : VPseudoVWALU_WV_WX;6210defm PseudoVWADD : VPseudoVWALU_WV_WX;6211defm PseudoVWSUB : VPseudoVWALU_WV_WX;6212 6213//===----------------------------------------------------------------------===//6214// 11.3. Vector Integer Extension6215//===----------------------------------------------------------------------===//6216defm PseudoVZEXT_VF2 : PseudoVEXT_VF2;6217defm PseudoVZEXT_VF4 : PseudoVEXT_VF4;6218defm PseudoVZEXT_VF8 : PseudoVEXT_VF8;6219defm PseudoVSEXT_VF2 : PseudoVEXT_VF2;6220defm PseudoVSEXT_VF4 : PseudoVEXT_VF4;6221defm PseudoVSEXT_VF8 : PseudoVEXT_VF8;6222 6223//===----------------------------------------------------------------------===//6224// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions6225//===----------------------------------------------------------------------===//6226defm PseudoVADC : VPseudoVCALU_VM_XM_IM;6227defm PseudoVMADC : VPseudoVCALUM_VM_XM_IM;6228defm PseudoVMADC : VPseudoVCALUM_V_X_I;6229 6230defm PseudoVSBC : VPseudoVCALU_VM_XM;6231defm PseudoVMSBC : VPseudoVCALUM_VM_XM;6232defm PseudoVMSBC : VPseudoVCALUM_V_X;6233 6234//===----------------------------------------------------------------------===//6235// 11.5. Vector Bitwise Logical Instructions6236//===----------------------------------------------------------------------===//6237defm PseudoVAND : VPseudoVALU_VV_VX_VI<Commutable=1>;6238defm PseudoVOR : VPseudoVALU_VV_VX_VI<Commutable=1>;6239defm PseudoVXOR : VPseudoVALU_VV_VX_VI<Commutable=1>;6240 6241//===----------------------------------------------------------------------===//6242// 11.6. Vector Single-Width Bit Shift Instructions6243//===----------------------------------------------------------------------===//6244defm PseudoVSLL : VPseudoVSHT_VV_VX_VI;6245defm PseudoVSRL : VPseudoVSHT_VV_VX_VI;6246defm PseudoVSRA : VPseudoVSHT_VV_VX_VI;6247 6248//===----------------------------------------------------------------------===//6249// 11.7. Vector Narrowing Integer Right Shift Instructions6250//===----------------------------------------------------------------------===//6251defm PseudoVNSRL : VPseudoVNSHT_WV_WX_WI;6252defm PseudoVNSRA : VPseudoVNSHT_WV_WX_WI;6253 6254//===----------------------------------------------------------------------===//6255// 11.8. Vector Integer Comparison Instructions6256//===----------------------------------------------------------------------===//6257defm PseudoVMSEQ : VPseudoVCMPM_VV_VX_VI<Commutable=1>;6258defm PseudoVMSNE : VPseudoVCMPM_VV_VX_VI<Commutable=1>;6259defm PseudoVMSLTU : VPseudoVCMPM_VV_VX;6260defm PseudoVMSLT : VPseudoVCMPM_VV_VX;6261defm PseudoVMSLEU : VPseudoVCMPM_VV_VX_VI;6262defm PseudoVMSLE : VPseudoVCMPM_VV_VX_VI;6263defm PseudoVMSGTU : VPseudoVCMPM_VX_VI;6264defm PseudoVMSGT : VPseudoVCMPM_VX_VI;6265 6266//===----------------------------------------------------------------------===//6267// 11.9. Vector Integer Min/Max Instructions6268//===----------------------------------------------------------------------===//6269defm PseudoVMINU : VPseudoVMINMAX_VV_VX;6270defm PseudoVMIN : VPseudoVMINMAX_VV_VX;6271defm PseudoVMAXU : VPseudoVMINMAX_VV_VX;6272defm PseudoVMAX : VPseudoVMINMAX_VV_VX;6273 6274//===----------------------------------------------------------------------===//6275// 11.10. Vector Single-Width Integer Multiply Instructions6276//===----------------------------------------------------------------------===//6277defm PseudoVMUL : VPseudoVMUL_VV_VX<Commutable=1>;6278defm PseudoVMULH : VPseudoVMUL_VV_VX<Commutable=1>;6279defm PseudoVMULHU : VPseudoVMUL_VV_VX<Commutable=1>;6280defm PseudoVMULHSU : VPseudoVMUL_VV_VX;6281 6282//===----------------------------------------------------------------------===//6283// 11.11. Vector Integer Divide Instructions6284//===----------------------------------------------------------------------===//6285defm PseudoVDIVU : VPseudoVDIV_VV_VX;6286defm PseudoVDIV : VPseudoVDIV_VV_VX;6287defm PseudoVREMU : VPseudoVDIV_VV_VX;6288defm PseudoVREM : VPseudoVDIV_VV_VX;6289 6290//===----------------------------------------------------------------------===//6291// 11.12. Vector Widening Integer Multiply Instructions6292//===----------------------------------------------------------------------===//6293defm PseudoVWMUL : VPseudoVWMUL_VV_VX<Commutable=1>;6294defm PseudoVWMULU : VPseudoVWMUL_VV_VX<Commutable=1>;6295defm PseudoVWMULSU : VPseudoVWMUL_VV_VX;6296 6297//===----------------------------------------------------------------------===//6298// 11.13. Vector Single-Width Integer Multiply-Add Instructions6299//===----------------------------------------------------------------------===//6300defm PseudoVMACC : VPseudoVMAC_VV_VX_AAXA;6301defm PseudoVNMSAC : VPseudoVMAC_VV_VX_AAXA;6302defm PseudoVMADD : VPseudoVMAC_VV_VX_AAXA;6303defm PseudoVNMSUB : VPseudoVMAC_VV_VX_AAXA;6304 6305//===----------------------------------------------------------------------===//6306// 11.14. Vector Widening Integer Multiply-Add Instructions6307//===----------------------------------------------------------------------===//6308defm PseudoVWMACCU : VPseudoVWMAC_VV_VX<Commutable=1>;6309defm PseudoVWMACC : VPseudoVWMAC_VV_VX<Commutable=1>;6310defm PseudoVWMACCSU : VPseudoVWMAC_VV_VX;6311defm PseudoVWMACCUS : VPseudoVWMAC_VX;6312 6313//===----------------------------------------------------------------------===//6314// 11.15. Vector Integer Merge Instructions6315//===----------------------------------------------------------------------===//6316defm PseudoVMERGE : VPseudoVMRG_VM_XM_IM;6317 6318//===----------------------------------------------------------------------===//6319// 11.16. Vector Integer Move Instructions6320//===----------------------------------------------------------------------===//6321defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I;6322 6323//===----------------------------------------------------------------------===//6324// 12. Vector Fixed-Point Arithmetic Instructions6325//===----------------------------------------------------------------------===//6326 6327//===----------------------------------------------------------------------===//6328// 12.1. Vector Single-Width Saturating Add and Subtract6329//===----------------------------------------------------------------------===//6330let Defs = [VXSAT] in {6331 defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI<Commutable=1>;6332 defm PseudoVSADD : VPseudoVSALU_VV_VX_VI<Commutable=1>;6333 defm PseudoVSSUBU : VPseudoVSALU_VV_VX;6334 defm PseudoVSSUB : VPseudoVSALU_VV_VX;6335}6336 6337//===----------------------------------------------------------------------===//6338// 12.2. Vector Single-Width Averaging Add and Subtract6339//===----------------------------------------------------------------------===//6340defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM<Commutable=1>;6341defm PseudoVAADD : VPseudoVAALU_VV_VX_RM<Commutable=1>;6342defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM;6343defm PseudoVASUB : VPseudoVAALU_VV_VX_RM;6344 6345//===----------------------------------------------------------------------===//6346// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation6347//===----------------------------------------------------------------------===//6348let Defs = [VXSAT] in {6349 defm PseudoVSMUL : VPseudoVSMUL_VV_VX_RM;6350}6351 6352//===----------------------------------------------------------------------===//6353// 12.4. Vector Single-Width Scaling Shift Instructions6354//===----------------------------------------------------------------------===//6355defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI_RM;6356defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM;6357 6358//===----------------------------------------------------------------------===//6359// 12.5. Vector Narrowing Fixed-Point Clip Instructions6360//===----------------------------------------------------------------------===//6361let Defs = [VXSAT] in {6362 defm PseudoVNCLIP : VPseudoVNCLP_WV_WX_WI_RM;6363 defm PseudoVNCLIPU : VPseudoVNCLP_WV_WX_WI_RM;6364}6365 6366} // Predicates = [HasVInstructions]6367 6368//===----------------------------------------------------------------------===//6369// 13. Vector Floating-Point Instructions6370//===----------------------------------------------------------------------===//6371 6372let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in {6373//===----------------------------------------------------------------------===//6374// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions6375//===----------------------------------------------------------------------===//6376let mayRaiseFPException = true in {6377defm PseudoVFADD : VPseudoVALU_VV_VF_RM;6378defm PseudoVFSUB : VPseudoVALU_VV_VF_RM;6379defm PseudoVFRSUB : VPseudoVALU_VF_RM;6380}6381 6382//===----------------------------------------------------------------------===//6383// 13.3. Vector Widening Floating-Point Add/Subtract Instructions6384//===----------------------------------------------------------------------===//6385let mayRaiseFPException = true in {6386defm PseudoVFWADD : VPseudoVFWALU_VV_VF_RM;6387defm PseudoVFWSUB : VPseudoVFWALU_VV_VF_RM;6388defm PseudoVFWADD : VPseudoVFWALU_WV_WF_RM;6389defm PseudoVFWSUB : VPseudoVFWALU_WV_WF_RM;6390}6391 6392//===----------------------------------------------------------------------===//6393// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions6394//===----------------------------------------------------------------------===//6395let mayRaiseFPException = true in {6396defm PseudoVFMUL : VPseudoVFMUL_VV_VF_RM;6397defm PseudoVFDIV : VPseudoVFDIV_VV_VF_RM;6398defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;6399}6400 6401//===----------------------------------------------------------------------===//6402// 13.5. Vector Widening Floating-Point Multiply6403//===----------------------------------------------------------------------===//6404let mayRaiseFPException = true in {6405defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM;6406}6407 6408//===----------------------------------------------------------------------===//6409// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions6410//===----------------------------------------------------------------------===//6411let mayRaiseFPException = true in {6412defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA_RM;6413defm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA_RM;6414defm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA_RM;6415defm PseudoVFNMSAC : VPseudoVMAC_VV_VF_AAXA_RM;6416defm PseudoVFMADD : VPseudoVMAC_VV_VF_AAXA_RM;6417defm PseudoVFNMADD : VPseudoVMAC_VV_VF_AAXA_RM;6418defm PseudoVFMSUB : VPseudoVMAC_VV_VF_AAXA_RM;6419defm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA_RM;6420}6421 6422//===----------------------------------------------------------------------===//6423// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions6424//===----------------------------------------------------------------------===//6425let mayRaiseFPException = true in {6426defm PseudoVFWMACC : VPseudoVWMAC_VV_VF_RM;6427defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF_RM;6428defm PseudoVFWMSAC : VPseudoVWMAC_VV_VF_RM;6429defm PseudoVFWNMSAC : VPseudoVWMAC_VV_VF_RM;6430}6431 6432//===----------------------------------------------------------------------===//6433// 13.8. Vector Floating-Point Square-Root Instruction6434//===----------------------------------------------------------------------===//6435let mayRaiseFPException = true in6436defm PseudoVFSQRT : VPseudoVSQR_V_RM;6437 6438//===----------------------------------------------------------------------===//6439// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction6440//===----------------------------------------------------------------------===//6441let mayRaiseFPException = true in6442defm PseudoVFRSQRT7 : VPseudoVRCP_V;6443 6444//===----------------------------------------------------------------------===//6445// 13.10. Vector Floating-Point Reciprocal Estimate Instruction6446//===----------------------------------------------------------------------===//6447let mayRaiseFPException = true in6448defm PseudoVFREC7 : VPseudoVRCP_V_RM;6449 6450//===----------------------------------------------------------------------===//6451// 13.11. Vector Floating-Point Min/Max Instructions6452//===----------------------------------------------------------------------===//6453let mayRaiseFPException = true in {6454defm PseudoVFMIN : VPseudoVMAX_VV_VF;6455defm PseudoVFMAX : VPseudoVMAX_VV_VF;6456}6457 6458//===----------------------------------------------------------------------===//6459// 13.12. Vector Floating-Point Sign-Injection Instructions6460//===----------------------------------------------------------------------===//6461defm PseudoVFSGNJ : VPseudoVSGNJ_VV_VF;6462defm PseudoVFSGNJN : VPseudoVSGNJ_VV_VF;6463defm PseudoVFSGNJX : VPseudoVSGNJ_VV_VF;6464 6465//===----------------------------------------------------------------------===//6466// 13.13. Vector Floating-Point Compare Instructions6467//===----------------------------------------------------------------------===//6468let mayRaiseFPException = true in {6469defm PseudoVMFEQ : VPseudoVCMPM_VV_VF;6470defm PseudoVMFNE : VPseudoVCMPM_VV_VF;6471defm PseudoVMFLT : VPseudoVCMPM_VV_VF;6472defm PseudoVMFLE : VPseudoVCMPM_VV_VF;6473defm PseudoVMFGT : VPseudoVCMPM_VF;6474defm PseudoVMFGE : VPseudoVCMPM_VF;6475}6476 6477//===----------------------------------------------------------------------===//6478// 13.14. Vector Floating-Point Classify Instruction6479//===----------------------------------------------------------------------===//6480defm PseudoVFCLASS : VPseudoVCLS_V;6481 6482//===----------------------------------------------------------------------===//6483// 13.15. Vector Floating-Point Merge Instruction6484//===----------------------------------------------------------------------===//6485defm PseudoVFMERGE : VPseudoVMRG_FM;6486 6487//===----------------------------------------------------------------------===//6488// 13.16. Vector Floating-Point Move Instruction6489//===----------------------------------------------------------------------===//6490let isReMaterializable = 1 in6491defm PseudoVFMV_V : VPseudoVMV_F;6492 6493//===----------------------------------------------------------------------===//6494// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions6495//===----------------------------------------------------------------------===//6496let mayRaiseFPException = true in {6497defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM;6498defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM;6499 6500defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;6501defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;6502 6503defm PseudoVFROUND_NOEXCEPT : VPseudoVFROUND_NOEXCEPT_V;6504defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM;6505defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM;6506} // mayRaiseFPException = true6507 6508//===----------------------------------------------------------------------===//6509// 13.18. Widening Floating-Point/Integer Type-Convert Instructions6510//===----------------------------------------------------------------------===//6511let mayRaiseFPException = true in {6512defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM;6513defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM;6514 6515defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;6516defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V;6517 6518defm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V;6519defm PseudoVFWCVT_F_X : VPseudoVWCVTF_V;6520 6521defm PseudoVFWCVT_F_F : VPseudoVWCVTD_V;6522} // mayRaiseFPException = true6523 6524//===----------------------------------------------------------------------===//6525// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions6526//===----------------------------------------------------------------------===//6527let mayRaiseFPException = true in {6528defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM;6529defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM;6530 6531defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;6532defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;6533 6534defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM;6535defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;6536 6537defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;6538 6539defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;6540} // mayRaiseFPException = true6541} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT6542 6543//===----------------------------------------------------------------------===//6544// 14. Vector Reduction Operations6545//===----------------------------------------------------------------------===//6546 6547let Predicates = [HasVInstructions] in {6548//===----------------------------------------------------------------------===//6549// 14.1. Vector Single-Width Integer Reduction Instructions6550//===----------------------------------------------------------------------===//6551defm PseudoVREDSUM : VPseudoVRED_VS;6552defm PseudoVREDAND : VPseudoVRED_VS;6553defm PseudoVREDOR : VPseudoVRED_VS;6554defm PseudoVREDXOR : VPseudoVRED_VS;6555defm PseudoVREDMINU : VPseudoVREDMINMAX_VS;6556defm PseudoVREDMIN : VPseudoVREDMINMAX_VS;6557defm PseudoVREDMAXU : VPseudoVREDMINMAX_VS;6558defm PseudoVREDMAX : VPseudoVREDMINMAX_VS;6559 6560//===----------------------------------------------------------------------===//6561// 14.2. Vector Widening Integer Reduction Instructions6562//===----------------------------------------------------------------------===//6563let IsRVVWideningReduction = 1 in {6564defm PseudoVWREDSUMU : VPseudoVWRED_VS;6565defm PseudoVWREDSUM : VPseudoVWRED_VS;6566}6567} // Predicates = [HasVInstructions]6568 6569let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in {6570//===----------------------------------------------------------------------===//6571// 14.3. Vector Single-Width Floating-Point Reduction Instructions6572//===----------------------------------------------------------------------===//6573let mayRaiseFPException = true in {6574defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM;6575defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM;6576defm PseudoVFREDMIN : VPseudoVFREDMINMAX_VS;6577defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS;6578}6579 6580//===----------------------------------------------------------------------===//6581// 14.4. Vector Widening Floating-Point Reduction Instructions6582//===----------------------------------------------------------------------===//6583let IsRVVWideningReduction = 1, mayRaiseFPException = true in {6584defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM;6585defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;6586}6587 6588} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT6589 6590//===----------------------------------------------------------------------===//6591// 15. Vector Mask Instructions6592//===----------------------------------------------------------------------===//6593 6594let Predicates = [HasVInstructions] in {6595//===----------------------------------------------------------------------===//6596// 15.1 Vector Mask-Register Logical Instructions6597//===----------------------------------------------------------------------===//6598 6599defm PseudoVMAND: VPseudoVALU_MM<Commutable=1>;6600defm PseudoVMNAND: VPseudoVALU_MM<Commutable=1>;6601defm PseudoVMANDN: VPseudoVALU_MM;6602defm PseudoVMXOR: VPseudoVALU_MM<Commutable=1>;6603defm PseudoVMOR: VPseudoVALU_MM<Commutable=1>;6604defm PseudoVMNOR: VPseudoVALU_MM<Commutable=1>;6605defm PseudoVMORN: VPseudoVALU_MM;6606defm PseudoVMXNOR: VPseudoVALU_MM<Commutable=1>;6607 6608// Pseudo instructions6609defm PseudoVMCLR : VPseudoNullaryPseudoM<"VMXOR">;6610defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">;6611 6612//===----------------------------------------------------------------------===//6613// 15.2. Vector mask population count vcpop6614//===----------------------------------------------------------------------===//6615let IsSignExtendingOpW = 1 in6616defm PseudoVCPOP: VPseudoVPOP_M;6617 6618//===----------------------------------------------------------------------===//6619// 15.3. vfirst find-first-set mask bit6620//===----------------------------------------------------------------------===//6621 6622let IsSignExtendingOpW = 1 in6623defm PseudoVFIRST: VPseudoV1ST_M;6624 6625//===----------------------------------------------------------------------===//6626// 15.4. vmsbf.m set-before-first mask bit6627//===----------------------------------------------------------------------===//6628defm PseudoVMSBF: VPseudoVSFS_M;6629 6630//===----------------------------------------------------------------------===//6631// 15.5. vmsif.m set-including-first mask bit6632//===----------------------------------------------------------------------===//6633defm PseudoVMSIF: VPseudoVSFS_M;6634 6635//===----------------------------------------------------------------------===//6636// 15.6. vmsof.m set-only-first mask bit6637//===----------------------------------------------------------------------===//6638defm PseudoVMSOF: VPseudoVSFS_M;6639 6640//===----------------------------------------------------------------------===//6641// 15.8. Vector Iota Instruction6642//===----------------------------------------------------------------------===//6643defm PseudoVIOTA_M: VPseudoVIOTA_M;6644 6645//===----------------------------------------------------------------------===//6646// 15.9. Vector Element Index Instruction6647//===----------------------------------------------------------------------===//6648let isReMaterializable = 1 in6649defm PseudoVID : VPseudoVID_V;6650} // Predicates = [HasVInstructions]6651 6652//===----------------------------------------------------------------------===//6653// 16. Vector Permutation Instructions6654//===----------------------------------------------------------------------===//6655 6656//===----------------------------------------------------------------------===//6657// 16.1. Integer Scalar Move Instructions6658//===----------------------------------------------------------------------===//6659 6660let Predicates = [HasVInstructions] in {6661let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {6662 let HasSEWOp = 1, BaseInstr = VMV_X_S in6663 def PseudoVMV_X_S :6664 RISCVVPseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew)>,6665 Sched<[WriteVMovXS, ReadVMovXS]>;6666 let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1,6667 Constraints = "$rd = $passthru" in6668 def PseudoVMV_S_X :6669 RISCVVPseudo<(outs VR:$rd),6670 (ins VR:$passthru, GPR:$rs1, AVL:$vl, sew:$sew)>,6671 Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>;6672}6673} // Predicates = [HasVInstructions]6674 6675//===----------------------------------------------------------------------===//6676// 16.2. Floating-Point Scalar Move Instructions6677//===----------------------------------------------------------------------===//6678 6679let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in {6680let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {6681 foreach f = FPList in {6682 let HasSEWOp = 1, BaseInstr = VFMV_F_S in6683 def "PseudoVFMV_" # f.FX # "_S" :6684 RISCVVPseudo<(outs f.fprclass:$rd), (ins VR:$rs2, sew:$sew)>,6685 Sched<[WriteVMovFS, ReadVMovFS]>;6686 let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,6687 Constraints = "$rd = $passthru" in6688 def "PseudoVFMV_S_" # f.FX :6689 RISCVVPseudo<(outs VR:$rd),6690 (ins VR:$passthru, f.fprclass:$rs1, AVL:$vl, sew:$sew)>,6691 Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;6692 }6693}6694} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT6695 6696//===----------------------------------------------------------------------===//6697// 16.3. Vector Slide Instructions6698//===----------------------------------------------------------------------===//6699let Predicates = [HasVInstructions] in {6700 defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI</*slidesUp=*/true, "@earlyclobber $rd">;6701 defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI</*slidesUp=*/false>;6702 defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">;6703 defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX;6704} // Predicates = [HasVInstructions]6705 6706let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in {6707 defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF<"@earlyclobber $rd">;6708 defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF;6709} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT6710 6711//===----------------------------------------------------------------------===//6712// 16.4. Vector Register Gather Instructions6713//===----------------------------------------------------------------------===//6714let Predicates = [HasVInstructions] in {6715defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI;6716defm PseudoVRGATHEREI16 : VPseudoVGTR_EI16_VV;6717 6718//===----------------------------------------------------------------------===//6719// 16.5. Vector Compress Instruction6720//===----------------------------------------------------------------------===//6721defm PseudoVCOMPRESS : VPseudoVCPR_V;6722} // Predicates = [HasVInstructions]6723 6724//===----------------------------------------------------------------------===//6725// Patterns.6726//===----------------------------------------------------------------------===//6727 6728//===----------------------------------------------------------------------===//6729// 11. Vector Integer Arithmetic Instructions6730//===----------------------------------------------------------------------===//6731 6732//===----------------------------------------------------------------------===//6733// 11.1. Vector Single-Width Integer Add and Subtract6734//===----------------------------------------------------------------------===//6735defm : VPatBinaryV_VV_VX_VI<"int_riscv_vadd", "PseudoVADD", AllIntegerVectors>;6736defm : VPatBinaryV_VV_VX<"int_riscv_vsub", "PseudoVSUB", AllIntegerVectors>;6737defm : VPatBinaryV_VX_VI<"int_riscv_vrsub", "PseudoVRSUB", AllIntegerVectors>;6738 6739//===----------------------------------------------------------------------===//6740// 11.2. Vector Widening Integer Add/Subtract6741//===----------------------------------------------------------------------===//6742defm : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU", AllWidenableIntVectors>;6743defm : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU", AllWidenableIntVectors>;6744defm : VPatBinaryW_VV_VX<"int_riscv_vwadd", "PseudoVWADD", AllWidenableIntVectors>;6745defm : VPatBinaryW_VV_VX<"int_riscv_vwsub", "PseudoVWSUB", AllWidenableIntVectors>;6746defm : VPatBinaryW_WV_WX<"int_riscv_vwaddu_w", "PseudoVWADDU", AllWidenableIntVectors>;6747defm : VPatBinaryW_WV_WX<"int_riscv_vwsubu_w", "PseudoVWSUBU", AllWidenableIntVectors>;6748defm : VPatBinaryW_WV_WX<"int_riscv_vwadd_w", "PseudoVWADD", AllWidenableIntVectors>;6749defm : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB", AllWidenableIntVectors>;6750 6751//===----------------------------------------------------------------------===//6752// 11.3. Vector Integer Extension6753//===----------------------------------------------------------------------===//6754defm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF2",6755 AllFractionableVF2IntVectors>;6756defm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF4",6757 AllFractionableVF4IntVectors>;6758defm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF8",6759 AllFractionableVF8IntVectors>;6760defm : VPatUnaryV_VF<"int_riscv_vsext", "PseudoVSEXT", "VF2",6761 AllFractionableVF2IntVectors>;6762defm : VPatUnaryV_VF<"int_riscv_vsext", "PseudoVSEXT", "VF4",6763 AllFractionableVF4IntVectors>;6764defm : VPatUnaryV_VF<"int_riscv_vsext", "PseudoVSEXT", "VF8",6765 AllFractionableVF8IntVectors>;6766 6767//===----------------------------------------------------------------------===//6768// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions6769//===----------------------------------------------------------------------===//6770defm : VPatBinaryV_VM_XM_IM<"int_riscv_vadc", "PseudoVADC">;6771defm : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">;6772defm : VPatBinaryM_V_X_I<"int_riscv_vmadc", "PseudoVMADC">;6773 6774defm : VPatBinaryV_VM_XM<"int_riscv_vsbc", "PseudoVSBC">;6775defm : VPatBinaryM_VM_XM<"int_riscv_vmsbc_borrow_in", "PseudoVMSBC">;6776defm : VPatBinaryM_V_X<"int_riscv_vmsbc", "PseudoVMSBC">;6777 6778//===----------------------------------------------------------------------===//6779// 11.5. Vector Bitwise Logical Instructions6780//===----------------------------------------------------------------------===//6781defm : VPatBinaryV_VV_VX_VI<"int_riscv_vand", "PseudoVAND", AllIntegerVectors>;6782defm : VPatBinaryV_VV_VX_VI<"int_riscv_vor", "PseudoVOR", AllIntegerVectors>;6783defm : VPatBinaryV_VV_VX_VI<"int_riscv_vxor", "PseudoVXOR", AllIntegerVectors>;6784 6785//===----------------------------------------------------------------------===//6786// 11.6. Vector Single-Width Bit Shift Instructions6787//===----------------------------------------------------------------------===//6788defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors,6789 uimm5>;6790defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors,6791 uimm5>;6792defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,6793 uimm5>;6794 6795foreach vti = AllIntegerVectors in {6796 // Emit shift by 1 as an add since it might be faster.6797 let Predicates = GetVTypePredicates<vti>.Predicates in {6798 def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector vti.RegClass:$passthru),6799 (vti.Vector vti.RegClass:$rs1),6800 (XLenVT 1), VLOpFrag)),6801 (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX)6802 vti.RegClass:$passthru, vti.RegClass:$rs1,6803 vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;6804 def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$passthru),6805 (vti.Vector vti.RegClass:$rs1),6806 (XLenVT 1),6807 (vti.Mask VMV0:$vm),6808 VLOpFrag,6809 (XLenVT timm:$policy))),6810 (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX#"_MASK")6811 vti.RegClass:$passthru,6812 vti.RegClass:$rs1,6813 vti.RegClass:$rs1,6814 (vti.Mask VMV0:$vm),6815 GPR:$vl,6816 vti.Log2SEW,6817 (XLenVT timm:$policy))>;6818 }6819}6820 6821//===----------------------------------------------------------------------===//6822// 11.7. Vector Narrowing Integer Right Shift Instructions6823//===----------------------------------------------------------------------===//6824defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>;6825defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>;6826 6827//===----------------------------------------------------------------------===//6828// 11.8. Vector Integer Comparison Instructions6829//===----------------------------------------------------------------------===//6830defm : VPatBinaryM_VV_VX_VI<"int_riscv_vmseq", "PseudoVMSEQ", AllIntegerVectors>;6831defm : VPatBinaryM_VV_VX_VI<"int_riscv_vmsne", "PseudoVMSNE", AllIntegerVectors>;6832defm : VPatBinaryM_VV_VX<"int_riscv_vmsltu", "PseudoVMSLTU", AllIntegerVectors>;6833defm : VPatBinaryM_VV_VX<"int_riscv_vmslt", "PseudoVMSLT", AllIntegerVectors>;6834defm : VPatBinaryM_VV_VX_VI<"int_riscv_vmsleu", "PseudoVMSLEU", AllIntegerVectors>;6835defm : VPatBinaryM_VV_VX_VI<"int_riscv_vmsle", "PseudoVMSLE", AllIntegerVectors>;6836 6837defm : VPatBinaryM_VX_VI<"int_riscv_vmsgtu", "PseudoVMSGTU", AllIntegerVectors>;6838defm : VPatBinaryM_VX_VI<"int_riscv_vmsgt", "PseudoVMSGT", AllIntegerVectors>;6839 6840// Match vmsgt with 2 vector operands to vmslt with the operands swapped.6841defm : VPatBinarySwappedM_VV<"int_riscv_vmsgtu", "PseudoVMSLTU", AllIntegerVectors>;6842defm : VPatBinarySwappedM_VV<"int_riscv_vmsgt", "PseudoVMSLT", AllIntegerVectors>;6843 6844defm : VPatBinarySwappedM_VV<"int_riscv_vmsgeu", "PseudoVMSLEU", AllIntegerVectors>;6845defm : VPatBinarySwappedM_VV<"int_riscv_vmsge", "PseudoVMSLE", AllIntegerVectors>;6846 6847// Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16 and6848// non-zero. Zero can be .vx with x0. This avoids the user needing to know that6849// there is no vmslt(u).vi instruction. Similar for vmsge(u).vx intrinsics6850// using vmslt(u).vi.6851defm : VPatCompare_VI<"int_riscv_vmslt", "PseudoVMSLE", simm5_plus1_nonzero>;6852defm : VPatCompare_VI<"int_riscv_vmsltu", "PseudoVMSLEU", simm5_plus1_nonzero>;6853 6854// We need to handle 0 for vmsge.vi using vmslt.vi because there is no vmsge.vx.6855defm : VPatCompare_VI<"int_riscv_vmsge", "PseudoVMSGT", simm5_plus1>;6856defm : VPatCompare_VI<"int_riscv_vmsgeu", "PseudoVMSGTU", simm5_plus1_nonzero>;6857 6858//===----------------------------------------------------------------------===//6859// 11.9. Vector Integer Min/Max Instructions6860//===----------------------------------------------------------------------===//6861defm : VPatBinaryV_VV_VX<"int_riscv_vminu", "PseudoVMINU", AllIntegerVectors>;6862defm : VPatBinaryV_VV_VX<"int_riscv_vmin", "PseudoVMIN", AllIntegerVectors>;6863defm : VPatBinaryV_VV_VX<"int_riscv_vmaxu", "PseudoVMAXU", AllIntegerVectors>;6864defm : VPatBinaryV_VV_VX<"int_riscv_vmax", "PseudoVMAX", AllIntegerVectors>;6865 6866//===----------------------------------------------------------------------===//6867// 11.10. Vector Single-Width Integer Multiply Instructions6868//===----------------------------------------------------------------------===//6869defm : VPatBinaryV_VV_VX<"int_riscv_vmul", "PseudoVMUL", AllIntegerVectors>;6870 6871defvar IntegerVectorsExceptI64 = !filter(vti, AllIntegerVectors,6872 !ne(vti.SEW, 64));6873defm : VPatBinaryV_VV_VX<"int_riscv_vmulh", "PseudoVMULH",6874 IntegerVectorsExceptI64>;6875defm : VPatBinaryV_VV_VX<"int_riscv_vmulhu", "PseudoVMULHU",6876 IntegerVectorsExceptI64>;6877defm : VPatBinaryV_VV_VX<"int_riscv_vmulhsu", "PseudoVMULHSU",6878 IntegerVectorsExceptI64>;6879 6880// vmulh, vmulhu, vmulhsu are not included for EEW=64 in Zve64*.6881defvar I64IntegerVectors = !filter(vti, AllIntegerVectors, !eq(vti.SEW, 64));6882let Predicates = [HasVInstructionsFullMultiply] in {6883 defm : VPatBinaryV_VV_VX<"int_riscv_vmulh", "PseudoVMULH",6884 I64IntegerVectors>;6885 defm : VPatBinaryV_VV_VX<"int_riscv_vmulhu", "PseudoVMULHU",6886 I64IntegerVectors>;6887 defm : VPatBinaryV_VV_VX<"int_riscv_vmulhsu", "PseudoVMULHSU",6888 I64IntegerVectors>;6889}6890 6891//===----------------------------------------------------------------------===//6892// 11.11. Vector Integer Divide Instructions6893//===----------------------------------------------------------------------===//6894defm : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors, isSEWAware=1>;6895defm : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors, isSEWAware=1>;6896defm : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors, isSEWAware=1>;6897defm : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors, isSEWAware=1>;6898 6899//===----------------------------------------------------------------------===//6900// 11.12. Vector Widening Integer Multiply Instructions6901//===----------------------------------------------------------------------===//6902defm : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL", AllWidenableIntVectors>;6903defm : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU", AllWidenableIntVectors>;6904defm : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU", AllWidenableIntVectors>;6905 6906//===----------------------------------------------------------------------===//6907// 11.13. Vector Single-Width Integer Multiply-Add Instructions6908//===----------------------------------------------------------------------===//6909defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vmadd", "PseudoVMADD", AllIntegerVectors>;6910defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsub", "PseudoVNMSUB", AllIntegerVectors>;6911defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vmacc", "PseudoVMACC", AllIntegerVectors>;6912defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsac", "PseudoVNMSAC", AllIntegerVectors>;6913 6914//===----------------------------------------------------------------------===//6915// 11.14. Vector Widening Integer Multiply-Add Instructions6916//===----------------------------------------------------------------------===//6917defm : VPatTernaryW_VV_VX<"int_riscv_vwmaccu", "PseudoVWMACCU", AllWidenableIntVectors>;6918defm : VPatTernaryW_VV_VX<"int_riscv_vwmacc", "PseudoVWMACC", AllWidenableIntVectors>;6919defm : VPatTernaryW_VV_VX<"int_riscv_vwmaccsu", "PseudoVWMACCSU", AllWidenableIntVectors>;6920defm : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>;6921 6922//===----------------------------------------------------------------------===//6923// 11.15. Vector Integer Merge Instructions6924//===----------------------------------------------------------------------===//6925defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;6926 6927//===----------------------------------------------------------------------===//6928// 11.16. Vector Integer Move Instructions6929//===----------------------------------------------------------------------===//6930foreach vti = AllVectors in {6931 let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in {6932 def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$passthru),6933 (vti.Vector vti.RegClass:$rs1),6934 VLOpFrag)),6935 (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)6936 $passthru, $rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;6937 6938 // vmv.v.x/vmv.v.i are handled in RISCInstrVInstrInfoVVLPatterns.td6939 }6940}6941 6942//===----------------------------------------------------------------------===//6943// 12. Vector Fixed-Point Arithmetic Instructions6944//===----------------------------------------------------------------------===//6945 6946//===----------------------------------------------------------------------===//6947// 12.1. Vector Single-Width Saturating Add and Subtract6948//===----------------------------------------------------------------------===//6949defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsaddu", "PseudoVSADDU", AllIntegerVectors>;6950defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsadd", "PseudoVSADD", AllIntegerVectors>;6951defm : VPatBinaryV_VV_VX<"int_riscv_vssubu", "PseudoVSSUBU", AllIntegerVectors>;6952defm : VPatBinaryV_VV_VX<"int_riscv_vssub", "PseudoVSSUB", AllIntegerVectors>;6953 6954//===----------------------------------------------------------------------===//6955// 12.2. Vector Single-Width Averaging Add and Subtract6956//===----------------------------------------------------------------------===//6957defm : VPatBinaryV_VV_VX_RM<"int_riscv_vaaddu", "PseudoVAADDU",6958 AllIntegerVectors>;6959defm : VPatBinaryV_VV_VX_RM<"int_riscv_vasubu", "PseudoVASUBU",6960 AllIntegerVectors>;6961defm : VPatBinaryV_VV_VX_RM<"int_riscv_vasub", "PseudoVASUB",6962 AllIntegerVectors>;6963defm : VPatBinaryV_VV_VX_RM<"int_riscv_vaadd", "PseudoVAADD",6964 AllIntegerVectors>;6965 6966//===----------------------------------------------------------------------===//6967// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation6968//===----------------------------------------------------------------------===//6969defm : VPatBinaryV_VV_VX_RM<"int_riscv_vsmul", "PseudoVSMUL",6970 IntegerVectorsExceptI64>;6971// vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*.6972let Predicates = [HasVInstructionsFullMultiply] in6973defm : VPatBinaryV_VV_VX_RM<"int_riscv_vsmul", "PseudoVSMUL",6974 I64IntegerVectors>;6975 6976//===----------------------------------------------------------------------===//6977// 12.4. Vector Single-Width Scaling Shift Instructions6978//===----------------------------------------------------------------------===//6979defm : VPatBinaryV_VV_VX_VI_RM<"int_riscv_vssrl", "PseudoVSSRL",6980 AllIntegerVectors, uimm5>;6981defm : VPatBinaryV_VV_VX_VI_RM<"int_riscv_vssra", "PseudoVSSRA",6982 AllIntegerVectors, uimm5>;6983 6984//===----------------------------------------------------------------------===//6985// 12.5. Vector Narrowing Fixed-Point Clip Instructions6986//===----------------------------------------------------------------------===//6987defm : VPatBinaryV_WV_WX_WI_RM<"int_riscv_vnclipu", "PseudoVNCLIPU",6988 AllWidenableIntVectors>;6989defm : VPatBinaryV_WV_WX_WI_RM<"int_riscv_vnclip", "PseudoVNCLIP",6990 AllWidenableIntVectors>;6991 6992//===----------------------------------------------------------------------===//6993// 13. Vector Floating-Point Instructions6994//===----------------------------------------------------------------------===//6995 6996//===----------------------------------------------------------------------===//6997// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions6998//===----------------------------------------------------------------------===//6999defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors,7000 isSEWAware = 1>;7001defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors,7002 isSEWAware = 1>;7003defm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors,7004 isSEWAware = 1>;7005 7006//===----------------------------------------------------------------------===//7007// 13.3. Vector Widening Floating-Point Add/Subtract Instructions7008//===----------------------------------------------------------------------===//7009defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwadd", "PseudoVFWADD",7010 AllWidenableFloatVectors, isSEWAware=1>;7011defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwsub", "PseudoVFWSUB",7012 AllWidenableFloatVectors, isSEWAware=1>;7013defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwadd_w", "PseudoVFWADD",7014 AllWidenableFloatVectors, isSEWAware=1>;7015defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB",7016 AllWidenableFloatVectors, isSEWAware=1>;7017 7018//===----------------------------------------------------------------------===//7019// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions7020//===----------------------------------------------------------------------===//7021defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL",7022 AllFloatVectors, isSEWAware=1>;7023defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfdiv", "PseudoVFDIV",7024 AllFloatVectors, isSEWAware=1>;7025defm : VPatBinaryV_VX_RM<"int_riscv_vfrdiv", "PseudoVFRDIV",7026 AllFloatVectors, isSEWAware=1>;7027 7028//===----------------------------------------------------------------------===//7029// 13.5. Vector Widening Floating-Point Multiply7030//===----------------------------------------------------------------------===//7031defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwmul", "PseudoVFWMUL",7032 AllWidenableFloatVectors, isSEWAware=1>;7033 7034//===----------------------------------------------------------------------===//7035// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions7036//===----------------------------------------------------------------------===//7037defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmacc", "PseudoVFMACC",7038 AllFloatVectors, isSEWAware=1>;7039defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmacc", "PseudoVFNMACC",7040 AllFloatVectors, isSEWAware=1>;7041defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsac", "PseudoVFMSAC",7042 AllFloatVectors, isSEWAware=1>;7043defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsac", "PseudoVFNMSAC",7044 AllFloatVectors, isSEWAware=1>;7045defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmadd", "PseudoVFMADD",7046 AllFloatVectors, isSEWAware=1>;7047defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmadd", "PseudoVFNMADD",7048 AllFloatVectors, isSEWAware=1>;7049defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsub", "PseudoVFMSUB",7050 AllFloatVectors, isSEWAware=1>;7051defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsub", "PseudoVFNMSUB",7052 AllFloatVectors, isSEWAware=1>;7053 7054//===----------------------------------------------------------------------===//7055// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions7056//===----------------------------------------------------------------------===//7057defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmacc", "PseudoVFWMACC",7058 AllWidenableFloatVectors, isSEWAware=1>;7059defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmacc", "PseudoVFWNMACC",7060 AllWidenableFloatVectors, isSEWAware=1>;7061defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC",7062 AllWidenableFloatVectors, isSEWAware=1>;7063defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC",7064 AllWidenableFloatVectors, isSEWAware=1>;7065 7066//===----------------------------------------------------------------------===//7067// 13.8. Vector Floating-Point Square-Root Instruction7068//===----------------------------------------------------------------------===//7069defm : VPatUnaryV_V_RM<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors, isSEWAware=1>;7070 7071//===----------------------------------------------------------------------===//7072// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction7073//===----------------------------------------------------------------------===//7074defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7", AllFloatVectors, isSEWAware=1>;7075 7076//===----------------------------------------------------------------------===//7077// 13.10. Vector Floating-Point Reciprocal Estimate Instruction7078//===----------------------------------------------------------------------===//7079defm : VPatUnaryV_V_RM<"int_riscv_vfrec7", "PseudoVFREC7", AllFloatVectors, isSEWAware=1>;7080 7081//===----------------------------------------------------------------------===//7082// 13.11. Vector Floating-Point Min/Max Instructions7083//===----------------------------------------------------------------------===//7084defm : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors,7085 isSEWAware=1>;7086defm : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors,7087 isSEWAware=1>;7088 7089//===----------------------------------------------------------------------===//7090// 13.12. Vector Floating-Point Sign-Injection Instructions7091//===----------------------------------------------------------------------===//7092defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnj", "PseudoVFSGNJ", AllFloatVectors,7093 isSEWAware=1>;7094defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjn", "PseudoVFSGNJN", AllFloatVectors,7095 isSEWAware=1>;7096defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjx", "PseudoVFSGNJX", AllFloatVectors,7097 isSEWAware=1>;7098 7099//===----------------------------------------------------------------------===//7100// 13.13. Vector Floating-Point Compare Instructions7101//===----------------------------------------------------------------------===//7102defm : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ", AllFloatVectors>;7103defm : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE", AllFloatVectors>;7104defm : VPatBinaryM_VV_VX<"int_riscv_vmflt", "PseudoVMFLT", AllFloatVectors>;7105defm : VPatBinaryM_VV_VX<"int_riscv_vmfne", "PseudoVMFNE", AllFloatVectors>;7106defm : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT", AllFloatVectors>;7107defm : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>;7108defm : VPatBinarySwappedM_VV<"int_riscv_vmfgt", "PseudoVMFLT", AllFloatVectors>;7109defm : VPatBinarySwappedM_VV<"int_riscv_vmfge", "PseudoVMFLE", AllFloatVectors>;7110 7111//===----------------------------------------------------------------------===//7112// 13.14. Vector Floating-Point Classify Instruction7113//===----------------------------------------------------------------------===//7114defm : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">;7115 7116//===----------------------------------------------------------------------===//7117// 13.15. Vector Floating-Point Merge Instruction7118//===----------------------------------------------------------------------===//7119// We can use vmerge.vvm to support vector-vector vfmerge.7120// NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses7121// int_riscv_vmerge. Support both for compatibility.7122foreach vti = AllFloatAndBF16Vectors in {7123 let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in7124 defm : VPatBinaryCarryInTAIL<"int_riscv_vmerge", "PseudoVMERGE", "VVM",7125 vti.Vector,7126 vti.Vector, vti.Vector, vti.Mask,7127 vti.Log2SEW, vti.LMul, vti.RegClass,7128 vti.RegClass, vti.RegClass>;7129}7130 7131foreach fvti = AllFloatVectors in {7132 let Predicates = GetVTypePredicates<fvti>.Predicates in {7133 defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVFMERGE",7134 "V"#fvti.ScalarSuffix#"M",7135 fvti.Vector,7136 fvti.Vector, fvti.Scalar, fvti.Mask,7137 fvti.Log2SEW, fvti.LMul, fvti.RegClass,7138 fvti.RegClass, fvti.ScalarRegClass>;7139 7140 defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX);7141 def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$passthru),7142 (fvti.Vector fvti.RegClass:$rs2),7143 (fvti.Scalar (fpimm0)),7144 (fvti.Mask VMV0:$vm), VLOpFrag)),7145 (instr fvti.RegClass:$passthru, fvti.RegClass:$rs2, 0,7146 (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW)>;7147 }7148}7149 7150//===----------------------------------------------------------------------===//7151// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions7152//===----------------------------------------------------------------------===//7153defm : VPatConversionVI_VF_RTZ<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_RTZ_X_F">;7154defm : VPatConversionVI_VF_RTZ<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_RTZ_XU_F">;7155defm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_X_F">;7156defm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_XU_F">;7157defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_xu_f_v", "PseudoVFCVT_RTZ_XU_F">;7158defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_x_f_v", "PseudoVFCVT_RTZ_X_F">;7159defm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_x_v", "PseudoVFCVT_F_X",7160 isSEWAware=1>;7161defm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU",7162 isSEWAware=1>;7163 7164//===----------------------------------------------------------------------===//7165// 13.18. Widening Floating-Point/Integer Type-Convert Instructions7166//===----------------------------------------------------------------------===//7167defm : VPatConversionWI_VF_RTZ<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_RTZ_XU_F">;7168defm : VPatConversionWI_VF_RTZ<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_RTZ_X_F">;7169defm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_xu_f_v", "PseudoVFWCVT_XU_F">;7170defm : VPatConversionWI_VF_RM<"int_riscv_vfwcvt_x_f_v", "PseudoVFWCVT_X_F">;7171defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_xu_f_v", "PseudoVFWCVT_RTZ_XU_F">;7172defm : VPatConversionWI_VF<"int_riscv_vfwcvt_rtz_x_f_v", "PseudoVFWCVT_RTZ_X_F">;7173defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU",7174 isSEWAware=1>;7175defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X",7176 isSEWAware=1>;7177defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F",7178 isSEWAware=1>;7179 7180//===----------------------------------------------------------------------===//7181// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions7182//===----------------------------------------------------------------------===//7183defm : VPatConversionVI_WF_RTZ<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">;7184defm : VPatConversionVI_WF_RTZ<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_RTZ_X_F">;7185defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F">;7186defm : VPatConversionVI_WF_RM<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F">;7187defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F">;7188defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">;7189defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU",7190 isSEWAware=1>;7191defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X",7192 isSEWAware=1>;7193defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",7194 AllWidenableFloatVectors, isSEWAware=1>;7195defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F",7196 isSEWAware=1>;7197 7198//===----------------------------------------------------------------------===//7199// 14. Vector Reduction Operations7200//===----------------------------------------------------------------------===//7201 7202//===----------------------------------------------------------------------===//7203// 14.1. Vector Single-Width Integer Reduction Instructions7204//===----------------------------------------------------------------------===//7205defm : VPatReductionV_VS<"int_riscv_vredsum", "PseudoVREDSUM">;7206defm : VPatReductionV_VS<"int_riscv_vredand", "PseudoVREDAND">;7207defm : VPatReductionV_VS<"int_riscv_vredor", "PseudoVREDOR">;7208defm : VPatReductionV_VS<"int_riscv_vredxor", "PseudoVREDXOR">;7209defm : VPatReductionV_VS<"int_riscv_vredminu", "PseudoVREDMINU">;7210defm : VPatReductionV_VS<"int_riscv_vredmin", "PseudoVREDMIN">;7211defm : VPatReductionV_VS<"int_riscv_vredmaxu", "PseudoVREDMAXU">;7212defm : VPatReductionV_VS<"int_riscv_vredmax", "PseudoVREDMAX">;7213 7214//===----------------------------------------------------------------------===//7215// 14.2. Vector Widening Integer Reduction Instructions7216//===----------------------------------------------------------------------===//7217defm : VPatReductionW_VS<"int_riscv_vwredsumu", "PseudoVWREDSUMU">;7218defm : VPatReductionW_VS<"int_riscv_vwredsum", "PseudoVWREDSUM">;7219 7220//===----------------------------------------------------------------------===//7221// 14.3. Vector Single-Width Floating-Point Reduction Instructions7222//===----------------------------------------------------------------------===//7223defm : VPatReductionV_VS_RM<"int_riscv_vfredosum", "PseudoVFREDOSUM", IsFloat=1>;7224defm : VPatReductionV_VS_RM<"int_riscv_vfredusum", "PseudoVFREDUSUM", IsFloat=1>;7225defm : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", IsFloat=1>;7226defm : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", IsFloat=1>;7227 7228//===----------------------------------------------------------------------===//7229// 14.4. Vector Widening Floating-Point Reduction Instructions7230//===----------------------------------------------------------------------===//7231defm : VPatReductionW_VS_RM<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", IsFloat=1>;7232defm : VPatReductionW_VS_RM<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", IsFloat=1>;7233 7234//===----------------------------------------------------------------------===//7235// 15. Vector Mask Instructions7236//===----------------------------------------------------------------------===//7237 7238//===----------------------------------------------------------------------===//7239// 15.1 Vector Mask-Register Logical Instructions7240//===----------------------------------------------------------------------===//7241defm : VPatBinaryM_MM<"int_riscv_vmand", "PseudoVMAND">;7242defm : VPatBinaryM_MM<"int_riscv_vmnand", "PseudoVMNAND">;7243defm : VPatBinaryM_MM<"int_riscv_vmandn", "PseudoVMANDN">;7244defm : VPatBinaryM_MM<"int_riscv_vmxor", "PseudoVMXOR">;7245defm : VPatBinaryM_MM<"int_riscv_vmor", "PseudoVMOR">;7246defm : VPatBinaryM_MM<"int_riscv_vmnor", "PseudoVMNOR">;7247defm : VPatBinaryM_MM<"int_riscv_vmorn", "PseudoVMORN">;7248defm : VPatBinaryM_MM<"int_riscv_vmxnor", "PseudoVMXNOR">;7249 7250// pseudo instructions7251defm : VPatNullaryM<"int_riscv_vmclr", "PseudoVMCLR">;7252defm : VPatNullaryM<"int_riscv_vmset", "PseudoVMSET">;7253 7254//===----------------------------------------------------------------------===//7255// 15.2. Vector count population in mask vcpop.m7256//===----------------------------------------------------------------------===//7257defm : VPatUnaryS_M<"int_riscv_vcpop", "PseudoVCPOP">;7258 7259//===----------------------------------------------------------------------===//7260// 15.3. vfirst find-first-set mask bit7261//===----------------------------------------------------------------------===//7262defm : VPatUnaryS_M<"int_riscv_vfirst", "PseudoVFIRST">;7263 7264//===----------------------------------------------------------------------===//7265// 15.4. vmsbf.m set-before-first mask bit7266//===----------------------------------------------------------------------===//7267defm : VPatUnaryM_M<"int_riscv_vmsbf", "PseudoVMSBF">;7268 7269//===----------------------------------------------------------------------===//7270// 15.5. vmsif.m set-including-first mask bit7271//===----------------------------------------------------------------------===//7272defm : VPatUnaryM_M<"int_riscv_vmsif", "PseudoVMSIF">;7273 7274//===----------------------------------------------------------------------===//7275// 15.6. vmsof.m set-only-first mask bit7276//===----------------------------------------------------------------------===//7277defm : VPatUnaryM_M<"int_riscv_vmsof", "PseudoVMSOF">;7278 7279//===----------------------------------------------------------------------===//7280// 15.8. Vector Iota Instruction7281//===----------------------------------------------------------------------===//7282defm : VPatUnaryV_M<"int_riscv_viota", "PseudoVIOTA">;7283 7284//===----------------------------------------------------------------------===//7285// 15.9. Vector Element Index Instruction7286//===----------------------------------------------------------------------===//7287defm : VPatNullaryV<"int_riscv_vid", "PseudoVID">;7288 7289 7290//===----------------------------------------------------------------------===//7291// 16. Vector Permutation Instructions7292//===----------------------------------------------------------------------===//7293 7294//===----------------------------------------------------------------------===//7295// 16.1. Integer Scalar Move Instructions7296//===----------------------------------------------------------------------===//7297 7298foreach vti = NoGroupIntegerVectors in {7299 let Predicates = GetVTypePredicates<vti>.Predicates in7300 def : Pat<(XLenVT (riscv_vmv_x_s (vti.Vector vti.RegClass:$rs2))),7301 (PseudoVMV_X_S $rs2, vti.Log2SEW)>;7302 // vmv.s.x is handled with a custom node in RISCVInstrInfoVVLPatterns.td7303}7304 7305//===----------------------------------------------------------------------===//7306// 16.3. Vector Slide Instructions7307//===----------------------------------------------------------------------===//7308defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllVectors, uimm5>;7309defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllVectors, uimm5>;7310 7311defm : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>;7312defm : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;7313 7314defm : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP", AllFloatVectors>;7315defm : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN", AllFloatVectors>;7316 7317//===----------------------------------------------------------------------===//7318// 16.4. Vector Register Gather Instructions7319//===----------------------------------------------------------------------===//7320defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",7321 AllVectors, uimm5>;7322defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",7323 eew=16, vtilist=AllVectors>;7324 7325//===----------------------------------------------------------------------===//7326// 16.5. Vector Compress Instruction7327//===----------------------------------------------------------------------===//7328defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllVectors>;7329 7330// Include the non-intrinsic ISel patterns7331include "RISCVInstrInfoVVLPatterns.td"7332include "RISCVInstrInfoVSDPatterns.td"7333