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1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8///9/// This file contains the required infrastructure and VL patterns to10/// support code generation for the standard 'V' (Vector) extension, version11/// version 1.0.12///13/// This file is included from and depends upon RISCVInstrInfoVPseudos.td14///15/// Note: the patterns for RVV intrinsics are found in16/// RISCVInstrInfoVPseudos.td.17///18//===----------------------------------------------------------------------===//19 20// Splats an 64-bit value that has been split into two i32 parts. This is21// expanded late to two scalar stores and a stride 0 vector load.22// The first operand is passthru operand.23//24// This is only present to generate the correct TableGen SDNode description,25// it is lowered before instruction selection.26// FIXME: I'm not sure the types here are entirely correct.27// Returns a vector. Operand 0 is a passthru, operand 1 and 2 are i32 scalars, operand 3 is VL28def riscv_splat_vector_split_i64_vl : RVSDNode<"SPLAT_VECTOR_SPLIT_I64_VL",29 SDTypeProfile<1, 4, [SDTCisVec<0>,30 SDTCVecEltisVT<0, i64>,31 SDTCisSameAs<1, 0>,32 SDTCisVT<2, i32>,33 SDTCisVT<3, i32>,34 SDTCisVT<4, XLenVT>]>>;35 36// RISC-V vector tuple type version of INSERT_SUBVECTOR/EXTRACT_SUBVECTOR.37def riscv_tuple_insert : RVSDNode<"TUPLE_INSERT",38 SDTypeProfile<1, 3, [SDTCisSameAs<1, 0>,39 SDTCisVec<2>,40 SDTCisVT<3, i32>]>>;41def riscv_tuple_extract : RVSDNode<"TUPLE_EXTRACT",42 SDTypeProfile<1, 2, [SDTCisVec<0>,43 SDTCisVT<2, i32>]>>;44 45 46//===----------------------------------------------------------------------===//47// Helpers to define the VL patterns.48//===----------------------------------------------------------------------===//49 50def SDT_RISCVIntUnOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,51 SDTCisSameAs<0, 2>,52 SDTCisVec<0>, SDTCisInt<0>,53 SDTCVecEltisVT<3, i1>,54 SDTCisSameNumEltsAs<0, 3>,55 SDTCisVT<4, XLenVT>]>;56 57def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,58 SDTCisSameAs<0, 2>,59 SDTCisVec<0>, SDTCisInt<0>,60 SDTCisSameAs<0, 3>,61 SDTCVecEltisVT<4, i1>,62 SDTCisSameNumEltsAs<0, 4>,63 SDTCisVT<5, XLenVT>]>;64 65// Input: (vector, vector/scalar, passthru, mask, roundmode, vl)66def SDT_RISCVVNBinOp_RM_VL : SDTypeProfile<1, 6, [SDTCisVec<0>, SDTCisInt<0>,67 SDTCisSameAs<0, 3>,68 SDTCisSameNumEltsAs<0, 1>,69 SDTCisVec<1>,70 SDTCisOpSmallerThanOp<2, 1>,71 SDTCisSameAs<0, 2>,72 SDTCisSameNumEltsAs<0, 4>,73 SDTCVecEltisVT<4, i1>,74 SDTCisVT<5, XLenVT>,75 SDTCisVT<6, XLenVT>]>;76 77def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,78 SDTCisVec<0>, SDTCisFP<0>,79 SDTCVecEltisVT<2, i1>,80 SDTCisSameNumEltsAs<0, 2>,81 SDTCisVT<3, XLenVT>]>;82def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,83 SDTCisSameAs<0, 2>,84 SDTCisVec<0>, SDTCisFP<0>,85 SDTCisSameAs<0, 3>,86 SDTCVecEltisVT<4, i1>,87 SDTCisSameNumEltsAs<0, 4>,88 SDTCisVT<5, XLenVT>]>;89 90def SDT_RISCVCopySign_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,91 SDTCisSameAs<0, 2>,92 SDTCisVec<0>, SDTCisFP<0>,93 SDTCisSameAs<0, 3>,94 SDTCVecEltisVT<4, i1>,95 SDTCisSameNumEltsAs<0, 4>,96 SDTCisVT<5, XLenVT>]>;97 98// VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand99// for the VL value to be used for the operation. The first operand is100// passthru operand.101def riscv_vmv_v_v_vl : RVSDNode<"VMV_V_V_VL",102 SDTypeProfile<1, 3, [SDTCisVec<0>,103 SDTCisSameAs<0, 1>,104 SDTCisSameAs<0, 2>,105 SDTCisVT<3, XLenVT>]>>;106 107// VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand108// for the VL value to be used for the operation. The first operand is109// passthru operand.110def riscv_vmv_v_x_vl : RVSDNode<"VMV_V_X_VL",111 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>,112 SDTCisSameAs<0, 1>,113 SDTCisVT<2, XLenVT>,114 SDTCisVT<3, XLenVT>]>>;115 116// VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand117// for the VL value to be used for the operation. The first operand is118// passthru operand.119def riscv_vfmv_v_f_vl : RVSDNode<"VFMV_V_F_VL",120 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,121 SDTCisSameAs<0, 1>,122 SDTCisEltOfVec<2, 0>,123 SDTCisVT<3, XLenVT>]>>;124 125// VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.126def riscv_vmv_s_x_vl : RVSDNode<"VMV_S_X_VL",127 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,128 SDTCisInt<0>,129 SDTCisVT<2, XLenVT>,130 SDTCisVT<3, XLenVT>]>>;131 132// VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.133def riscv_vfmv_s_f_vl : RVSDNode<"VFMV_S_F_VL",134 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,135 SDTCisFP<0>,136 SDTCisEltOfVec<2, 0>,137 SDTCisVT<3, XLenVT>]>>;138 139// Vector binary ops with a passthru as a third operand, a mask as a fourth140// operand, and VL as a fifth operand.141let HasPassthruOp = true, HasMaskOp = true in {142 def riscv_add_vl : RVSDNode<"ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;143 def riscv_sub_vl : RVSDNode<"SUB_VL", SDT_RISCVIntBinOp_VL>;144 def riscv_mul_vl : RVSDNode<"MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;145 def riscv_mulhs_vl : RVSDNode<"MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;146 def riscv_mulhu_vl : RVSDNode<"MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;147 def riscv_and_vl : RVSDNode<"AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;148 def riscv_or_vl : RVSDNode<"OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;149 def riscv_xor_vl : RVSDNode<"XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;150 def riscv_sdiv_vl : RVSDNode<"SDIV_VL", SDT_RISCVIntBinOp_VL>;151 def riscv_srem_vl : RVSDNode<"SREM_VL", SDT_RISCVIntBinOp_VL>;152 def riscv_udiv_vl : RVSDNode<"UDIV_VL", SDT_RISCVIntBinOp_VL>;153 def riscv_urem_vl : RVSDNode<"UREM_VL", SDT_RISCVIntBinOp_VL>;154 def riscv_shl_vl : RVSDNode<"SHL_VL", SDT_RISCVIntBinOp_VL>;155 def riscv_sra_vl : RVSDNode<"SRA_VL", SDT_RISCVIntBinOp_VL>;156 def riscv_srl_vl : RVSDNode<"SRL_VL", SDT_RISCVIntBinOp_VL>;157 def riscv_rotl_vl : RVSDNode<"ROTL_VL", SDT_RISCVIntBinOp_VL>;158 def riscv_rotr_vl : RVSDNode<"ROTR_VL", SDT_RISCVIntBinOp_VL>;159 def riscv_smin_vl : RVSDNode<"SMIN_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;160 def riscv_smax_vl : RVSDNode<"SMAX_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;161 def riscv_umin_vl : RVSDNode<"UMIN_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;162 def riscv_umax_vl : RVSDNode<"UMAX_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;163 164 def riscv_bitreverse_vl : RVSDNode<"BITREVERSE_VL", SDT_RISCVIntUnOp_VL>;165 def riscv_bswap_vl : RVSDNode<"BSWAP_VL", SDT_RISCVIntUnOp_VL>;166 def riscv_ctlz_vl : RVSDNode<"CTLZ_VL", SDT_RISCVIntUnOp_VL>;167 def riscv_cttz_vl : RVSDNode<"CTTZ_VL", SDT_RISCVIntUnOp_VL>;168 def riscv_ctpop_vl : RVSDNode<"CTPOP_VL", SDT_RISCVIntUnOp_VL>;169 170 // Averaging adds of signed integers.171 def riscv_avgfloors_vl : RVSDNode<"AVGFLOORS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;172 // Averaging adds of unsigned integers.173 def riscv_avgflooru_vl : RVSDNode<"AVGFLOORU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;174 // Rounding averaging adds of signed integers.175 def riscv_avgceils_vl : RVSDNode<"AVGCEILS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;176 // Rounding averaging adds of unsigned integers.177 def riscv_avgceilu_vl : RVSDNode<"AVGCEILU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;178 def riscv_saddsat_vl : RVSDNode<"SADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;179 def riscv_uaddsat_vl : RVSDNode<"UADDSAT_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;180 def riscv_ssubsat_vl : RVSDNode<"SSUBSAT_VL", SDT_RISCVIntBinOp_VL>;181 def riscv_usubsat_vl : RVSDNode<"USUBSAT_VL", SDT_RISCVIntBinOp_VL>;182 183 def riscv_fadd_vl : RVSDNode<"FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>;184 def riscv_fsub_vl : RVSDNode<"FSUB_VL", SDT_RISCVFPBinOp_VL>;185 def riscv_fmul_vl : RVSDNode<"FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>;186 def riscv_fdiv_vl : RVSDNode<"FDIV_VL", SDT_RISCVFPBinOp_VL>;187} // let HasPassthruOp = true, HasMaskOp = true188 189// Vector unary ops with a mask as a second operand and VL as a third operand.190let HasMaskOp = true in {191 def riscv_fneg_vl : RVSDNode<"FNEG_VL", SDT_RISCVFPUnOp_VL>;192 def riscv_fabs_vl : RVSDNode<"FABS_VL", SDT_RISCVFPUnOp_VL>;193 def riscv_fsqrt_vl : RVSDNode<"FSQRT_VL", SDT_RISCVFPUnOp_VL>;194} // let HasMaskOp = true195 196let HasPassthruOp = true, HasMaskOp = true in {197 def riscv_fcopysign_vl : RVSDNode<"FCOPYSIGN_VL", SDT_RISCVCopySign_VL>;198 def riscv_vfmin_vl : RVSDNode<"VFMIN_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>;199 def riscv_vfmax_vl : RVSDNode<"VFMAX_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>;200} // let HasPassthruOp = true, HasMaskOp = true201 202let IsStrictFP = true, HasPassthruOp = true, HasMaskOp = true in {203 def riscv_strict_fadd_vl : RVSDNode<"STRICT_FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative, SDNPHasChain]>;204 def riscv_strict_fsub_vl : RVSDNode<"STRICT_FSUB_VL", SDT_RISCVFPBinOp_VL, [SDNPHasChain]>;205 def riscv_strict_fmul_vl : RVSDNode<"STRICT_FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative, SDNPHasChain]>;206 def riscv_strict_fdiv_vl : RVSDNode<"STRICT_FDIV_VL", SDT_RISCVFPBinOp_VL, [SDNPHasChain]>;207} // let IsStrictFP = true, HasPassthruOp = true, HasMaskOp = true208 209let IsStrictFP = true, HasMaskOp = true in210def riscv_strict_fsqrt_vl : RVSDNode<"STRICT_FSQRT_VL", SDT_RISCVFPUnOp_VL, [SDNPHasChain]>;211 212def any_riscv_fadd_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),213 [(riscv_fadd_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),214 (riscv_strict_fadd_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl)]>;215def any_riscv_fsub_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),216 [(riscv_fsub_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),217 (riscv_strict_fsub_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl)]>;218def any_riscv_fmul_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),219 [(riscv_fmul_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),220 (riscv_strict_fmul_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl)]>;221def any_riscv_fdiv_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),222 [(riscv_fdiv_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl),223 (riscv_strict_fdiv_vl node:$lhs, node:$rhs, node:$passthru, node:$mask, node:$vl)]>;224def any_riscv_fsqrt_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),225 [(riscv_fsqrt_vl node:$src, node:$mask, node:$vl),226 (riscv_strict_fsqrt_vl node:$src, node:$mask, node:$vl)]>;227 228let HasMaskOp = true in229def riscv_fclass_vl : RVSDNode<"FCLASS_VL",230 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,231 SDTCisFP<1>, SDTCisVec<1>,232 SDTCisSameSizeAs<0, 1>,233 SDTCisSameNumEltsAs<0, 1>,234 SDTCVecEltisVT<2, i1>,235 SDTCisSameNumEltsAs<0, 2>,236 SDTCisVT<3, XLenVT>]>>;237 238def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,239 SDTCisSameAs<0, 2>,240 SDTCisSameAs<0, 3>,241 SDTCisVec<0>, SDTCisFP<0>,242 SDTCVecEltisVT<4, i1>,243 SDTCisSameNumEltsAs<0, 4>,244 SDTCisVT<5, XLenVT>]>;245 246let HasMaskOp = true in {247 // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.248 def riscv_vfmadd_vl : RVSDNode<"VFMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>;249 def riscv_vfnmadd_vl : RVSDNode<"VFNMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>;250 def riscv_vfmsub_vl : RVSDNode<"VFMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>;251 def riscv_vfnmsub_vl : RVSDNode<"VFNMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>;252}253 254def SDT_RISCVWVecFMA_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>,255 SDTCisVec<1>, SDTCisFP<1>,256 SDTCisOpSmallerThanOp<1, 0>,257 SDTCisSameNumEltsAs<0, 1>,258 SDTCisSameAs<1, 2>,259 SDTCisSameAs<0, 3>,260 SDTCVecEltisVT<4, i1>,261 SDTCisSameNumEltsAs<0, 4>,262 SDTCisVT<5, XLenVT>]>;263 264let HasMaskOp = true in {265 // Vector widening FMA ops with a mask as a fourth operand and VL as a fifth266 // operand.267 def riscv_vfwmadd_vl : RVSDNode<"VFWMADD_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>;268 def riscv_vfwnmadd_vl : RVSDNode<"VFWNMADD_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>;269 def riscv_vfwmsub_vl : RVSDNode<"VFWMSUB_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>;270 def riscv_vfwnmsub_vl : RVSDNode<"VFWNMSUB_VL", SDT_RISCVWVecFMA_VL, [SDNPCommutative]>;271 272 let IsStrictFP = true in {273 def riscv_strict_vfmadd_vl : RVSDNode<"STRICT_VFMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>;274 def riscv_strict_vfnmadd_vl : RVSDNode<"STRICT_VFNMADD_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>;275 def riscv_strict_vfmsub_vl : RVSDNode<"STRICT_VFMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>;276 def riscv_strict_vfnmsub_vl : RVSDNode<"STRICT_VFNMSUB_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative, SDNPHasChain]>;277 } // let IsStrictFP = true278} // let HasMaskOp = true279 280def any_riscv_vfmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),281 [(riscv_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),282 (riscv_strict_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;283def any_riscv_vfnmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),284 [(riscv_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),285 (riscv_strict_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;286def any_riscv_vfmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),287 [(riscv_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),288 (riscv_strict_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;289def any_riscv_vfnmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),290 [(riscv_vfnmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),291 (riscv_strict_vfnmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;292 293def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [294 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>,295 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>296]>;297def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [298 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>,299 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>300]>;301 302let HasMaskOp = true in {303 def riscv_fpround_vl : RVSDNode<"FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>;304 def riscv_fpextend_vl : RVSDNode<"FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>;305 306 // Matches the semantics of the vfcnvt.rod function (Convert double-width307 // float to single-width float, rounding towards odd). Takes a double-width308 // float vector and produces a single-width float vector. Also has a mask and309 // VL operand.310 def riscv_fncvt_rod_vl : RVSDNode<"VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>;311 312 let IsStrictFP = true in {313 def riscv_strict_fpround_vl : RVSDNode<"STRICT_FP_ROUND_VL", SDT_RISCVFPRoundOp_VL, [SDNPHasChain]>;314 def riscv_strict_fpextend_vl : RVSDNode<"STRICT_FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL, [SDNPHasChain]>;315 def riscv_strict_fncvt_rod_vl : RVSDNode<"STRICT_VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL, [SDNPHasChain]>;316 } // let IsStrictFP = true317} // let HasMaskOp = true318 319def any_riscv_fpround_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),320 [(riscv_fpround_vl node:$src, node:$mask, node:$vl),321 (riscv_strict_fpround_vl node:$src, node:$mask, node:$vl)]>;322def any_riscv_fpextend_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),323 [(riscv_fpextend_vl node:$src, node:$mask, node:$vl),324 (riscv_strict_fpextend_vl node:$src, node:$mask, node:$vl)]>;325def any_riscv_fncvt_rod_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),326 [(riscv_fncvt_rod_vl node:$src, node:$mask, node:$vl),327 (riscv_strict_fncvt_rod_vl node:$src, node:$mask, node:$vl)]>;328 329def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [330 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>,331 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>332]>;333def SDT_RISCVFP2IOp_RM_VL : SDTypeProfile<1, 4, [334 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>,335 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>,336 SDTCisVT<4, XLenVT> // Rounding mode337]>;338 339def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [340 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>,341 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>342]>;343def SDT_RISCVI2FPOp_RM_VL : SDTypeProfile<1, 4, [344 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>,345 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>,346 SDTCisVT<4, XLenVT> // Rounding mode347]>;348 349def SDT_RISCVSETCCOP_VL : SDTypeProfile<1, 6, [350 SDTCVecEltisVT<0, i1>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>,351 SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>, SDTCisSameAs<0, 4>,352 SDTCisSameAs<0, 5>, SDTCisVT<6, XLenVT>]>;353 354// Float -> Int355 356let HasMaskOp = true in {357 def riscv_vfcvt_rm_xu_f_vl : RVSDNode<"VFCVT_RM_XU_F_VL", SDT_RISCVFP2IOp_RM_VL>;358 def riscv_vfcvt_rm_x_f_vl : RVSDNode<"VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL>;359 360 def riscv_vfcvt_rtz_xu_f_vl : RVSDNode<"VFCVT_RTZ_XU_F_VL", SDT_RISCVFP2IOp_VL>;361 def riscv_vfcvt_rtz_x_f_vl : RVSDNode<"VFCVT_RTZ_X_F_VL", SDT_RISCVFP2IOp_VL>;362 363 let IsStrictFP = true in {364 def riscv_strict_vfcvt_rm_x_f_vl : RVSDNode<"STRICT_VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL, [SDNPHasChain]>;365 def riscv_strict_vfcvt_rtz_xu_f_vl : RVSDNode<"STRICT_VFCVT_RTZ_XU_F_VL", SDT_RISCVFP2IOp_VL, [SDNPHasChain]>;366 def riscv_strict_vfcvt_rtz_x_f_vl : RVSDNode<"STRICT_VFCVT_RTZ_X_F_VL", SDT_RISCVFP2IOp_VL, [SDNPHasChain]>;367 } // let IsStrictFP = true368} // let HasMaskOp = true369 370def any_riscv_vfcvt_rm_x_f_vl : PatFrags<(ops node:$src, node:$mask, node:$vl, node:$rm),371 [(riscv_vfcvt_rm_x_f_vl node:$src, node:$mask, node:$vl, node:$rm),372 (riscv_strict_vfcvt_rm_x_f_vl node:$src, node:$mask, node:$vl, node:$rm)]>;373def any_riscv_vfcvt_rtz_xu_f_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),374 [(riscv_vfcvt_rtz_xu_f_vl node:$src, node:$mask, node:$vl),375 (riscv_strict_vfcvt_rtz_xu_f_vl node:$src, node:$mask, node:$vl)]>;376def any_riscv_vfcvt_rtz_x_f_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),377 [(riscv_vfcvt_rtz_x_f_vl node:$src, node:$mask, node:$vl),378 (riscv_strict_vfcvt_rtz_x_f_vl node:$src, node:$mask, node:$vl)]>;379 380// Int -> Float381 382let HasMaskOp = true in {383 def riscv_sint_to_fp_vl : RVSDNode<"SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>;384 def riscv_uint_to_fp_vl : RVSDNode<"UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>;385 def riscv_vfcvt_rm_f_xu_vl : RVSDNode<"VFCVT_RM_F_XU_VL", SDT_RISCVI2FPOp_RM_VL>;386 def riscv_vfcvt_rm_f_x_vl : RVSDNode<"VFCVT_RM_F_X_VL", SDT_RISCVI2FPOp_RM_VL>;387 388 let IsStrictFP = true in {389 def riscv_strict_sint_to_fp_vl : RVSDNode<"STRICT_SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL, [SDNPHasChain]>;390 def riscv_strict_uint_to_fp_vl : RVSDNode<"STRICT_UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL, [SDNPHasChain]>;391 } // let IsStrictFP = true392} // let HasMaskOp = true393 394def any_riscv_sint_to_fp_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),395 [(riscv_sint_to_fp_vl node:$src, node:$mask, node:$vl),396 (riscv_strict_sint_to_fp_vl node:$src, node:$mask, node:$vl)]>;397def any_riscv_uint_to_fp_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),398 [(riscv_uint_to_fp_vl node:$src, node:$mask, node:$vl),399 (riscv_strict_uint_to_fp_vl node:$src, node:$mask, node:$vl)]>;400 401let HasMaskOp = true in {402 def riscv_vfround_noexcept_vl: RVSDNode<"VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL>;403 404 let IsStrictFP = true in405 def riscv_strict_vfround_noexcept_vl: RVSDNode<"STRICT_VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL, [SDNPHasChain]>;406}407 408def any_riscv_vfround_noexcept_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),409 [(riscv_vfround_noexcept_vl node:$src, node:$mask, node:$vl),410 (riscv_strict_vfround_noexcept_vl node:$src, node:$mask, node:$vl)]>;411 412// Vector compare producing a mask. Fourth operand is input mask. Fifth413// operand is VL.414let HasPassthruOp = true, HasMaskOp = true in415def riscv_setcc_vl : RVSDNode<"SETCC_VL", SDT_RISCVSETCCOP_VL>;416 417let IsStrictFP = true, HasMaskOp = true in {418 def riscv_strict_fsetcc_vl : RVSDNode<"STRICT_FSETCC_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>;419 def riscv_strict_fsetccs_vl : RVSDNode<"STRICT_FSETCCS_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>;420} // let IsStrictFP = true, HasMaskOp = true421 422def any_riscv_fsetcc_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),423 [(riscv_setcc_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),424 (riscv_strict_fsetcc_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl)]>;425def any_riscv_fsetccs_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),426 [(riscv_setcc_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),427 (riscv_strict_fsetccs_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl)]>;428 429let HasMaskOp = true in {430 // Matches the semantics of vrgather.vx and vrgather.vv with extra operands431 // for passthru and VL, except that out of bound indices result in a poison432 // result not zero. Operands are (src, index, mask, passthru, vl).433 def riscv_vrgather_vx_vl : RVSDNode<"VRGATHER_VX_VL",434 SDTypeProfile<1, 5, [SDTCisVec<0>,435 SDTCisSameAs<0, 1>,436 SDTCisVT<2, XLenVT>,437 SDTCisSameAs<0, 3>,438 SDTCVecEltisVT<4, i1>,439 SDTCisSameNumEltsAs<0, 4>,440 SDTCisVT<5, XLenVT>]>>;441 def riscv_vrgather_vv_vl : RVSDNode<"VRGATHER_VV_VL",442 SDTypeProfile<1, 5, [SDTCisVec<0>,443 SDTCisSameAs<0, 1>,444 SDTCisInt<2>,445 SDTCisSameNumEltsAs<0, 2>,446 SDTCisSameSizeAs<0, 2>,447 SDTCisSameAs<0, 3>,448 SDTCVecEltisVT<4, i1>,449 SDTCisSameNumEltsAs<0, 4>,450 SDTCisVT<5, XLenVT>]>>;451 def riscv_vrgatherei16_vv_vl : RVSDNode<"VRGATHEREI16_VV_VL",452 SDTypeProfile<1, 5, [SDTCisVec<0>,453 SDTCisSameAs<0, 1>,454 SDTCisInt<2>,455 SDTCVecEltisVT<2, i16>,456 SDTCisSameNumEltsAs<0, 2>,457 SDTCisSameAs<0, 3>,458 SDTCVecEltisVT<4, i1>,459 SDTCisSameNumEltsAs<0, 4>,460 SDTCisVT<5, XLenVT>]>>;461} // let HasMaskOp = true462 463def SDT_RISCVVMERGE_VL : SDTypeProfile<1, 5, [464 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>,465 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameAs<0, 4>,466 SDTCisVT<5, XLenVT>467]>;468 469// General vmerge node with mask, true, false, passthru, and vl operands.470// Tail agnostic vselect can be implemented by setting passthru to undef.471let HasPassthruOp = true in472def riscv_vmerge_vl : RVSDNode<"VMERGE_VL", SDT_RISCVVMERGE_VL>;473 474def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>,475 SDTCisVT<1, XLenVT>]>;476 477// Set mask vector to all zeros or ones.478def riscv_vmclr_vl : RVSDNode<"VMCLR_VL", SDT_RISCVVMSETCLR_VL>;479def riscv_vmset_vl : RVSDNode<"VMSET_VL", SDT_RISCVVMSETCLR_VL>;480 481def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,482 SDTCisSameAs<0, 2>,483 SDTCVecEltisVT<0, i1>,484 SDTCisVT<3, XLenVT>]>;485 486// Mask binary operators.487def riscv_vmand_vl : RVSDNode<"VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;488def riscv_vmor_vl : RVSDNode<"VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;489def riscv_vmxor_vl : RVSDNode<"VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;490 491def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>;492 493def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl),494 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>;495 496let HasMaskOp = true in {497 // vcpop.m with additional mask and VL operands.498 def riscv_vcpop_vl : RVSDNode<"VCPOP_VL",499 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,500 SDTCisVec<1>, SDTCisInt<1>,501 SDTCVecEltisVT<2, i1>,502 SDTCisSameNumEltsAs<1, 2>,503 SDTCisVT<3, XLenVT>]>>;504 505 // vfirst.m with additional mask and VL operands.506 def riscv_vfirst_vl : RVSDNode<"VFIRST_VL",507 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,508 SDTCisVec<1>, SDTCisInt<1>,509 SDTCVecEltisVT<2, i1>,510 SDTCisSameNumEltsAs<1, 2>,511 SDTCisVT<3, XLenVT>]>>;512} // let HasMaskOp = true513 514def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>,515 SDTCisSameNumEltsAs<0, 1>,516 SDTCisSameNumEltsAs<1, 2>,517 SDTCVecEltisVT<2, i1>,518 SDTCisVT<3, XLenVT>]>;519 520let HasMaskOp = true in {521 // Vector sign/zero extend with additional mask & VL operands.522 def riscv_sext_vl : RVSDNode<"VSEXT_VL", SDT_RISCVVEXTEND_VL>;523 def riscv_zext_vl : RVSDNode<"VZEXT_VL", SDT_RISCVVEXTEND_VL>;524} // let HasMaskOp = true525 526def riscv_ext_vl : PatFrags<(ops node:$A, node:$B, node:$C),527 [(riscv_sext_vl node:$A, node:$B, node:$C),528 (riscv_zext_vl node:$A, node:$B, node:$C)]>;529 530def SDT_RISCVVTRUNCATE_VL : SDTypeProfile<1, 3, [SDTCisVec<0>,531 SDTCisSameNumEltsAs<0, 1>,532 SDTCisSameNumEltsAs<0, 2>,533 SDTCVecEltisVT<2, i1>,534 SDTCisVT<3, XLenVT>]>;535 536let HasMaskOp = true in {537 // Truncates a RVV integer vector by one power-of-two. Carries both an extra538 // mask and VL operand.539 def riscv_trunc_vector_vl : RVSDNode<"TRUNCATE_VECTOR_VL",540 SDT_RISCVVTRUNCATE_VL>;541 542 // Truncates a RVV integer vector by one power-of-two. If the value doesn't543 // fit in the destination type, the result is saturated. These correspond to544 // vnclip and vnclipu with a shift of 0. Carries both an extra mask and VL545 // operand.546 def riscv_trunc_vector_vl_ssat : RVSDNode<"TRUNCATE_VECTOR_VL_SSAT",547 SDT_RISCVVTRUNCATE_VL>;548 def riscv_trunc_vector_vl_usat : RVSDNode<"TRUNCATE_VECTOR_VL_USAT",549 SDT_RISCVVTRUNCATE_VL>;550} // let HasMaskOp = true551 552def SDT_RISCVVWIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,553 SDTCisInt<1>,554 SDTCisSameNumEltsAs<0, 1>,555 SDTCisOpSmallerThanOp<1, 0>,556 SDTCisSameAs<1, 2>,557 SDTCisSameAs<0, 3>,558 SDTCisSameNumEltsAs<1, 4>,559 SDTCVecEltisVT<4, i1>,560 SDTCisVT<5, XLenVT>]>;561 562let HasPassthruOp = true, HasMaskOp = true in {563 // Widening instructions with a passthru value a third operand, a mask as a564 // fourth operand, and VL as a fifth operand.565 def riscv_vwmul_vl : RVSDNode<"VWMUL_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>;566 def riscv_vwmulu_vl : RVSDNode<"VWMULU_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>;567 def riscv_vwmulsu_vl : RVSDNode<"VWMULSU_VL", SDT_RISCVVWIntBinOp_VL>;568 def riscv_vwadd_vl : RVSDNode<"VWADD_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>;569 def riscv_vwaddu_vl : RVSDNode<"VWADDU_VL", SDT_RISCVVWIntBinOp_VL, [SDNPCommutative]>;570 def riscv_vwsub_vl : RVSDNode<"VWSUB_VL", SDT_RISCVVWIntBinOp_VL, []>;571 def riscv_vwsubu_vl : RVSDNode<"VWSUBU_VL", SDT_RISCVVWIntBinOp_VL, []>;572 def riscv_vwsll_vl : RVSDNode<"VWSLL_VL", SDT_RISCVVWIntBinOp_VL, []>;573} // let HasPassthruOp = true, HasMaskOp = true574 575def SDT_RISCVVWIntTernOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,576 SDTCisInt<1>,577 SDTCisSameNumEltsAs<0, 1>,578 SDTCisOpSmallerThanOp<1, 0>,579 SDTCisSameAs<1, 2>,580 SDTCisSameAs<0, 3>,581 SDTCisSameNumEltsAs<1, 4>,582 SDTCVecEltisVT<4, i1>,583 SDTCisVT<5, XLenVT>]>;584 585let HasMaskOp = true in {586 // Widening ternary operations with a mask as the fourth operand and VL as the587 // fifth operand.588 def riscv_vwmacc_vl : RVSDNode<"VWMACC_VL", SDT_RISCVVWIntTernOp_VL, [SDNPCommutative]>;589 def riscv_vwmaccu_vl : RVSDNode<"VWMACCU_VL", SDT_RISCVVWIntTernOp_VL, [SDNPCommutative]>;590 def riscv_vwmaccsu_vl : RVSDNode<"VWMACCSU_VL", SDT_RISCVVWIntTernOp_VL, []>;591} // let HasMaskOp = true592 593def SDT_RISCVVWFPBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>,594 SDTCisFP<1>,595 SDTCisSameNumEltsAs<0, 1>,596 SDTCisOpSmallerThanOp<1, 0>,597 SDTCisSameAs<1, 2>,598 SDTCisSameAs<0, 3>,599 SDTCisSameNumEltsAs<1, 4>,600 SDTCVecEltisVT<4, i1>,601 SDTCisVT<5, XLenVT>]>;602 603let HasPassthruOp = true, HasMaskOp = true in {604 def riscv_vfwmul_vl : RVSDNode<"VFWMUL_VL", SDT_RISCVVWFPBinOp_VL, [SDNPCommutative]>;605 def riscv_vfwadd_vl : RVSDNode<"VFWADD_VL", SDT_RISCVVWFPBinOp_VL, [SDNPCommutative]>;606 def riscv_vfwsub_vl : RVSDNode<"VFWSUB_VL", SDT_RISCVVWFPBinOp_VL, []>;607} // let HasPassthruOp = true, HasMaskOp = true608 609def SDT_RISCVVWIntBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,610 SDTCisSameAs<0, 1>,611 SDTCisInt<2>,612 SDTCisSameNumEltsAs<1, 2>,613 SDTCisOpSmallerThanOp<2, 1>,614 SDTCisSameAs<0, 3>,615 SDTCisSameNumEltsAs<1, 4>,616 SDTCVecEltisVT<4, i1>,617 SDTCisVT<5, XLenVT>]>;618 619let HasPassthruOp = true, HasMaskOp = true in {620 def riscv_vwadd_w_vl : RVSDNode<"VWADD_W_VL", SDT_RISCVVWIntBinOpW_VL>;621 def riscv_vwaddu_w_vl : RVSDNode<"VWADDU_W_VL", SDT_RISCVVWIntBinOpW_VL>;622 def riscv_vwsub_w_vl : RVSDNode<"VWSUB_W_VL", SDT_RISCVVWIntBinOpW_VL>;623 def riscv_vwsubu_w_vl : RVSDNode<"VWSUBU_W_VL", SDT_RISCVVWIntBinOpW_VL>;624} // let HasPassthruOp = true, HasMaskOp = true625 626def SDT_RISCVVWFPBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>,627 SDTCisSameAs<0, 1>,628 SDTCisFP<2>,629 SDTCisSameNumEltsAs<1, 2>,630 SDTCisOpSmallerThanOp<2, 1>,631 SDTCisSameAs<0, 3>,632 SDTCisSameNumEltsAs<1, 4>,633 SDTCVecEltisVT<4, i1>,634 SDTCisVT<5, XLenVT>]>;635 636let HasPassthruOp = true, HasMaskOp = true in {637 def riscv_vfwadd_w_vl : RVSDNode<"VFWADD_W_VL", SDT_RISCVVWFPBinOpW_VL>;638 def riscv_vfwsub_w_vl : RVSDNode<"VFWSUB_W_VL", SDT_RISCVVWFPBinOpW_VL>;639} // let HasPassthruOp = true, HasMaskOp = true640 641def SDTRVVVecReduce : SDTypeProfile<1, 6, [642 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>,643 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT>,644 SDTCisVT<6, XLenVT>645]>;646 647let HasOneUse = 1 in {648 def riscv_add_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,649 node:$E),650 (riscv_add_vl node:$A, node:$B, node:$C,651 node:$D, node:$E)>;652 def riscv_or_vl_is_add_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,653 node:$E),654 (riscv_or_vl node:$A, node:$B, node:$C,655 node:$D, node:$E), [{656 return orDisjoint(N);657 }]>;658 def riscv_sub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,659 node:$E),660 (riscv_sub_vl node:$A, node:$B, node:$C,661 node:$D, node:$E)>;662 def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,663 node:$E),664 (riscv_mul_vl node:$A, node:$B, node:$C,665 node:$D, node:$E)>;666 def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,667 node:$E),668 (riscv_vwmul_vl node:$A, node:$B, node:$C,669 node:$D, node:$E)>;670 def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,671 node:$E),672 (riscv_vwmulu_vl node:$A, node:$B, node:$C,673 node:$D, node:$E)>;674 def riscv_vwmulsu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,675 node:$E),676 (riscv_vwmulsu_vl node:$A, node:$B, node:$C,677 node:$D, node:$E)>;678 def riscv_sext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C),679 (riscv_sext_vl node:$A, node:$B, node:$C)>;680 def riscv_zext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C),681 (riscv_zext_vl node:$A, node:$B, node:$C)>;682 def riscv_ext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C),683 (riscv_ext_vl node:$A, node:$B, node:$C)>;684 def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C),685 (riscv_fpextend_vl node:$A, node:$B, node:$C)>;686 def riscv_vfmadd_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,687 node:$E),688 (riscv_vfmadd_vl node:$A, node:$B,689 node:$C, node:$D, node:$E)>;690 def riscv_vfnmadd_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,691 node:$E),692 (riscv_vfnmadd_vl node:$A, node:$B,693 node:$C, node:$D, node:$E)>;694 def riscv_vfmsub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,695 node:$E),696 (riscv_vfmsub_vl node:$A, node:$B,697 node:$C, node:$D, node:$E)>;698 def riscv_vfnmsub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,699 node:$E),700 (riscv_vfnmsub_vl node:$A, node:$B,701 node:$C, node:$D, node:$E)>;702} // HasOneUse = 1703 704def riscv_fpextend_vl_sameuser : PatFrag<(ops node:$A, node:$B, node:$C),705 (riscv_fpextend_vl node:$A, node:$B, node:$C), [{706 return !N->use_empty() && all_equal(N->users());707}]>;708 709// These nodes match the semantics of the corresponding RVV vector reduction710// instructions. They produce a vector result which is the reduction711// performed over the second vector operand plus the first element of the712// third vector operand. The first operand is the pass-thru operand. The713// second operand is an unconstrained vector type, and the result, first, and714// third operand's types are expected to be the corresponding full-width715// LMUL=1 type for the second operand:716// nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8717// nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32718// The different in types does introduce extra vsetvli instructions but719// similarly it reduces the number of registers consumed per reduction.720// Also has a mask and VL operand.721let HasMaskOp = true in722foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR",723 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in724 def rvv_vecreduce_#kind#_vl : RVSDNode<"VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>;725 726// Give explicit Complexity to prefer simm5/uimm5.727def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;728def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 3>;729def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<5>", [], [], 3>;730def SplatPat_uimm6 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<6>", [], [], 3>;731def SplatPat_simm5_plus1732 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 3>;733def SplatPat_simm5_plus1_nodec734 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NoDec", [], [], 3>;735def SplatPat_simm5_plus1_nonzero736 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 3>;737def SplatPat_imm64_neg : ComplexPattern<vAny, 1, "selectVSplatImm64Neg", [], [], 3>;738 739// Selects extends or truncates of splats where we only care about the lowest 8740// bits of each element.741def Low8BitsSplatPat742 : ComplexPattern<vAny, 1, "selectLow8BitsVSplat", [], [], 2>;743 744// Ignore the vl operand on vmv_v_f, and vmv_s_f.745def SplatFPOp : PatFrags<(ops node:$op),746 [(riscv_vfmv_v_f_vl undef, node:$op, srcvalue),747 (riscv_vfmv_s_f_vl undef, node:$op, srcvalue)]>;748 749def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>;750def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;751def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>;752def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>;753 754class VPatBinaryVL_V<SDPatternOperator vop,755 string instruction_name,756 string suffix,757 ValueType result_type,758 ValueType op1_type,759 ValueType op2_type,760 ValueType mask_type,761 int log2sew,762 LMULInfo vlmul,763 VReg result_reg_class,764 VReg op1_reg_class,765 VReg op2_reg_class,766 bit isSEWAware = 0>767 : Pat<(result_type (vop768 (op1_type op1_reg_class:$rs1),769 (op2_type op2_reg_class:$rs2),770 (result_type result_reg_class:$passthru),771 (mask_type VMV0:$vm),772 VLOpFrag)),773 (!cast<Instruction>(774 !if(isSEWAware,775 instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",776 instruction_name#"_"#suffix#"_"#vlmul.MX#"_MASK"))777 result_reg_class:$passthru,778 op1_reg_class:$rs1,779 op2_reg_class:$rs2,780 (mask_type VMV0:$vm), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;781 782class VPatBinaryVL_V_RM<SDPatternOperator vop,783 string instruction_name,784 string suffix,785 ValueType result_type,786 ValueType op1_type,787 ValueType op2_type,788 ValueType mask_type,789 int log2sew,790 LMULInfo vlmul,791 VReg result_reg_class,792 VReg op1_reg_class,793 VReg op2_reg_class,794 bit isSEWAware = 0>795 : Pat<(result_type (vop796 (op1_type op1_reg_class:$rs1),797 (op2_type op2_reg_class:$rs2),798 (result_type result_reg_class:$passthru),799 (mask_type VMV0:$vm),800 VLOpFrag)),801 (!cast<Instruction>(802 !if(isSEWAware,803 instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",804 instruction_name#"_"#suffix#"_"#vlmul.MX#"_MASK"))805 result_reg_class:$passthru,806 op1_reg_class:$rs1,807 op2_reg_class:$rs2,808 (mask_type VMV0:$vm),809 // Value to indicate no rounding mode change in810 // RISCVInsertReadWriteCSR811 FRM_DYN,812 GPR:$vl, log2sew, TAIL_AGNOSTIC)>;813 814multiclass VPatTiedBinaryNoMaskVL_V<SDNode vop,815 string instruction_name,816 string suffix,817 ValueType result_type,818 ValueType op2_type,819 int sew,820 LMULInfo vlmul,821 VReg result_reg_class,822 VReg op2_reg_class> {823 def : Pat<(result_type (vop824 (result_type result_reg_class:$rs1),825 (op2_type op2_reg_class:$rs2),826 srcvalue,827 true_mask,828 VLOpFrag)),829 (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED")830 result_reg_class:$rs1,831 op2_reg_class:$rs2,832 GPR:$vl, sew, TAIL_AGNOSTIC)>;833}834 835class VPatTiedBinaryMaskVL_V<SDNode vop,836 string instruction_name,837 string suffix,838 ValueType result_type,839 ValueType op2_type,840 ValueType mask_type,841 int sew,842 LMULInfo vlmul,843 VReg result_reg_class,844 VReg op2_reg_class> :845 Pat<(result_type (vop846 (result_type result_reg_class:$rs1),847 (op2_type op2_reg_class:$rs2),848 (result_type result_reg_class:$rs1),849 (mask_type VMV0:$vm),850 VLOpFrag)),851 (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_MASK_TIED")852 result_reg_class:$rs1,853 op2_reg_class:$rs2,854 (mask_type VMV0:$vm), GPR:$vl, sew, TU_MU)>;855 856multiclass VPatTiedBinaryNoMaskVL_V_RM<SDNode vop,857 string instruction_name,858 string suffix,859 ValueType result_type,860 ValueType op2_type,861 int log2sew,862 LMULInfo vlmul,863 VReg result_reg_class,864 VReg op2_reg_class,865 bit isSEWAware = 0> {866 defvar name = !if(isSEWAware,867 instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_TIED",868 instruction_name#"_"#suffix#"_"#vlmul.MX#"_TIED");869 def : Pat<(result_type (vop870 (result_type result_reg_class:$rs1),871 (op2_type op2_reg_class:$rs2),872 srcvalue,873 true_mask,874 VLOpFrag)),875 (!cast<Instruction>(name)876 result_reg_class:$rs1,877 op2_reg_class:$rs2,878 // Value to indicate no rounding mode change in879 // RISCVInsertReadWriteCSR880 FRM_DYN,881 GPR:$vl, log2sew, TAIL_AGNOSTIC)>;882}883 884class VPatBinaryVL_XI<SDPatternOperator vop,885 string instruction_name,886 string suffix,887 ValueType result_type,888 ValueType vop1_type,889 ValueType vop2_type,890 ValueType mask_type,891 int log2sew,892 LMULInfo vlmul,893 VReg result_reg_class,894 VReg vop_reg_class,895 ComplexPattern SplatPatKind,896 DAGOperand xop_kind,897 bit isSEWAware = 0>898 : Pat<(result_type (vop899 (vop1_type vop_reg_class:$rs1),900 (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))),901 (result_type result_reg_class:$passthru),902 (mask_type VMV0:$vm),903 VLOpFrag)),904 (!cast<Instruction>(905 !if(isSEWAware,906 instruction_name#_#suffix#_#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",907 instruction_name#_#suffix#_#vlmul.MX#"_MASK"))908 result_reg_class:$passthru,909 vop_reg_class:$rs1,910 xop_kind:$rs2,911 (mask_type VMV0:$vm), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;912 913multiclass VPatBinaryVL_VV_VX<SDPatternOperator vop, string instruction_name,914 list<VTypeInfo> vtilist = AllIntegerVectors,915 bit isSEWAware = 0> {916 foreach vti = vtilist in {917 let Predicates = GetVTypePredicates<vti>.Predicates in {918 def : VPatBinaryVL_V<vop, instruction_name, "VV",919 vti.Vector, vti.Vector, vti.Vector, vti.Mask,920 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,921 vti.RegClass, isSEWAware>;922 def : VPatBinaryVL_XI<vop, instruction_name, "VX",923 vti.Vector, vti.Vector, vti.Vector, vti.Mask,924 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,925 SplatPat, GPR, isSEWAware>;926 }927 }928}929 930multiclass VPatBinaryVL_VV_VX_VI<SDPatternOperator vop, string instruction_name,931 Operand ImmType = simm5>932 : VPatBinaryVL_VV_VX<vop, instruction_name> {933 foreach vti = AllIntegerVectors in {934 let Predicates = GetVTypePredicates<vti>.Predicates in935 def : VPatBinaryVL_XI<vop, instruction_name, "VI",936 vti.Vector, vti.Vector, vti.Vector, vti.Mask,937 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,938 !cast<ComplexPattern>(SplatPat#_#ImmType),939 ImmType>;940 }941}942 943multiclass VPatBinaryWVL_VV_VX<SDPatternOperator vop, string instruction_name> {944 foreach VtiToWti = AllWidenableIntVectors in {945 defvar vti = VtiToWti.Vti;946 defvar wti = VtiToWti.Wti;947 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,948 GetVTypePredicates<wti>.Predicates) in {949 def : VPatBinaryVL_V<vop, instruction_name, "VV",950 wti.Vector, vti.Vector, vti.Vector, vti.Mask,951 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,952 vti.RegClass>;953 def : VPatBinaryVL_XI<vop, instruction_name, "VX",954 wti.Vector, vti.Vector, vti.Vector, vti.Mask,955 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,956 SplatPat, GPR>;957 }958 }959}960 961multiclass VPatBinaryWVL_VV_VX_WV_WX<SDPatternOperator vop, SDNode vop_w,962 string instruction_name>963 : VPatBinaryWVL_VV_VX<vop, instruction_name> {964 foreach VtiToWti = AllWidenableIntVectors in {965 defvar vti = VtiToWti.Vti;966 defvar wti = VtiToWti.Wti;967 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,968 GetVTypePredicates<wti>.Predicates) in {969 defm : VPatTiedBinaryNoMaskVL_V<vop_w, instruction_name, "WV",970 wti.Vector, vti.Vector, vti.Log2SEW,971 vti.LMul, wti.RegClass, vti.RegClass>;972 def : VPatTiedBinaryMaskVL_V<vop_w, instruction_name, "WV",973 wti.Vector, vti.Vector, wti.Mask,974 vti.Log2SEW, vti.LMul, wti.RegClass,975 vti.RegClass>;976 def : VPatBinaryVL_V<vop_w, instruction_name, "WV",977 wti.Vector, wti.Vector, vti.Vector, vti.Mask,978 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,979 vti.RegClass>;980 def : VPatBinaryVL_XI<vop_w, instruction_name, "WX",981 wti.Vector, wti.Vector, vti.Vector, vti.Mask,982 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,983 SplatPat, GPR>;984 }985 }986}987 988class VPatBinaryVL_VF<SDPatternOperator vop,989 string instruction_name,990 ValueType result_type,991 ValueType vop1_type,992 ValueType vop2_type,993 ValueType mask_type,994 int log2sew,995 LMULInfo vlmul,996 VReg result_reg_class,997 VReg vop_reg_class,998 RegisterClass scalar_reg_class,999 bit isSEWAware = 0>1000 : Pat<(result_type (vop (vop1_type vop_reg_class:$rs1),1001 (vop2_type (SplatFPOp scalar_reg_class:$rs2)),1002 (result_type result_reg_class:$passthru),1003 (mask_type VMV0:$vm),1004 VLOpFrag)),1005 (!cast<Instruction>(1006 !if(isSEWAware,1007 instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",1008 instruction_name#"_"#vlmul.MX#"_MASK"))1009 result_reg_class:$passthru,1010 vop_reg_class:$rs1,1011 scalar_reg_class:$rs2,1012 (mask_type VMV0:$vm), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;1013 1014class VPatBinaryVL_VF_RM<SDPatternOperator vop,1015 string instruction_name,1016 ValueType result_type,1017 ValueType vop1_type,1018 ValueType vop2_type,1019 ValueType mask_type,1020 int log2sew,1021 LMULInfo vlmul,1022 VReg result_reg_class,1023 VReg vop_reg_class,1024 RegisterClass scalar_reg_class,1025 bit isSEWAware = 0>1026 : Pat<(result_type (vop (vop1_type vop_reg_class:$rs1),1027 (vop2_type (SplatFPOp scalar_reg_class:$rs2)),1028 (result_type result_reg_class:$passthru),1029 (mask_type VMV0:$vm),1030 VLOpFrag)),1031 (!cast<Instruction>(1032 !if(isSEWAware,1033 instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",1034 instruction_name#"_"#vlmul.MX#"_MASK"))1035 result_reg_class:$passthru,1036 vop_reg_class:$rs1,1037 scalar_reg_class:$rs2,1038 (mask_type VMV0:$vm),1039 // Value to indicate no rounding mode change in1040 // RISCVInsertReadWriteCSR1041 FRM_DYN,1042 GPR:$vl, log2sew, TAIL_AGNOSTIC)>;1043 1044multiclass VPatBinaryFPVL_VV_VF<SDPatternOperator vop, string instruction_name,1045 bit isSEWAware = 0> {1046 foreach vti = AllFloatVectors in {1047 let Predicates = GetVTypePredicates<vti>.Predicates in {1048 def : VPatBinaryVL_V<vop, instruction_name, "VV",1049 vti.Vector, vti.Vector, vti.Vector, vti.Mask,1050 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,1051 vti.RegClass, isSEWAware>;1052 def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,1053 vti.Vector, vti.Vector, vti.Vector, vti.Mask,1054 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,1055 vti.ScalarRegClass, isSEWAware>;1056 }1057 }1058}1059 1060multiclass VPatBinaryFPVL_VV_VF_RM<SDPatternOperator vop, string instruction_name,1061 bit isSEWAware = 0> {1062 foreach vti = AllFloatVectors in {1063 let Predicates = GetVTypePredicates<vti>.Predicates in {1064 def : VPatBinaryVL_V_RM<vop, instruction_name, "VV",1065 vti.Vector, vti.Vector, vti.Vector, vti.Mask,1066 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,1067 vti.RegClass, isSEWAware>;1068 def : VPatBinaryVL_VF_RM<vop, instruction_name#"_V"#vti.ScalarSuffix,1069 vti.Vector, vti.Vector, vti.Vector, vti.Mask,1070 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,1071 vti.ScalarRegClass, isSEWAware>;1072 }1073 }1074}1075 1076multiclass VPatBinaryFPVL_R_VF<SDPatternOperator vop, string instruction_name,1077 bit isSEWAware = 0> {1078 foreach fvti = AllFloatVectors in {1079 let Predicates = GetVTypePredicates<fvti>.Predicates in1080 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),1081 fvti.RegClass:$rs1,1082 (fvti.Vector fvti.RegClass:$passthru),1083 (fvti.Mask VMV0:$vm),1084 VLOpFrag)),1085 (!cast<Instruction>(1086 !if(isSEWAware,1087 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK",1088 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK"))1089 fvti.RegClass:$passthru,1090 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,1091 (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;1092 }1093}1094 1095multiclass VPatBinaryFPVL_R_VF_RM<SDPatternOperator vop, string instruction_name,1096 bit isSEWAware = 0> {1097 foreach fvti = AllFloatVectors in {1098 let Predicates = GetVTypePredicates<fvti>.Predicates in1099 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),1100 fvti.RegClass:$rs1,1101 (fvti.Vector fvti.RegClass:$passthru),1102 (fvti.Mask VMV0:$vm),1103 VLOpFrag)),1104 (!cast<Instruction>(1105 !if(isSEWAware,1106 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK",1107 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK"))1108 fvti.RegClass:$passthru,1109 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,1110 (fvti.Mask VMV0:$vm),1111 // Value to indicate no rounding mode change in1112 // RISCVInsertReadWriteCSR1113 FRM_DYN,1114 GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;1115 }1116}1117 1118multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,1119 CondCode cc> {1120 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),1121 vti.RegClass:$rs2, cc,1122 VR:$passthru,1123 (vti.Mask VMV0:$vm),1124 VLOpFrag)),1125 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")1126 VR:$passthru,1127 vti.RegClass:$rs1,1128 vti.RegClass:$rs2,1129 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MU)>;1130}1131 1132// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.1133multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name,1134 CondCode cc, CondCode invcc>1135 : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {1136 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),1137 vti.RegClass:$rs1, invcc,1138 VR:$passthru,1139 (vti.Mask VMV0:$vm),1140 VLOpFrag)),1141 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")1142 VR:$passthru, vti.RegClass:$rs1,1143 vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,1144 vti.Log2SEW, TA_MU)>;1145}1146 1147multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name,1148 CondCode cc, CondCode invcc> {1149 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK");1150 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),1151 (SplatPat (XLenVT GPR:$rs2)), cc,1152 VR:$passthru,1153 (vti.Mask VMV0:$vm),1154 VLOpFrag)),1155 (instruction_masked VR:$passthru, vti.RegClass:$rs1,1156 GPR:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,1157 vti.Log2SEW, TA_MU)>;1158 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)),1159 (vti.Vector vti.RegClass:$rs1), invcc,1160 VR:$passthru,1161 (vti.Mask VMV0:$vm),1162 VLOpFrag)),1163 (instruction_masked VR:$passthru, vti.RegClass:$rs1,1164 GPR:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,1165 vti.Log2SEW, TA_MU)>;1166}1167 1168multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,1169 CondCode cc, CondCode invcc,1170 ComplexPattern splatpat_kind = SplatPat_simm5> {1171 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");1172 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),1173 (splatpat_kind simm5:$rs2), cc,1174 VR:$passthru,1175 (vti.Mask VMV0:$vm),1176 VLOpFrag)),1177 (instruction_masked VR:$passthru, vti.RegClass:$rs1,1178 XLenVT:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,1179 vti.Log2SEW, TA_MU)>;1180 1181 // FIXME: Can do some canonicalization to remove these patterns.1182 def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2),1183 (vti.Vector vti.RegClass:$rs1), invcc,1184 VR:$passthru,1185 (vti.Mask VMV0:$vm),1186 VLOpFrag)),1187 (instruction_masked VR:$passthru, vti.RegClass:$rs1,1188 simm5:$rs2, (vti.Mask VMV0:$vm), GPR:$vl,1189 vti.Log2SEW, TA_MU)>;1190}1191 1192multiclass VPatFPSetCCVL_VV_VF_FV<SDPatternOperator vop, CondCode cc,1193 string inst_name,1194 string swapped_op_inst_name> {1195 foreach fvti = AllFloatVectors in {1196 let Predicates = GetVTypePredicates<fvti>.Predicates in {1197 def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1),1198 fvti.RegClass:$rs2,1199 cc,1200 VR:$passthru,1201 (fvti.Mask VMV0:$vm),1202 VLOpFrag)),1203 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX#"_MASK")1204 VR:$passthru, fvti.RegClass:$rs1,1205 fvti.RegClass:$rs2, (fvti.Mask VMV0:$vm),1206 GPR:$vl, fvti.Log2SEW, TA_MU)>;1207 def : Pat<(fvti.Mask (vop (fvti.Vector fvti.RegClass:$rs1),1208 (SplatFPOp fvti.ScalarRegClass:$rs2),1209 cc,1210 VR:$passthru,1211 (fvti.Mask VMV0:$vm),1212 VLOpFrag)),1213 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")1214 VR:$passthru, fvti.RegClass:$rs1,1215 fvti.ScalarRegClass:$rs2, (fvti.Mask VMV0:$vm),1216 GPR:$vl, fvti.Log2SEW, TA_MU)>;1217 def : Pat<(fvti.Mask (vop (SplatFPOp fvti.ScalarRegClass:$rs2),1218 (fvti.Vector fvti.RegClass:$rs1),1219 cc,1220 VR:$passthru,1221 (fvti.Mask VMV0:$vm),1222 VLOpFrag)),1223 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK")1224 VR:$passthru, fvti.RegClass:$rs1,1225 fvti.ScalarRegClass:$rs2, (fvti.Mask VMV0:$vm),1226 GPR:$vl, fvti.Log2SEW, TA_MU)>;1227 }1228 }1229}1230 1231multiclass VPatExtendVL_V<SDNode vop, string inst_name, string suffix,1232 list <VTypeInfoToFraction> fraction_list> {1233 foreach vtiTofti = fraction_list in {1234 defvar vti = vtiTofti.Vti;1235 defvar fti = vtiTofti.Fti;1236 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1237 GetVTypePredicates<fti>.Predicates) in1238 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2),1239 (fti.Mask VMV0:$vm), VLOpFrag)),1240 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK")1241 (vti.Vector (IMPLICIT_DEF)),1242 fti.RegClass:$rs2,1243 (fti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;1244 }1245}1246 1247// Single width converting1248 1249multiclass VPatConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {1250 foreach fvti = AllFloatVectors in {1251 defvar ivti = GetIntVTypeInfo<fvti>.Vti;1252 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1253 GetVTypePredicates<ivti>.Predicates) in1254 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),1255 (fvti.Mask VMV0:$vm),1256 VLOpFrag)),1257 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")1258 (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,1259 (fvti.Mask VMV0:$vm), GPR:$vl, ivti.Log2SEW, TA_MA)>;1260 }1261}1262 1263 1264multiclass VPatConvertFP2I_RM_VL_V<SDPatternOperator vop, string instruction_name> {1265 foreach fvti = AllFloatVectors in {1266 defvar ivti = GetIntVTypeInfo<fvti>.Vti;1267 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1268 GetVTypePredicates<ivti>.Predicates) in1269 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),1270 (fvti.Mask VMV0:$vm), (XLenVT timm:$frm),1271 VLOpFrag)),1272 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")1273 (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,1274 (fvti.Mask VMV0:$vm), timm:$frm, GPR:$vl, ivti.Log2SEW,1275 TA_MA)>;1276 }1277}1278 1279multiclass VPatConvertI2FPVL_V_RM<SDPatternOperator vop, string instruction_name> {1280 foreach fvti = AllFloatVectors in {1281 defvar ivti = GetIntVTypeInfo<fvti>.Vti;1282 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1283 GetVTypePredicates<ivti>.Predicates) in1284 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),1285 (ivti.Mask VMV0:$vm),1286 VLOpFrag)),1287 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")1288 (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,1289 (ivti.Mask VMV0:$vm),1290 // Value to indicate no rounding mode change in1291 // RISCVInsertReadWriteCSR1292 FRM_DYN,1293 GPR:$vl, fvti.Log2SEW, TA_MA)>;1294 }1295}1296 1297multiclass VPatConvertI2FP_RM_VL_V<SDNode vop, string instruction_name> {1298 foreach fvti = AllFloatVectors in {1299 defvar ivti = GetIntVTypeInfo<fvti>.Vti;1300 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1301 GetVTypePredicates<ivti>.Predicates) in1302 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),1303 (ivti.Mask VMV0:$vm), (XLenVT timm:$frm),1304 VLOpFrag)),1305 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")1306 (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,1307 (ivti.Mask VMV0:$vm), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;1308 }1309}1310 1311// Widening converting1312 1313multiclass VPatWConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {1314 foreach fvtiToFWti = AllWidenableFloatVectors in {1315 defvar fvti = fvtiToFWti.Vti;1316 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;1317 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1318 GetVTypePredicates<iwti>.Predicates) in1319 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),1320 (fvti.Mask VMV0:$vm),1321 VLOpFrag)),1322 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")1323 (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,1324 (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TA_MA)>;1325 }1326}1327 1328 1329multiclass VPatWConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {1330 foreach fvtiToFWti = AllWidenableFloatVectors in {1331 defvar fvti = fvtiToFWti.Vti;1332 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;1333 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1334 GetVTypePredicates<iwti>.Predicates) in1335 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),1336 (fvti.Mask VMV0:$vm), (XLenVT timm:$frm),1337 VLOpFrag)),1338 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")1339 (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,1340 (fvti.Mask VMV0:$vm), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;1341 }1342}1343 1344multiclass VPatWConvertI2FPVL_V<SDPatternOperator vop,1345 string instruction_name> {1346 foreach vtiToWti = AllWidenableIntToFloatVectors in {1347 defvar ivti = vtiToWti.Vti;1348 defvar fwti = vtiToWti.Wti;1349 let Predicates = !listconcat(GetVTypePredicates<ivti>.Predicates,1350 GetVTypePredicates<fwti>.Predicates) in1351 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),1352 (ivti.Mask VMV0:$vm),1353 VLOpFrag)),1354 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_E"#ivti.SEW#"_MASK")1355 (fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,1356 (ivti.Mask VMV0:$vm),1357 GPR:$vl, ivti.Log2SEW, TA_MA)>;1358 }1359}1360 1361// Narrowing converting1362 1363multiclass VPatNConvertFP2IVL_W<SDPatternOperator vop,1364 string instruction_name> {1365 // Reuse the same list of types used in the widening nodes, but just swap the1366 // direction of types around so we're converting from Wti -> Vti1367 foreach vtiToWti = AllWidenableIntToFloatVectors in {1368 defvar vti = vtiToWti.Vti;1369 defvar fwti = vtiToWti.Wti;1370 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1371 GetVTypePredicates<fwti>.Predicates) in1372 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),1373 (fwti.Mask VMV0:$vm),1374 VLOpFrag)),1375 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK")1376 (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,1377 (fwti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;1378 }1379}1380 1381multiclass VPatNConvertFP2I_RM_VL_W<SDNode vop, string instruction_name> {1382 foreach vtiToWti = AllWidenableIntToFloatVectors in {1383 defvar vti = vtiToWti.Vti;1384 defvar fwti = vtiToWti.Wti;1385 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1386 GetVTypePredicates<fwti>.Predicates) in1387 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),1388 (fwti.Mask VMV0:$vm), (XLenVT timm:$frm),1389 VLOpFrag)),1390 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK")1391 (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,1392 (fwti.Mask VMV0:$vm), timm:$frm, GPR:$vl, vti.Log2SEW, TA_MA)>;1393 }1394}1395 1396multiclass VPatNConvertI2FPVL_W_RM<SDPatternOperator vop,1397 string instruction_name> {1398 foreach fvtiToFWti = AllWidenableFloatVectors in {1399 defvar fvti = fvtiToFWti.Vti;1400 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;1401 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1402 GetVTypePredicates<iwti>.Predicates) in1403 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),1404 (iwti.Mask VMV0:$vm),1405 VLOpFrag)),1406 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK") 1407 (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,1408 (iwti.Mask VMV0:$vm),1409 // Value to indicate no rounding mode change in1410 // RISCVInsertReadWriteCSR1411 FRM_DYN,1412 GPR:$vl, fvti.Log2SEW, TA_MA)>;1413 }1414}1415 1416multiclass VPatNConvertI2FP_RM_VL_W<SDNode vop, string instruction_name> {1417 foreach fvtiToFWti = AllWidenableFloatVectors in {1418 defvar fvti = fvtiToFWti.Vti;1419 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;1420 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,1421 GetVTypePredicates<iwti>.Predicates) in1422 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),1423 (iwti.Mask VMV0:$vm), (XLenVT timm:$frm),1424 VLOpFrag)),1425 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")1426 (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1,1427 (iwti.Mask VMV0:$vm), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;1428 }1429}1430 1431multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> {1432 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in {1433 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1");1434 let Predicates = GetVTypePredicates<vti>.Predicates in {1435 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$passthru),1436 (vti.Vector vti.RegClass:$rs1), VR:$rs2,1437 (vti.Mask VMV0:$vm), VLOpFrag,1438 (XLenVT timm:$policy))),1439 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")1440 (vti_m1.Vector VR:$passthru),1441 (vti.Vector vti.RegClass:$rs1),1442 (vti_m1.Vector VR:$rs2),1443 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;1444 }1445 }1446}1447 1448multiclass VPatReductionVL_RM<SDNode vop, string instruction_name, bit is_float> {1449 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in {1450 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1");1451 let Predicates = GetVTypePredicates<vti>.Predicates in {1452 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$passthru),1453 (vti.Vector vti.RegClass:$rs1), VR:$rs2,1454 (vti.Mask VMV0:$vm), VLOpFrag,1455 (XLenVT timm:$policy))),1456 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")1457 (vti_m1.Vector VR:$passthru),1458 (vti.Vector vti.RegClass:$rs1),1459 (vti_m1.Vector VR:$rs2),1460 (vti.Mask VMV0:$vm),1461 // Value to indicate no rounding mode change in1462 // RISCVInsertReadWriteCSR1463 FRM_DYN,1464 GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;1465 }1466 }1467}1468 1469multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> {1470 foreach vtiToWti = AllWidenableIntVectors in {1471 defvar vti = vtiToWti.Vti;1472 defvar wti = vtiToWti.Wti;1473 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1474 GetVTypePredicates<wti>.Predicates) in {1475 def : Pat<1476 (vti.Vector1477 (riscv_trunc_vector_vl1478 (op (wti.Vector wti.RegClass:$rs2),1479 (wti.Vector (ext_oneuse (vti.Vector vti.RegClass:$rs1)))),1480 (vti.Mask true_mask),1481 VLOpFrag)),1482 (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)1483 (vti.Vector (IMPLICIT_DEF)),1484 wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;1485 1486 def : Pat<1487 (vti.Vector1488 (riscv_trunc_vector_vl1489 (op (wti.Vector wti.RegClass:$rs2),1490 (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1)))),1491 (vti.Mask true_mask),1492 VLOpFrag)),1493 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)1494 (vti.Vector (IMPLICIT_DEF)),1495 wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;1496 1497 def : Pat<1498 (vti.Vector1499 (riscv_trunc_vector_vl1500 (op (wti.Vector wti.RegClass:$rs2),1501 (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask),1502 VLOpFrag)),1503 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)1504 (vti.Vector (IMPLICIT_DEF)),1505 wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;1506 }1507 }1508}1509 1510multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {1511 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {1512 defvar vti = vtiToWti.Vti;1513 defvar wti = vtiToWti.Wti;1514 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");1515 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1516 GetVTypePredicates<wti>.Predicates) in {1517 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$passthru),1518 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),1519 VR:$rs2, (vti.Mask VMV0:$vm), VLOpFrag,1520 (XLenVT timm:$policy))),1521 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")1522 (wti_m1.Vector VR:$passthru), (vti.Vector vti.RegClass:$rs1),1523 (wti_m1.Vector VR:$rs2), (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,1524 (XLenVT timm:$policy))>;1525 }1526 }1527}1528 1529multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {1530 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {1531 defvar vti = vtiToWti.Vti;1532 defvar wti = vtiToWti.Wti;1533 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");1534 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1535 GetVTypePredicates<wti>.Predicates) in {1536 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$passthru),1537 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), (XLenVT srcvalue))),1538 VR:$rs2, (vti.Mask VMV0:$vm), VLOpFrag,1539 (XLenVT timm:$policy))),1540 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")1541 (wti_m1.Vector VR:$passthru), (vti.Vector vti.RegClass:$rs1),1542 (wti_m1.Vector VR:$rs2), (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,1543 (XLenVT timm:$policy))>;1544 }1545 }1546}1547 1548multiclass VPatWidenReductionVL_Ext_VL_RM<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {1549 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {1550 defvar vti = vtiToWti.Vti;1551 defvar wti = vtiToWti.Wti;1552 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");1553 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1554 GetVTypePredicates<wti>.Predicates) in {1555 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$passthru),1556 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), (XLenVT srcvalue))),1557 VR:$rs2, (vti.Mask VMV0:$vm), VLOpFrag,1558 (XLenVT timm:$policy))),1559 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")1560 (wti_m1.Vector VR:$passthru), (vti.Vector vti.RegClass:$rs1),1561 (wti_m1.Vector VR:$rs2), (vti.Mask VMV0:$vm),1562 // Value to indicate no rounding mode change in1563 // RISCVInsertReadWriteCSR1564 FRM_DYN,1565 GPR:$vl, vti.Log2SEW,1566 (XLenVT timm:$policy))>;1567 }1568 }1569}1570 1571multiclass VPatBinaryFPWVL_VV_VF<SDNode vop, string instruction_name> {1572 foreach fvtiToFWti = AllWidenableFloatVectors in {1573 defvar vti = fvtiToFWti.Vti;1574 defvar wti = fvtiToFWti.Wti;1575 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1576 GetVTypePredicates<wti>.Predicates) in {1577 def : VPatBinaryVL_V<vop, instruction_name, "VV",1578 wti.Vector, vti.Vector, vti.Vector, vti.Mask,1579 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,1580 vti.RegClass>;1581 def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,1582 wti.Vector, vti.Vector, vti.Vector, vti.Mask,1583 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,1584 vti.ScalarRegClass>;1585 }1586 }1587}1588 1589multiclass VPatBinaryFPWVL_VV_VF_RM<SDNode vop, string instruction_name,1590 bit isSEWAware = 0> {1591 foreach fvtiToFWti = AllWidenableFloatVectors in {1592 defvar vti = fvtiToFWti.Vti;1593 defvar wti = fvtiToFWti.Wti;1594 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1595 GetVTypePredicates<wti>.Predicates) in {1596 def : VPatBinaryVL_V_RM<vop, instruction_name, "VV",1597 wti.Vector, vti.Vector, vti.Vector, vti.Mask,1598 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,1599 vti.RegClass, isSEWAware>;1600 def : VPatBinaryVL_VF_RM<vop, instruction_name#"_V"#vti.ScalarSuffix,1601 wti.Vector, vti.Vector, vti.Vector, vti.Mask,1602 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,1603 vti.ScalarRegClass, isSEWAware>;1604 }1605 }1606}1607 1608multiclass VPatBinaryFPWVL_VV_VF_WV_WF<SDNode vop, SDNode vop_w, string instruction_name>1609 : VPatBinaryFPWVL_VV_VF<vop, instruction_name> {1610 foreach fvtiToFWti = AllWidenableFloatVectors in {1611 defvar vti = fvtiToFWti.Vti;1612 defvar wti = fvtiToFWti.Wti;1613 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1614 GetVTypePredicates<wti>.Predicates) in {1615 defm : VPatTiedBinaryNoMaskVL_V<vop_w, instruction_name, "WV",1616 wti.Vector, vti.Vector, vti.Log2SEW,1617 vti.LMul, wti.RegClass, vti.RegClass>;1618 def : VPatBinaryVL_V<vop_w, instruction_name, "WV",1619 wti.Vector, wti.Vector, vti.Vector, vti.Mask,1620 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,1621 vti.RegClass>;1622 def : VPatBinaryVL_VF<vop_w, instruction_name#"_W"#vti.ScalarSuffix,1623 wti.Vector, wti.Vector, vti.Vector, vti.Mask,1624 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,1625 vti.ScalarRegClass>;1626 }1627 }1628}1629 1630multiclass VPatBinaryFPWVL_VV_VF_WV_WF_RM<1631 SDNode vop, SDNode vop_w, string instruction_name, bit isSEWAware = 0>1632 : VPatBinaryFPWVL_VV_VF_RM<vop, instruction_name, isSEWAware> {1633 foreach fvtiToFWti = AllWidenableFloatVectors in {1634 defvar vti = fvtiToFWti.Vti;1635 defvar wti = fvtiToFWti.Wti;1636 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1637 GetVTypePredicates<wti>.Predicates) in {1638 defm : VPatTiedBinaryNoMaskVL_V_RM<vop_w, instruction_name, "WV",1639 wti.Vector, vti.Vector, vti.Log2SEW,1640 vti.LMul, wti.RegClass, vti.RegClass,1641 isSEWAware>;1642 def : VPatBinaryVL_V_RM<vop_w, instruction_name, "WV",1643 wti.Vector, wti.Vector, vti.Vector, vti.Mask,1644 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,1645 vti.RegClass, isSEWAware>;1646 def : VPatBinaryVL_VF_RM<vop_w, instruction_name#"_W"#vti.ScalarSuffix,1647 wti.Vector, wti.Vector, vti.Vector, vti.Mask,1648 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,1649 vti.ScalarRegClass, isSEWAware>;1650 }1651 }1652}1653 1654multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> {1655 foreach vtiToWti = AllWidenableIntVectors in {1656 defvar vti = vtiToWti.Vti;1657 defvar wti = vtiToWti.Wti;1658 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1659 GetVTypePredicates<wti>.Predicates) in1660 def : Pat<1661 (vti.Vector1662 (riscv_trunc_vector_vl1663 (op (wti.Vector wti.RegClass:$rs2),1664 (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1))),1665 (vti.Mask true_mask), VLOpFrag)),1666 srcvalue, (wti.Mask true_mask), VLOpFrag),1667 (vti.Mask true_mask), VLOpFrag)),1668 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)1669 (vti.Vector (IMPLICIT_DEF)),1670 wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;1671 }1672}1673 1674multiclass VPatNarrowShiftExtVL_WV<SDNode op, PatFrags extop, string instruction_name> {1675 foreach vtiToWti = AllWidenableIntVectors in {1676 defvar vti = vtiToWti.Vti;1677 defvar wti = vtiToWti.Wti;1678 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1679 GetVTypePredicates<wti>.Predicates) in1680 def : Pat<1681 (vti.Vector1682 (riscv_trunc_vector_vl1683 (op (wti.Vector wti.RegClass:$rs2),1684 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1),1685 (vti.Mask true_mask), VLOpFrag)),1686 srcvalue, (vti.Mask true_mask), VLOpFrag),1687 (vti.Mask VMV0:$vm), VLOpFrag)),1688 (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_MASK")1689 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2, vti.RegClass:$rs1,1690 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;1691 }1692}1693 1694multiclass VPatNarrowShiftVL_WV<SDNode op, string instruction_name> {1695 defm : VPatNarrowShiftExtVL_WV<op, riscv_sext_vl_oneuse, instruction_name>;1696 defm : VPatNarrowShiftExtVL_WV<op, riscv_zext_vl_oneuse, instruction_name>;1697}1698 1699multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> {1700 foreach vti = AllIntegerVectors in {1701 defvar suffix = vti.LMul.MX;1702 let Predicates = GetVTypePredicates<vti>.Predicates in {1703 // NOTE: We choose VMADD because it has the most commuting freedom. So it1704 // works best with how TwoAddressInstructionPass tries commuting.1705 def : Pat<(vti.Vector1706 (op vti.RegClass:$rs2,1707 (riscv_mul_vl_oneuse vti.RegClass:$rs1,1708 vti.RegClass:$rd,1709 srcvalue, (vti.Mask true_mask), VLOpFrag),1710 srcvalue, (vti.Mask true_mask), VLOpFrag)),1711 (!cast<Instruction>(instruction_name#"_VV_"# suffix)1712 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,1713 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1714 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally1715 // commutable.1716 def : Pat<(vti.Vector1717 (op vti.RegClass:$rs2,1718 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1),1719 vti.RegClass:$rd,1720 srcvalue, (vti.Mask true_mask), VLOpFrag),1721 srcvalue, (vti.Mask true_mask), VLOpFrag)),1722 (!cast<Instruction>(instruction_name#"_VX_" # suffix)1723 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,1724 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1725 }1726 }1727}1728 1729multiclass VPatWidenMultiplyAddVL_VV_VX<SDNode vwmacc_op, string instr_name> {1730 foreach vtiTowti = AllWidenableIntVectors in {1731 defvar vti = vtiTowti.Vti;1732 defvar wti = vtiTowti.Wti;1733 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1734 GetVTypePredicates<wti>.Predicates) in {1735 def : Pat<(vwmacc_op (vti.Vector vti.RegClass:$rs1),1736 (vti.Vector vti.RegClass:$rs2),1737 (wti.Vector wti.RegClass:$rd),1738 (vti.Mask VMV0:$vm), VLOpFrag),1739 (!cast<Instruction>(instr_name#"_VV_"#vti.LMul.MX#"_MASK")1740 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,1741 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1742 def : Pat<(vwmacc_op (SplatPat XLenVT:$rs1),1743 (vti.Vector vti.RegClass:$rs2),1744 (wti.Vector wti.RegClass:$rd),1745 (vti.Mask VMV0:$vm), VLOpFrag),1746 (!cast<Instruction>(instr_name#"_VX_"#vti.LMul.MX#"_MASK")1747 wti.RegClass:$rd, vti.ScalarRegClass:$rs1,1748 vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,1749 TAIL_AGNOSTIC)>;1750 }1751 }1752}1753 1754multiclass VPatNarrowShiftSplat_WX_WI<SDNode op, string instruction_name> {1755 foreach vtiTowti = AllWidenableIntVectors in {1756 defvar vti = vtiTowti.Vti;1757 defvar wti = vtiTowti.Wti;1758 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1759 GetVTypePredicates<wti>.Predicates) in {1760 def : Pat<(vti.Vector (riscv_trunc_vector_vl1761 (wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2),1762 srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)),1763 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)1764 (vti.Vector (IMPLICIT_DEF)),1765 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;1766 def : Pat<(vti.Vector (riscv_trunc_vector_vl1767 (wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2),1768 srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)),1769 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)1770 (vti.Vector (IMPLICIT_DEF)),1771 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;1772 }1773 }1774}1775 1776multiclass VPatFPMulAddVL_VV_VF<SDPatternOperator vop, string instruction_name> {1777 foreach vti = AllFloatVectors in {1778 defvar suffix = vti.LMul.MX;1779 let Predicates = GetVTypePredicates<vti>.Predicates in {1780 def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd,1781 vti.RegClass:$rs2, (vti.Mask VMV0:$vm),1782 VLOpFrag)),1783 (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")1784 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,1785 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;1786 1787 def : Pat<(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1),1788 vti.RegClass:$rd, vti.RegClass:$rs2,1789 (vti.Mask VMV0:$vm),1790 VLOpFrag)),1791 (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")1792 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,1793 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;1794 }1795 }1796}1797 1798multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_name> {1799 foreach vti = AllFloatVectors in {1800 defvar suffix = vti.LMul.MX # "_E" # vti.SEW;1801 let Predicates = GetVTypePredicates<vti>.Predicates in {1802 def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd,1803 vti.RegClass:$rs2, (vti.Mask VMV0:$vm),1804 VLOpFrag)),1805 (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")1806 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,1807 (vti.Mask VMV0:$vm),1808 // Value to indicate no rounding mode change in1809 // RISCVInsertReadWriteCSR1810 FRM_DYN,1811 GPR:$vl, vti.Log2SEW, TA_MA)>;1812 1813 def : Pat<(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1),1814 vti.RegClass:$rd, vti.RegClass:$rs2,1815 (vti.Mask VMV0:$vm),1816 VLOpFrag)),1817 (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")1818 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,1819 (vti.Mask VMV0:$vm),1820 // Value to indicate no rounding mode change in1821 // RISCVInsertReadWriteCSR1822 FRM_DYN,1823 GPR:$vl, vti.Log2SEW, TA_MA)>;1824 }1825 }1826}1827 1828multiclass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name,1829 list<VTypeInfoToWide> vtiToWtis =1830 AllWidenableFloatVectors> {1831 foreach vtiToWti = vtiToWtis in {1832 defvar vti = vtiToWti.Vti;1833 defvar wti = vtiToWti.Wti;1834 defvar suffix = vti.LMul.MX # "_E" # vti.SEW;1835 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1836 GetVTypePredicates<wti>.Predicates,1837 !if(!eq(vti.Scalar, bf16),1838 [HasStdExtZvfbfwma],1839 [])) in {1840 def : Pat<(vop (vti.Vector vti.RegClass:$rs1),1841 (vti.Vector vti.RegClass:$rs2),1842 (wti.Vector wti.RegClass:$rd), (vti.Mask VMV0:$vm),1843 VLOpFrag),1844 (!cast<Instruction>(instruction_name#"_VV_"#suffix#"_MASK")1845 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,1846 (vti.Mask VMV0:$vm),1847 // Value to indicate no rounding mode change in1848 // RISCVInsertReadWriteCSR1849 FRM_DYN,1850 GPR:$vl, vti.Log2SEW, TA_MA)>;1851 def : Pat<(vop (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),1852 (vti.Vector vti.RegClass:$rs2),1853 (wti.Vector wti.RegClass:$rd), (vti.Mask VMV0:$vm),1854 VLOpFrag),1855 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix#"_MASK")1856 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,1857 (vti.Mask VMV0:$vm),1858 // Value to indicate no rounding mode change in1859 // RISCVInsertReadWriteCSR1860 FRM_DYN,1861 GPR:$vl, vti.Log2SEW, TA_MA)>;1862 }1863 }1864}1865 1866multiclass VPatSlideVL_VX_VI<SDNode vop, string instruction_name> {1867 foreach vti = AllVectors in {1868 defvar ivti = GetIntVTypeInfo<vti>.Vti;1869 let Predicates = GetVTypePredicates<ivti>.Predicates in {1870 def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rd),1871 (vti.Vector vti.RegClass:$rs1),1872 uimm5:$rs2, (vti.Mask VMV0:$vm),1873 VLOpFrag, (XLenVT timm:$policy))),1874 (!cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK")1875 vti.RegClass:$rd, vti.RegClass:$rs1, uimm5:$rs2,1876 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,1877 (XLenVT timm:$policy))>;1878 1879 def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rd),1880 (vti.Vector vti.RegClass:$rs1),1881 GPR:$rs2, (vti.Mask VMV0:$vm),1882 VLOpFrag, (XLenVT timm:$policy))),1883 (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK")1884 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2,1885 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,1886 (XLenVT timm:$policy))>;1887 }1888 }1889}1890 1891multiclass VPatSlide1VL_VX<SDNode vop, string instruction_name> {1892 foreach vti = AllIntegerVectors in {1893 let Predicates = GetVTypePredicates<vti>.Predicates in {1894 def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rs3),1895 (vti.Vector vti.RegClass:$rs1),1896 GPR:$rs2, (vti.Mask VMV0:$vm), VLOpFrag)),1897 (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK")1898 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2,1899 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TU_MU)>;1900 }1901 }1902}1903 1904multiclass VPatSlide1VL_VF<SDNode vop, string instruction_name> {1905 foreach vti = AllFloatVectors in {1906 let Predicates = GetVTypePredicates<vti>.Predicates in {1907 def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rs3),1908 (vti.Vector vti.RegClass:$rs1),1909 vti.Scalar:$rs2, (vti.Mask VMV0:$vm), VLOpFrag)),1910 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_MASK")1911 vti.RegClass:$rs3, vti.RegClass:$rs1, vti.Scalar:$rs2,1912 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TU_MU)>;1913 }1914 }1915}1916 1917multiclass VPatAVGADDVL_VV_VX_RM<SDNode vop, int vxrm, string suffix = ""> {1918 foreach vti = AllIntegerVectors in {1919 let Predicates = GetVTypePredicates<vti>.Predicates in {1920 def : Pat<(vop (vti.Vector vti.RegClass:$rs1),1921 (vti.Vector vti.RegClass:$rs2),1922 vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),1923 (!cast<Instruction>("PseudoVAADD"#suffix#"_VV_"#vti.LMul.MX#"_MASK")1924 vti.RegClass:$passthru, vti.RegClass:$rs1, vti.RegClass:$rs2,1925 (vti.Mask VMV0:$vm), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1926 def : Pat<(vop (vti.Vector vti.RegClass:$rs1),1927 (vti.Vector (SplatPat (XLenVT GPR:$rs2))),1928 vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),1929 (!cast<Instruction>("PseudoVAADD"#suffix#"_VX_"#vti.LMul.MX#"_MASK")1930 vti.RegClass:$passthru, vti.RegClass:$rs1, GPR:$rs2,1931 (vti.Mask VMV0:$vm), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1932 }1933 }1934}1935 1936//===----------------------------------------------------------------------===//1937// Patterns.1938//===----------------------------------------------------------------------===//1939 1940// 11. Vector Integer Arithmetic Instructions1941 1942// 11.1. Vector Single-Width Integer Add and Subtract1943defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">;1944defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">;1945foreach vti = AllIntegerVectors in {1946 let Predicates = GetVTypePredicates<vti>.Predicates in {1947 // Handle VRSUB specially since it's the only integer binary op with1948 // reversed pattern operands1949 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))),1950 (vti.Vector vti.RegClass:$rs1),1951 vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),1952 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK")1953 vti.RegClass:$passthru, vti.RegClass:$rs1, GPR:$rs2,1954 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1955 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)),1956 (vti.Vector vti.RegClass:$rs1),1957 vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),1958 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK")1959 vti.RegClass:$passthru, vti.RegClass:$rs1, simm5:$rs2,1960 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1961 1962 // Match VSUB with a small immediate to vadd.vi by negating the immediate.1963 def : Pat<(riscv_sub_vl (vti.Vector vti.RegClass:$rs1),1964 (vti.Vector (SplatPat_simm5_plus1_nodec simm5_plus1:$rs2)),1965 vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),1966 (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX#"_MASK")1967 vti.RegClass:$passthru, vti.RegClass:$rs1,1968 (NegImm simm5_plus1:$rs2), (vti.Mask VMV0:$vm),1969 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1970 }1971}1972 1973// (add v, C) -> (sub v, -C) if -C cheaper to materialize1974foreach vti = I64IntegerVectors in {1975 let Predicates = [HasVInstructionsI64] in {1976 def : Pat<(riscv_add_vl (vti.Vector vti.RegClass:$rs1),1977 (vti.Vector (SplatPat_imm64_neg (i64 GPR:$rs2))),1978 vti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),1979 (!cast<Instruction>("PseudoVSUB_VX_"#vti.LMul.MX#"_MASK")1980 vti.RegClass:$passthru, vti.RegClass:$rs1,1981 negImm:$rs2, (vti.Mask VMV0:$vm),1982 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;1983 }1984}1985 1986// 11.2. Vector Widening Integer Add/Subtract1987defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwadd_vl, riscv_vwadd_w_vl, "PseudoVWADD">;1988defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWADDU">;1989defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">;1990defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">;1991 1992// shl_vl (ext_vl v, splat 1) is a special case of widening add.1993foreach vtiToWti = AllWidenableIntVectors in {1994 defvar vti = vtiToWti.Vti;1995 defvar wti = vtiToWti.Wti;1996 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,1997 GetVTypePredicates<wti>.Predicates) in {1998 def : Pat<(riscv_shl_vl (wti.Vector (riscv_sext_vl_oneuse1999 (vti.Vector vti.RegClass:$rs1),2000 (vti.Mask VMV0:$vm), VLOpFrag)),2001 (wti.Vector (riscv_vmv_v_x_vl2002 (wti.Vector undef), 1, VLOpFrag)),2003 wti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),2004 (!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX#"_MASK")2005 wti.RegClass:$passthru, vti.RegClass:$rs1, vti.RegClass:$rs1,2006 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2007 def : Pat<(riscv_shl_vl (wti.Vector (riscv_zext_vl_oneuse2008 (vti.Vector vti.RegClass:$rs1),2009 (vti.Mask VMV0:$vm), VLOpFrag)),2010 (wti.Vector (riscv_vmv_v_x_vl2011 (wti.Vector undef), 1, VLOpFrag)),2012 wti.RegClass:$passthru, (vti.Mask VMV0:$vm), VLOpFrag),2013 (!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX#"_MASK")2014 wti.RegClass:$passthru, vti.RegClass:$rs1, vti.RegClass:$rs1,2015 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2016 }2017}2018 2019// DAGCombiner::hoistLogicOpWithSameOpcodeHands may hoist disjoint ors2020// to (ext (or disjoint (a, b)))2021multiclass VPatWidenOrDisjointVL_VV_VX<SDNode extop, string instruction_name> {2022 foreach vtiToWti = AllWidenableIntVectors in {2023 defvar vti = vtiToWti.Vti;2024 defvar wti = vtiToWti.Wti;2025 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,2026 GetVTypePredicates<wti>.Predicates) in {2027 def : Pat<(wti.Vector2028 (extop2029 (vti.Vector2030 (riscv_or_vl_is_add_oneuse2031 vti.RegClass:$rs2, vti.RegClass:$rs1,2032 undef, srcvalue, srcvalue)),2033 VMV0:$vm, VLOpFrag)),2034 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")2035 (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,2036 vti.RegClass:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;2037 def : Pat<(wti.Vector2038 (extop2039 (vti.Vector2040 (riscv_or_vl_is_add_oneuse2041 vti.RegClass:$rs2, (SplatPat (XLenVT GPR:$rs1)),2042 undef, srcvalue, srcvalue)),2043 VMV0:$vm, VLOpFrag)),2044 (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK")2045 (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,2046 GPR:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;2047 }2048 }2049}2050 2051defm : VPatWidenOrDisjointVL_VV_VX<riscv_sext_vl, "PseudoVWADD">;2052defm : VPatWidenOrDisjointVL_VV_VX<riscv_zext_vl, "PseudoVWADDU">;2053 2054// 11.3. Vector Integer Extension2055defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF2",2056 AllFractionableVF2IntVectors>;2057defm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF2",2058 AllFractionableVF2IntVectors>;2059defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF4",2060 AllFractionableVF4IntVectors>;2061defm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF4",2062 AllFractionableVF4IntVectors>;2063defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF8",2064 AllFractionableVF8IntVectors>;2065defm : VPatExtendVL_V<riscv_sext_vl, "PseudoVSEXT", "VF8",2066 AllFractionableVF8IntVectors>;2067 2068// 11.5. Vector Bitwise Logical Instructions2069defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">;2070defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">;2071defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">;2072 2073// 11.6. Vector Single-Width Bit Shift Instructions2074defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>;2075defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>;2076defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>;2077 2078foreach vti = AllIntegerVectors in {2079 // Emit shift by 1 as an add since it might be faster.2080 let Predicates = GetVTypePredicates<vti>.Predicates in2081 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1),2082 (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)),2083 srcvalue, (vti.Mask true_mask), VLOpFrag),2084 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)2085 (vti.Vector (IMPLICIT_DEF)),2086 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;2087}2088 2089// 11.7. Vector Narrowing Integer Right Shift Instructions2090defm : VPatBinaryVL_WV_WX_WI<srl, "PseudoVNSRL">;2091defm : VPatBinaryVL_WV_WX_WI<sra, "PseudoVNSRA">;2092 2093defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">;2094defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">;2095defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">;2096defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">;2097defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">;2098defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">;2099 2100defm : VPatNarrowShiftVL_WV<riscv_srl_vl, "PseudoVNSRL">;2101defm : VPatNarrowShiftVL_WV<riscv_sra_vl, "PseudoVNSRA">;2102 2103foreach vtiTowti = AllWidenableIntVectors in {2104 defvar vti = vtiTowti.Vti;2105 defvar wti = vtiTowti.Wti;2106 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,2107 GetVTypePredicates<wti>.Predicates) in2108 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1),2109 (vti.Mask VMV0:$vm),2110 VLOpFrag)),2111 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX#"_MASK")2112 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,2113 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;2114}2115 2116// 11.8. Vector Integer Comparison Instructions2117foreach vti = AllIntegerVectors in {2118 let Predicates = GetVTypePredicates<vti>.Predicates in {2119 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>;2120 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>;2121 2122 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;2123 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;2124 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;2125 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;2126 2127 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>;2128 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>;2129 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;2130 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;2131 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;2132 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;2133 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;2134 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;2135 // There is no VMSGE(U)_VX instruction2136 2137 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>;2138 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>;2139 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;2140 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;2141 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;2142 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;2143 2144 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,2145 SplatPat_simm5_plus1>;2146 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,2147 SplatPat_simm5_plus1_nonzero>;2148 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,2149 SplatPat_simm5_plus1>;2150 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,2151 SplatPat_simm5_plus1_nonzero>;2152 }2153} // foreach vti = AllIntegerVectors2154 2155// 11.9. Vector Integer Min/Max Instructions2156defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">;2157defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">;2158defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">;2159defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">;2160 2161// 11.10. Vector Single-Width Integer Multiply Instructions2162defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">;2163defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH", IntegerVectorsExceptI64>;2164defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU", IntegerVectorsExceptI64>;2165// vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*.2166let Predicates = [HasVInstructionsFullMultiply] in {2167 defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH", I64IntegerVectors>;2168 defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU", I64IntegerVectors>;2169}2170 2171// 11.11. Vector Integer Divide Instructions2172defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU", isSEWAware=1>;2173defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV", isSEWAware=1>;2174defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU", isSEWAware=1>;2175defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM", isSEWAware=1>;2176 2177// 11.12. Vector Widening Integer Multiply Instructions2178defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">;2179defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">;2180defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">;2181 2182// 11.13 Vector Single-Width Integer Multiply-Add Instructions2183defm : VPatMultiplyAddVL_VV_VX<riscv_add_vl, "PseudoVMADD">;2184defm : VPatMultiplyAddVL_VV_VX<riscv_sub_vl, "PseudoVNMSUB">;2185 2186// 11.14. Vector Widening Integer Multiply-Add Instructions2187defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmacc_vl, "PseudoVWMACC">;2188defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmaccu_vl, "PseudoVWMACCU">;2189defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmaccsu_vl, "PseudoVWMACCSU">;2190foreach vtiTowti = AllWidenableIntVectors in {2191 defvar vti = vtiTowti.Vti;2192 defvar wti = vtiTowti.Wti;2193 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,2194 GetVTypePredicates<wti>.Predicates) in2195 def : Pat<(riscv_vwmaccsu_vl (vti.Vector vti.RegClass:$rs1),2196 (SplatPat XLenVT:$rs2),2197 (wti.Vector wti.RegClass:$rd),2198 (vti.Mask VMV0:$vm), VLOpFrag),2199 (!cast<Instruction>("PseudoVWMACCUS_VX_"#vti.LMul.MX#"_MASK")2200 wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1,2201 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2202}2203 2204// 11.15. Vector Integer Merge Instructions2205foreach vti = AllIntegerVectors in {2206 let Predicates = GetVTypePredicates<vti>.Predicates in {2207 def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask VMV0:$vm),2208 vti.RegClass:$rs1,2209 vti.RegClass:$rs2,2210 vti.RegClass:$passthru,2211 VLOpFrag)),2212 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)2213 vti.RegClass:$passthru, vti.RegClass:$rs2, vti.RegClass:$rs1,2214 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;2215 2216 def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask VMV0:$vm),2217 (SplatPat XLenVT:$rs1),2218 vti.RegClass:$rs2,2219 vti.RegClass:$passthru,2220 VLOpFrag)),2221 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX)2222 vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$rs1,2223 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;2224 2225 def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask VMV0:$vm),2226 (SplatPat_simm5 simm5:$rs1),2227 vti.RegClass:$rs2,2228 vti.RegClass:$passthru,2229 VLOpFrag)),2230 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX)2231 vti.RegClass:$passthru, vti.RegClass:$rs2, simm5:$rs1,2232 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW)>;2233 }2234}2235 2236// 11.16. Vector Integer Move Instructions2237foreach vti = AllVectors in {2238 defvar ivti = GetIntVTypeInfo<vti>.Vti;2239 let Predicates = GetVTypePredicates<ivti>.Predicates in {2240 def : Pat<(vti.Vector (riscv_vmv_v_v_vl vti.RegClass:$passthru,2241 vti.RegClass:$rs2, VLOpFrag)),2242 (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)2243 vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;2244}2245 2246foreach vti = AllIntegerVectors in {2247 let Predicates = GetVTypePredicates<vti>.Predicates in {2248 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, GPR:$rs2, VLOpFrag)),2249 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)2250 vti.RegClass:$passthru, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;2251 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");2252 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, (ImmPat simm5:$imm5),2253 VLOpFrag)),2254 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)2255 vti.RegClass:$passthru, simm5:$imm5, GPR:$vl, vti.Log2SEW, TU_MU)>;2256 }2257 }2258}2259 2260// 12. Vector Fixed-Point Arithmetic Instructions2261 2262// 12.1. Vector Single-Width Saturating Add and Subtract2263defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">;2264defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">;2265defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">;2266defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">;2267 2268// 12.2. Vector Single-Width Averaging Add and Subtract2269defm : VPatAVGADDVL_VV_VX_RM<riscv_avgfloors_vl, 0b10>;2270defm : VPatAVGADDVL_VV_VX_RM<riscv_avgflooru_vl, 0b10, suffix="U">;2271defm : VPatAVGADDVL_VV_VX_RM<riscv_avgceils_vl, 0b00>;2272defm : VPatAVGADDVL_VV_VX_RM<riscv_avgceilu_vl, 0b00, suffix="U">;2273 2274// 12.5. Vector Narrowing Fixed-Point Clip Instructions2275foreach vtiTowti = AllWidenableIntVectors in {2276 defvar vti = vtiTowti.Vti;2277 defvar wti = vtiTowti.Wti;2278 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,2279 GetVTypePredicates<wti>.Predicates) in {2280 // Rounding mode here is arbitrary since we aren't shifting out any bits.2281 def : Pat<(vti.Vector (riscv_trunc_vector_vl_ssat (wti.Vector wti.RegClass:$rs1),2282 (vti.Mask VMV0:$vm),2283 VLOpFrag)),2284 (!cast<Instruction>("PseudoVNCLIP_WI_"#vti.LMul.MX#"_MASK")2285 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,2286 (vti.Mask VMV0:$vm), /*RNU*/0, GPR:$vl, vti.Log2SEW, TA_MA)>;2287 def : Pat<(vti.Vector (riscv_trunc_vector_vl_usat (wti.Vector wti.RegClass:$rs1),2288 (vti.Mask VMV0:$vm),2289 VLOpFrag)),2290 (!cast<Instruction>("PseudoVNCLIPU_WI_"#vti.LMul.MX#"_MASK")2291 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,2292 (vti.Mask VMV0:$vm), /*RNU*/0, GPR:$vl, vti.Log2SEW, TA_MA)>;2293 }2294}2295 2296// 13. Vector Floating-Point Instructions2297 2298// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions2299defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fadd_vl, "PseudoVFADD", isSEWAware=1>;2300defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fsub_vl, "PseudoVFSUB", isSEWAware=1>;2301defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fsub_vl, "PseudoVFRSUB", isSEWAware=1>;2302 2303// 13.3. Vector Widening Floating-Point Add/Subtract Instructions2304defm : VPatBinaryFPWVL_VV_VF_WV_WF_RM<riscv_vfwadd_vl, riscv_vfwadd_w_vl,2305 "PseudoVFWADD", isSEWAware=1>;2306defm : VPatBinaryFPWVL_VV_VF_WV_WF_RM<riscv_vfwsub_vl, riscv_vfwsub_w_vl,2307 "PseudoVFWSUB", isSEWAware=1>;2308 2309// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions2310defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL", isSEWAware=1>;2311defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", isSEWAware=1>;2312defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", isSEWAware=1>;2313 2314// 13.5. Vector Widening Floating-Point Multiply Instructions2315defm : VPatBinaryFPWVL_VV_VF_RM<riscv_vfwmul_vl, "PseudoVFWMUL", isSEWAware=1>;2316 2317// 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions.2318defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmadd_vl, "PseudoVFMADD">;2319defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmsub_vl, "PseudoVFMSUB">;2320defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmadd_vl, "PseudoVFNMADD">;2321defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmsub_vl, "PseudoVFNMSUB">;2322 2323// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions2324defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmadd_vl, "PseudoVFWMACC">;2325defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwnmadd_vl, "PseudoVFWNMACC">;2326defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmsub_vl, "PseudoVFWMSAC">;2327defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwnmsub_vl, "PseudoVFWNMSAC">;2328 2329// 13.11. Vector Floating-Point MIN/MAX Instructions2330defm : VPatBinaryFPVL_VV_VF<riscv_vfmin_vl, "PseudoVFMIN", isSEWAware=1>;2331defm : VPatBinaryFPVL_VV_VF<riscv_vfmax_vl, "PseudoVFMAX", isSEWAware=1>;2332 2333// 13.13. Vector Floating-Point Compare Instructions2334defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETEQ,2335 "PseudoVMFEQ", "PseudoVMFEQ">;2336defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETOEQ,2337 "PseudoVMFEQ", "PseudoVMFEQ">;2338defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETNE,2339 "PseudoVMFNE", "PseudoVMFNE">;2340defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetcc_vl, SETUNE,2341 "PseudoVMFNE", "PseudoVMFNE">;2342defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETLT,2343 "PseudoVMFLT", "PseudoVMFGT">;2344defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETOLT,2345 "PseudoVMFLT", "PseudoVMFGT">;2346defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETLE,2347 "PseudoVMFLE", "PseudoVMFGE">;2348defm : VPatFPSetCCVL_VV_VF_FV<any_riscv_fsetccs_vl, SETOLE,2349 "PseudoVMFLE", "PseudoVMFGE">;2350 2351foreach vti = AllFloatVectors in {2352 let Predicates = GetVTypePredicates<vti>.Predicates in {2353 // 13.8. Vector Floating-Point Square-Root Instruction2354 def : Pat<(any_riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask VMV0:$vm),2355 VLOpFrag),2356 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX # "_E" # vti.SEW # "_MASK")2357 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,2358 (vti.Mask VMV0:$vm),2359 // Value to indicate no rounding mode change in2360 // RISCVInsertReadWriteCSR2361 FRM_DYN,2362 GPR:$vl, vti.Log2SEW, TA_MA)>;2363 2364 // 13.12. Vector Floating-Point Sign-Injection Instructions2365 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),2366 VLOpFrag),2367 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX #"_E"#vti.SEW#"_MASK")2368 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,2369 vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,2370 TA_MA)>;2371 // Handle fneg with VFSGNJN using the same input for both operands.2372 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),2373 VLOpFrag),2374 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX#"_E"#vti.SEW #"_MASK")2375 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,2376 vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,2377 TA_MA)>;2378 2379 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),2380 (vti.Vector vti.RegClass:$rs2),2381 vti.RegClass:$passthru,2382 (vti.Mask VMV0:$vm),2383 VLOpFrag),2384 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")2385 vti.RegClass:$passthru, vti.RegClass:$rs1,2386 vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,2387 TAIL_AGNOSTIC)>;2388 2389 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),2390 (riscv_fneg_vl vti.RegClass:$rs2,2391 (vti.Mask true_mask),2392 VLOpFrag),2393 srcvalue,2394 (vti.Mask true_mask),2395 VLOpFrag),2396 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX#"_E"#vti.SEW)2397 (vti.Vector (IMPLICIT_DEF)),2398 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;2399 2400 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),2401 (SplatFPOp vti.ScalarRegClass:$rs2),2402 vti.RegClass:$passthru,2403 (vti.Mask VMV0:$vm),2404 VLOpFrag),2405 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")2406 vti.RegClass:$passthru, vti.RegClass:$rs1,2407 vti.ScalarRegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,2408 TAIL_AGNOSTIC)>;2409 2410 // Rounding without exception to implement nearbyint.2411 def : Pat<(any_riscv_vfround_noexcept_vl (vti.Vector vti.RegClass:$rs1),2412 (vti.Mask VMV0:$vm), VLOpFrag),2413 (!cast<Instruction>("PseudoVFROUND_NOEXCEPT_V_" # vti.LMul.MX #"_MASK")2414 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,2415 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;2416 2417 // 14.14. Vector Floating-Point Classify Instruction2418 def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2),2419 (vti.Mask VMV0:$vm), VLOpFrag),2420 (!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX #"_MASK")2421 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, 2422 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;2423 }2424}2425 2426// Floating-point vselects:2427// 11.15. Vector Integer Merge Instructions2428// 13.15. Vector Floating-Point Merge Instruction2429foreach fvti = AllFloatAndBF16Vectors in {2430 defvar ivti = GetIntVTypeInfo<fvti>.Vti;2431 let Predicates = GetVTypePredicates<ivti>.Predicates in {2432 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),2433 fvti.RegClass:$rs1,2434 fvti.RegClass:$rs2,2435 fvti.RegClass:$passthru,2436 VLOpFrag)),2437 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)2438 fvti.RegClass:$passthru, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask VMV0:$vm),2439 GPR:$vl, fvti.Log2SEW)>;2440 }2441}2442 2443foreach fvti = AllFloatVectors in {2444 defvar ivti = GetIntVTypeInfo<fvti>.Vti;2445 let Predicates = GetVTypePredicates<ivti>.Predicates in {2446 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),2447 (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))),2448 fvti.RegClass:$rs2,2449 fvti.RegClass:$passthru,2450 VLOpFrag)),2451 (!cast<Instruction>("PseudoVMERGE_VXM_"#fvti.LMul.MX)2452 fvti.RegClass:$passthru, fvti.RegClass:$rs2, GPR:$imm, (fvti.Mask VMV0:$vm),2453 GPR:$vl, fvti.Log2SEW)>;2454 2455 2456 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),2457 (SplatFPOp (fvti.Scalar fpimm0)),2458 fvti.RegClass:$rs2,2459 fvti.RegClass:$passthru,2460 VLOpFrag)),2461 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)2462 fvti.RegClass:$passthru, fvti.RegClass:$rs2, 0, (fvti.Mask VMV0:$vm),2463 GPR:$vl, fvti.Log2SEW)>;2464 }2465 2466 let Predicates = GetVTypePredicates<fvti>.Predicates in {2467 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),2468 (SplatFPOp fvti.ScalarRegClass:$rs1),2469 fvti.RegClass:$rs2,2470 fvti.RegClass:$passthru,2471 VLOpFrag)),2472 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)2473 fvti.RegClass:$passthru, fvti.RegClass:$rs2,2474 (fvti.Scalar fvti.ScalarRegClass:$rs1),2475 (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW)>;2476 }2477}2478 2479foreach fvti = AllFloatVectors in {2480 defvar ivti = GetIntVTypeInfo<fvti>.Vti;2481 let Predicates = GetVTypePredicates<ivti>.Predicates in {2482 // 13.16. Vector Floating-Point Move Instruction2483 // If we're splatting fpimm0, use vmv.v.x vd, x0.2484 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl2485 fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)),2486 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)2487 $passthru, 0, GPR:$vl, fvti.Log2SEW, TU_MU)>;2488 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl2489 fvti.Vector:$passthru, (fvti.Scalar (SelectScalarFPAsInt (XLenVT GPR:$imm))), VLOpFrag)),2490 (!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX)2491 $passthru, GPR:$imm, GPR:$vl, fvti.Log2SEW, TU_MU)>;2492 }2493}2494 2495foreach fvti = AllFloatVectors in {2496 let Predicates = GetVTypePredicates<fvti>.Predicates in {2497 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl2498 fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),2499 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #2500 fvti.LMul.MX)2501 $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2),2502 GPR:$vl, fvti.Log2SEW, TU_MU)>;2503 }2504}2505 2506// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions2507defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_XU_F_V">;2508defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_X_F_V">;2509 2510defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFCVT_RTZ_XU_F_V">;2511defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFCVT_RTZ_X_F_V">;2512 2513defm : VPatConvertI2FPVL_V_RM<any_riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;2514defm : VPatConvertI2FPVL_V_RM<any_riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;2515 2516defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_F_XU_V">;2517defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_F_X_V">;2518 2519// 13.18. Widening Floating-Point/Integer Type-Convert Instructions2520defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_XU_F_V">;2521defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_X_F_V">;2522 2523defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFWCVT_RTZ_XU_F_V">;2524defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">;2525 2526defm : VPatWConvertI2FPVL_V<any_riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">;2527defm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;2528 2529foreach fvtiToFWti = AllWidenableFloatVectors in {2530 defvar fvti = fvtiToFWti.Vti;2531 defvar fwti = fvtiToFWti.Wti;2532 // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.2533 let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,2534 GetVTypeMinimalPredicates<fwti>.Predicates) in2535 def : Pat<(fwti.Vector (any_riscv_fpextend_vl2536 (fvti.Vector fvti.RegClass:$rs1),2537 (fvti.Mask VMV0:$vm),2538 VLOpFrag)),2539 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")2540 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,2541 (fvti.Mask VMV0:$vm),2542 GPR:$vl, fvti.Log2SEW, TA_MA)>;2543}2544 2545// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions2546defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;2547defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;2548 2549defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F_W">;2550defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F_W">;2551 2552defm : VPatNConvertI2FPVL_W_RM<any_riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;2553defm : VPatNConvertI2FPVL_W_RM<any_riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;2554 2555defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_F_XU_W">;2556defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_F_X_W">;2557 2558foreach fvtiToFWti = AllWidenableFloatVectors in {2559 defvar fvti = fvtiToFWti.Vti;2560 defvar fwti = fvtiToFWti.Wti;2561 // Define vfncvt.f.f.w for f16 when Zvfhmin is enable.2562 let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,2563 GetVTypeMinimalPredicates<fwti>.Predicates) in {2564 def : Pat<(fvti.Vector (any_riscv_fpround_vl2565 (fwti.Vector fwti.RegClass:$rs1),2566 (fwti.Mask VMV0:$vm), VLOpFrag)),2567 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")2568 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,2569 (fwti.Mask VMV0:$vm),2570 // Value to indicate no rounding mode change in2571 // RISCVInsertReadWriteCSR2572 FRM_DYN,2573 GPR:$vl, fvti.Log2SEW, TA_MA)>;2574 2575 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,2576 GetVTypePredicates<fwti>.Predicates) in2577 def : Pat<(fvti.Vector (any_riscv_fncvt_rod_vl2578 (fwti.Vector fwti.RegClass:$rs1),2579 (fwti.Mask VMV0:$vm), VLOpFrag)),2580 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")2581 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,2582 (fwti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TA_MA)>;2583 }2584}2585 2586// 14. Vector Reduction Operations2587 2588// 14.1. Vector Single-Width Integer Reduction Instructions2589defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", is_float=0>;2590defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", is_float=0>;2591defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", is_float=0>;2592defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", is_float=0>;2593defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", is_float=0>;2594defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", is_float=0>;2595defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", is_float=0>;2596defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", is_float=0>;2597 2598// 14.2. Vector Widening Integer Reduction Instructions2599defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", is_float=0>;2600defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", is_float=0>;2601defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", is_float=0>;2602defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", is_float=0>;2603defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", is_float=0>;2604 2605// 14.3. Vector Single-Width Floating-Point Reduction Instructions2606defm : VPatReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", is_float=1>;2607defm : VPatReductionVL_RM<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", is_float=1>;2608defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", is_float=1>;2609defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", is_float=1>;2610 2611// 14.4. Vector Widening Floating-Point Reduction Instructions2612defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_SEQ_FADD_vl,2613 riscv_fpextend_vl_oneuse,2614 "PseudoVFWREDOSUM", is_float=1>;2615defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_FADD_vl,2616 riscv_fpextend_vl_oneuse,2617 "PseudoVFWREDUSUM", is_float=1>;2618 2619// 15. Vector Mask Instructions2620 2621foreach mti = AllMasks in {2622 let Predicates = [HasVInstructions] in {2623 // 15.1 Vector Mask-Register Logical Instructions2624 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)),2625 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>;2626 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)),2627 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>;2628 2629 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)),2630 (!cast<Instruction>("PseudoVMAND_MM_" # mti.BX)2631 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2632 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)),2633 (!cast<Instruction>("PseudoVMOR_MM_" # mti.BX)2634 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2635 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)),2636 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.BX)2637 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2638 2639 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1,2640 (riscv_vmnot_vl VR:$rs2, VLOpFrag),2641 VLOpFrag)),2642 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.BX)2643 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2644 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1,2645 (riscv_vmnot_vl VR:$rs2, VLOpFrag),2646 VLOpFrag)),2647 (!cast<Instruction>("PseudoVMORN_MM_" # mti.BX)2648 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2649 // XOR is associative so we need 2 patterns for VMXNOR.2650 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1,2651 VLOpFrag),2652 VR:$rs2, VLOpFrag)),2653 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.BX)2654 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2655 2656 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2,2657 VLOpFrag),2658 VLOpFrag)),2659 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.BX)2660 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2661 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2,2662 VLOpFrag),2663 VLOpFrag)),2664 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.BX)2665 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2666 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2,2667 VLOpFrag),2668 VLOpFrag)),2669 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.BX)2670 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;2671 2672 // Match the not idiom to the vmnot.m pseudo.2673 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)),2674 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.BX)2675 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>;2676 2677 // 15.2 Vector count population in mask vcpop.m2678 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask VMV0:$vm),2679 VLOpFrag)),2680 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK")2681 VR:$rs2, (mti.Mask VMV0:$vm), GPR:$vl, mti.Log2SEW)>;2682 2683 // 15.3 vfirst find-first-set mask bit2684 def : Pat<(XLenVT (riscv_vfirst_vl (mti.Mask VR:$rs2), (mti.Mask VMV0:$vm),2685 VLOpFrag)),2686 (!cast<Instruction>("PseudoVFIRST_M_" # mti.BX # "_MASK")2687 VR:$rs2, (mti.Mask VMV0:$vm), GPR:$vl, mti.Log2SEW)>;2688 }2689}2690 2691// 16. Vector Permutation Instructions2692 2693// 16.1. Integer Scalar Move Instructions2694foreach vti = NoGroupIntegerVectors in {2695 let Predicates = GetVTypePredicates<vti>.Predicates in {2696 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$passthru),2697 vti.ScalarRegClass:$rs1,2698 VLOpFrag)),2699 (PseudoVMV_S_X $passthru, vti.ScalarRegClass:$rs1, GPR:$vl,2700 vti.Log2SEW)>;2701 }2702}2703 2704// 16.4. Vector Register Gather Instruction2705foreach vti = AllIntegerVectors in {2706 let Predicates = GetVTypePredicates<vti>.Predicates in {2707 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,2708 vti.RegClass:$rs1,2709 vti.RegClass:$passthru,2710 (vti.Mask VMV0:$vm),2711 VLOpFrag)),2712 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK")2713 vti.RegClass:$passthru, vti.RegClass:$rs2, vti.RegClass:$rs1,2714 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2715 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,2716 vti.RegClass:$passthru,2717 (vti.Mask VMV0:$vm),2718 VLOpFrag)),2719 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX#"_MASK")2720 vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$rs1,2721 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2722 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2,2723 uimm5:$imm,2724 vti.RegClass:$passthru,2725 (vti.Mask VMV0:$vm),2726 VLOpFrag)),2727 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK")2728 vti.RegClass:$passthru, vti.RegClass:$rs2, uimm5:$imm,2729 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2730 }2731 2732 // emul = lmul * 16 / sew2733 defvar vlmul = vti.LMul;2734 defvar octuple_lmul = vlmul.octuple;2735 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW);2736 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {2737 defvar emul_str = octuple_to_str<octuple_emul>.ret;2738 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);2739 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;2740 let Predicates = GetVTypePredicates<vti>.Predicates in2741 def : Pat<(vti.Vector2742 (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,2743 (ivti.Vector ivti.RegClass:$rs1),2744 vti.RegClass:$passthru,2745 (vti.Mask VMV0:$vm),2746 VLOpFrag)),2747 (!cast<Instruction>(inst#"_MASK")2748 vti.RegClass:$passthru, vti.RegClass:$rs2, ivti.RegClass:$rs1,2749 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2750 }2751}2752 2753// 16.2. Floating-Point Scalar Move Instructions2754foreach vti = NoGroupFloatVectors in {2755 let Predicates = GetVTypePredicates<vti>.Predicates in {2756 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$passthru),2757 (vti.Scalar (fpimm0)),2758 VLOpFrag)),2759 (PseudoVMV_S_X $passthru, (XLenVT X0), GPR:$vl, vti.Log2SEW)>;2760 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$passthru),2761 (vti.Scalar (SelectScalarFPAsInt (XLenVT GPR:$imm))),2762 VLOpFrag)),2763 (PseudoVMV_S_X $passthru, GPR:$imm, GPR:$vl, vti.Log2SEW)>;2764 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$passthru),2765 vti.ScalarRegClass:$rs1,2766 VLOpFrag)),2767 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix)2768 vti.RegClass:$passthru,2769 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;2770 }2771}2772 2773foreach vti = AllFloatAndBF16Vectors in {2774 defvar ivti = GetIntVTypeInfo<vti>.Vti;2775 let Predicates = GetVTypePredicates<ivti>.Predicates in {2776 def : Pat<(vti.Vector2777 (riscv_vrgather_vv_vl vti.RegClass:$rs2,2778 (ivti.Vector vti.RegClass:$rs1),2779 vti.RegClass:$passthru,2780 (vti.Mask VMV0:$vm),2781 VLOpFrag)),2782 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK")2783 vti.RegClass:$passthru, vti.RegClass:$rs2, vti.RegClass:$rs1,2784 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2785 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,2786 vti.RegClass:$passthru,2787 (vti.Mask VMV0:$vm),2788 VLOpFrag)),2789 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX#"_MASK")2790 vti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$rs1,2791 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2792 def : Pat<(vti.Vector2793 (riscv_vrgather_vx_vl vti.RegClass:$rs2,2794 uimm5:$imm,2795 vti.RegClass:$passthru,2796 (vti.Mask VMV0:$vm),2797 VLOpFrag)),2798 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK")2799 vti.RegClass:$passthru, vti.RegClass:$rs2, uimm5:$imm,2800 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2801 }2802 2803 defvar vlmul = vti.LMul;2804 defvar octuple_lmul = vlmul.octuple;2805 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW);2806 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {2807 defvar emul_str = octuple_to_str<octuple_emul>.ret;2808 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);2809 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;2810 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,2811 GetVTypePredicates<ivti>.Predicates) in2812 def : Pat<(vti.Vector2813 (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,2814 (ivti.Vector ivti.RegClass:$rs1),2815 vti.RegClass:$passthru,2816 (vti.Mask VMV0:$vm),2817 VLOpFrag)),2818 (!cast<Instruction>(inst#"_MASK")2819 vti.RegClass:$passthru, vti.RegClass:$rs2, ivti.RegClass:$rs1,2820 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;2821 }2822}2823 2824//===----------------------------------------------------------------------===//2825// Miscellaneous RISCVISD SDNodes2826//===----------------------------------------------------------------------===//2827 2828// Matches the semantics of the vid.v instruction, with a mask and VL2829// operand.2830let HasMaskOp = true in2831def riscv_vid_vl : RVSDNode<"VID_VL", SDTypeProfile<1, 2, [SDTCisVec<0>,2832 SDTCVecEltisVT<1, i1>,2833 SDTCisSameNumEltsAs<0, 1>,2834 SDTCisVT<2, XLenVT>]>>;2835 2836def SDTRVVSlide : SDTypeProfile<1, 6, [2837 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>,2838 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT>,2839 SDTCisVT<6, XLenVT>2840]>;2841def SDTRVVSlide1 : SDTypeProfile<1, 5, [2842 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>,2843 SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>,2844 SDTCisVT<5, XLenVT>2845]>;2846def SDTRVVFSlide1 : SDTypeProfile<1, 5, [2847 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisFP<0>,2848 SDTCisEltOfVec<3, 0>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>,2849 SDTCisVT<5, XLenVT>2850]>;2851 2852let HasMaskOp = true in {2853 // Matches the semantics of vslideup/vslidedown. The first operand is the2854 // pass-thru operand, the second is the source vector, the third is the XLenVT2855 // index (either constant or non-constant), the fourth is the mask, the fifth2856 // is the VL and the sixth is the policy.2857 def riscv_slideup_vl : RVSDNode<"VSLIDEUP_VL", SDTRVVSlide, []>;2858 def riscv_slidedown_vl : RVSDNode<"VSLIDEDOWN_VL", SDTRVVSlide, []>;2859 2860 // Matches the semantics of vslide1up/slide1down. The first operand is2861 // passthru operand, the second is source vector, third is the XLenVT scalar2862 // value. The fourth and fifth operands are the mask and VL operands.2863 def riscv_slide1up_vl : RVSDNode<"VSLIDE1UP_VL", SDTRVVSlide1, []>;2864 def riscv_slide1down_vl : RVSDNode<"VSLIDE1DOWN_VL", SDTRVVSlide1, []>;2865 2866 // Matches the semantics of vfslide1up/vfslide1down. The first operand is2867 // passthru operand, the second is source vector, third is a scalar value2868 // whose type matches the element type of the vectors. The fourth and fifth2869 // operands are the mask and VL operands.2870 def riscv_fslide1up_vl : RVSDNode<"VFSLIDE1UP_VL", SDTRVVFSlide1, []>;2871 def riscv_fslide1down_vl : RVSDNode<"VFSLIDE1DOWN_VL", SDTRVVFSlide1, []>;2872} // let HasMaskOp = true2873 2874foreach vti = AllIntegerVectors in {2875 let Predicates = GetVTypePredicates<vti>.Predicates in {2876 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask VMV0:$vm),2877 VLOpFrag)),2878 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX#"_MASK")2879 (vti.Vector (IMPLICIT_DEF)), (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,2880 TAIL_AGNOSTIC)>;2881 }2882}2883 2884defm : VPatSlideVL_VX_VI<riscv_slideup_vl, "PseudoVSLIDEUP">;2885defm : VPatSlideVL_VX_VI<riscv_slidedown_vl, "PseudoVSLIDEDOWN">;2886defm : VPatSlide1VL_VX<riscv_slide1up_vl, "PseudoVSLIDE1UP">;2887defm : VPatSlide1VL_VF<riscv_fslide1up_vl, "PseudoVFSLIDE1UP">;2888defm : VPatSlide1VL_VX<riscv_slide1down_vl, "PseudoVSLIDE1DOWN">;2889defm : VPatSlide1VL_VF<riscv_fslide1down_vl, "PseudoVFSLIDE1DOWN">;2890