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1//===-- RISCVInstrInfoXAndes.td ----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the vendor extensions defined by Andes Technology.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// RISC-V specific DAG Nodes.15//===----------------------------------------------------------------------===//16 17def SDT_NDS_FMV_BF16_X18 : SDTypeProfile<1, 1, [SDTCisVT<0, bf16>, SDTCisVT<1, XLenVT>]>;19def SDT_NDS_FMV_X_ANYEXTBF1620 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, bf16>]>;21 22def riscv_nds_fmv_bf16_x23 : SDNode<"RISCVISD::NDS_FMV_BF16_X", SDT_NDS_FMV_BF16_X>;24def riscv_nds_fmv_x_anyextbf1625 : SDNode<"RISCVISD::NDS_FMV_X_ANYEXTBF16", SDT_NDS_FMV_X_ANYEXTBF16>;26 27//===----------------------------------------------------------------------===//28// Operand and SDNode transformation definitions.29//===----------------------------------------------------------------------===//30 31// A 11-bit signed immediate where the least significant bit is zero.32def bare_simm11_lsb0 : Operand<OtherVT> {33 let ParserMatchClass = BareSImmNLsb0AsmOperand<11>;34 let PrintMethod = "printBranchOperand";35 let EncoderMethod = "getImmOpValueAsrN<1>";36 let DecoderMethod = "decodeSImmOperandAndLslN<11, 1>";37 let MCOperandPredicate = [{38 int64_t Imm;39 if (MCOp.evaluateAsConstantImm(Imm))40 return isShiftedInt<10, 1>(Imm);41 return MCOp.isBareSymbolRef();42 }];43 let OperandType = "OPERAND_PCREL";44}45 46def simm18 : Operand<XLenVT> {47 let ParserMatchClass = SImmAsmOperand<18>;48 let EncoderMethod = "getImmOpValue";49 let DecoderMethod = "decodeSImmOperand<18>";50}51 52def simm18_lsb0 : Operand<XLenVT> {53 let ParserMatchClass = SImmAsmOperand<18, "Lsb0">;54 let EncoderMethod = "getImmOpValueAsrN<1>";55 let DecoderMethod = "decodeSImmOperandAndLslN<18, 1>";56}57 58def simm19_lsb00 : Operand<XLenVT> {59 let ParserMatchClass = SImmAsmOperand<19, "Lsb00">;60 let EncoderMethod = "getImmOpValueAsrN<2>";61 let DecoderMethod = "decodeSImmOperandAndLslN<19, 2>";62}63 64def simm20_lsb000 : Operand<XLenVT> {65 let ParserMatchClass = SImmAsmOperand<20, "Lsb000">;66 let EncoderMethod = "getImmOpValueAsrN<3>";67 let DecoderMethod = "decodeSImmOperandAndLslN<20, 3>";68}69 70// Predicate: True if immediate is a power of 2.71def PowerOf2 : PatLeaf<(imm), [{72 return isPowerOf2_64(N->getZExtValue());73}]>;74 75// Transformation function: Get log2 of immediate.76def Log2 : SDNodeXForm<imm, [{77 uint64_t Imm = Log2_64(N->getZExtValue());78 return CurDAG->getTargetConstant(Imm, SDLoc(N), N->getValueType(0));79}]>;80 81//===----------------------------------------------------------------------===//82// Pseudo table83//===----------------------------------------------------------------------===//84 85class RISCVNDSVLN<bit M, bit U, bits<3> S, bits<3> L> {86 bits<1> Masked = M;87 bits<1> Unsigned = U;88 bits<3> Log2SEW = S;89 bits<3> LMUL = L;90 Pseudo Pseudo = !cast<Pseudo>(NAME);91}92 93def RISCVNDSVLNTable : GenericTable {94 let FilterClass = "RISCVNDSVLN";95 let CppTypeName = "NDSVLNPseudo";96 let Fields = ["Masked", "Unsigned", "Log2SEW", "LMUL", "Pseudo"];97 let PrimaryKey = ["Masked", "Unsigned", "Log2SEW", "LMUL"];98 let PrimaryKeyName = "getNDSVLNPseudo";99}100 101//===----------------------------------------------------------------------===//102// Instruction Class Templates103//===----------------------------------------------------------------------===//104 105class NDSRVInstBB<bit cs, string opcodestr>106 : RVInst<(outs),107 (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10),108 opcodestr, "$rs1, $cimm, $imm10", [], InstFormatNDS_BRANCH_10>,109 Sched<[WriteJmp, ReadIALU]> {110 bits<10> imm10;111 bits<5> rs1;112 bits<6> cimm;113 114 let Inst{31} = imm10{9};115 let Inst{30} = cs;116 let Inst{29-25} = imm10{8-4};117 let Inst{24-20} = cimm{4-0};118 let Inst{19-15} = rs1;119 let Inst{14-12} = 0b111;120 let Inst{11-8} = imm10{3-0};121 let Inst{7} = cimm{5};122 let Inst{6-0} = OPC_CUSTOM_2.Value;123 let hasSideEffects = 0;124 let mayLoad = 0;125 let mayStore = 0;126 let isBranch = 1;127 let isTerminator = 1;128}129 130class NDSRVInstBC<bits<3> funct3, string opcodestr>131 : RVInst<(outs), (ins GPR:$rs1, uimm7:$cimm, bare_simm11_lsb0:$imm10),132 opcodestr, "$rs1, $cimm, $imm10", [], InstFormatNDS_BRANCH_10>,133 Sched<[WriteJmp, ReadIALU]> {134 bits<10> imm10;135 bits<5> rs1;136 bits<7> cimm;137 138 let Inst{31} = imm10{9};139 let Inst{30} = cimm{6};140 let Inst{29-25} = imm10{8-4};141 let Inst{24-20} = cimm{4-0};142 let Inst{19-15} = rs1;143 let Inst{14-12} = funct3;144 let Inst{11-8} = imm10{3-0};145 let Inst{7} = cimm{5};146 let Inst{6-0} = OPC_CUSTOM_2.Value;147 let hasSideEffects = 0;148 let mayLoad = 0;149 let mayStore = 0;150 let isBranch = 1;151 let isTerminator = 1;152}153 154class NDSRVInstBFO<bits<3> funct3, string opcodestr>155 : RVInst<(outs GPR:$rd),156 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),157 opcodestr, "$rd, $rs1, $msb, $lsb", [], InstFormatOther>,158 Sched<[WriteIALU, ReadIALU]> {159 bits<5> rd;160 bits<5> rs1;161 bits<6> msb;162 bits<6> lsb;163 164 let Inst{31-26} = msb;165 let Inst{25-20} = lsb;166 let Inst{19-15} = rs1;167 let Inst{14-12} = funct3;168 let Inst{11-7} = rd;169 let Inst{6-0} = OPC_CUSTOM_2.Value;170 let hasSideEffects = 0;171 let mayLoad = 0;172 let mayStore = 0;173}174 175class NDSRVInstRR<bits<7> funct7, string opcodestr>176 : RVInstR<funct7, 0b000, OPC_CUSTOM_2,177 (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),178 opcodestr, "$rd, $rs1, $rs2">,179 Sched<[WriteIALU, ReadIALU, ReadIALU]> {180 let hasSideEffects = 0;181 let mayLoad = 0;182 let mayStore = 0;183}184 185class NDSRVInstLEA<bits<7> funct7, string opcodestr>186 : RVInstR<funct7, 0b000, OPC_CUSTOM_2,187 (outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1),188 opcodestr, "$rd, $rs1, $rs2">,189 Sched<[WriteIALU, ReadIALU, ReadIALU]> {190 let hasSideEffects = 0;191 let mayLoad = 0;192 let mayStore = 0;193}194 195// GP: ADDI, LB, LBU196class NDSRVInstLBGP<bits<2> funct2, string opcodestr>197 : RVInst<(outs GPR:$rd), (ins simm18:$imm18),198 opcodestr, "$rd, ${imm18}", [], InstFormatOther> {199 bits<18> imm18;200 bits<5> rd;201 202 let Inst{31} = imm18{17};203 let Inst{30-21} = imm18{10-1};204 let Inst{20} = imm18{11};205 let Inst{19-17} = imm18{14-12};206 let Inst{16-15} = imm18{16-15};207 let Inst{14} = imm18{0};208 let Inst{13-12} = funct2;209 let Inst{11-7} = rd;210 let Inst{6-0} = OPC_CUSTOM_0.Value;211 let hasSideEffects = 0;212 let mayLoad = 1;213 let mayStore = 0;214}215 216// GP: LH, LHU217class NDSRVInstLHGP<bits<3> funct3, string opcodestr>218 : RVInst<(outs GPR:$rd), (ins simm18_lsb0:$imm17),219 opcodestr, "$rd, ${imm17}", [], InstFormatOther> {220 bits<17> imm17;221 bits<5> rd;222 223 let Inst{31} = imm17{16};224 let Inst{30-21} = imm17{9-0};225 let Inst{20} = imm17{10};226 let Inst{19-17} = imm17{13-11};227 let Inst{16-15} = imm17{15-14};228 let Inst{14-12} = funct3;229 let Inst{11-7} = rd;230 let Inst{6-0} = OPC_CUSTOM_1.Value;231 let hasSideEffects = 0;232 let mayLoad = 1;233 let mayStore = 0;234}235 236// GP: LW, LWU237class NDSRVInstLWGP<bits<3> funct3, string opcodestr>238 : RVInst<(outs GPR:$rd), (ins simm19_lsb00:$imm17),239 opcodestr, "$rd, ${imm17}", [], InstFormatOther> {240 bits<17> imm17;241 bits<5> rd;242 243 let Inst{31} = imm17{16};244 let Inst{30-22} = imm17{8-0};245 let Inst{21} = imm17{15};246 let Inst{20} = imm17{9};247 let Inst{19-17} = imm17{12-10};248 let Inst{16-15} = imm17{14-13};249 let Inst{14-12} = funct3;250 let Inst{11-7} = rd;251 let Inst{6-0} = OPC_CUSTOM_1.Value;252 let hasSideEffects = 0;253 let mayLoad = 1;254 let mayStore = 0;255}256 257// GP: LD258class NDSRVInstLDGP<bits<3> funct3, string opcodestr>259 : RVInst<(outs GPR:$rd), (ins simm20_lsb000:$imm17),260 opcodestr, "$rd, ${imm17}", [], InstFormatOther> {261 bits<17> imm17;262 bits<5> rd;263 264 let Inst{31} = imm17{16};265 let Inst{30-23} = imm17{7-0};266 let Inst{22-21} = imm17{15-14};267 let Inst{20} = imm17{8};268 let Inst{19-17} = imm17{11-9};269 let Inst{16-15} = imm17{13-12};270 let Inst{14-12} = funct3;271 let Inst{11-7} = rd;272 let Inst{6-0} = OPC_CUSTOM_1.Value;273 let hasSideEffects = 0;274 let mayLoad = 1;275 let mayStore = 0;276}277 278// GP: SB279class NDSRVInstSBGP<bits<2> funct2, string opcodestr>280 : RVInst<(outs), (ins GPR:$rs2, simm18:$imm18),281 opcodestr, "$rs2, ${imm18}", [], InstFormatOther> {282 bits<18> imm18;283 bits<5> rs2;284 285 let Inst{31} = imm18{17};286 let Inst{30-25} = imm18{10-5};287 let Inst{24-20} = rs2;288 let Inst{19-17} = imm18{14-12};289 let Inst{16-15} = imm18{16-15};290 let Inst{14} = imm18{0};291 let Inst{13-12} = funct2;292 let Inst{11-8} = imm18{4-1};293 let Inst{7} = imm18{11};294 let Inst{6-0} = OPC_CUSTOM_0.Value;295 let hasSideEffects = 0;296 let mayLoad = 0;297 let mayStore = 1;298}299 300// GP: SH301class NDSRVInstSHGP<bits<3> funct3, string opcodestr>302 : RVInst<(outs), (ins GPR:$rs2, simm18_lsb0:$imm17),303 opcodestr, "$rs2, ${imm17}", [], InstFormatOther> {304 bits<17> imm17;305 bits<5> rs2;306 307 let Inst{31} = imm17{16};308 let Inst{30-25} = imm17{9-4};309 let Inst{24-20} = rs2;310 let Inst{19-17} = imm17{13-11};311 let Inst{16-15} = imm17{15-14};312 let Inst{14-12} = funct3;313 let Inst{11-8} = imm17{3-0};314 let Inst{7} = imm17{10};315 let Inst{6-0} = OPC_CUSTOM_1.Value;316 let hasSideEffects = 0;317 let mayLoad = 0;318 let mayStore = 1;319}320 321// GP: SW322class NDSRVInstSWGP<bits<3> funct3, string opcodestr>323 : RVInst<(outs), (ins GPR:$rs2, simm19_lsb00:$imm17),324 opcodestr, "$rs2, ${imm17}", [], InstFormatOther> {325 bits<17> imm17;326 bits<5> rs2;327 328 let Inst{31} = imm17{16};329 let Inst{30-25} = imm17{8-3};330 let Inst{24-20} = rs2;331 let Inst{19-17} = imm17{12-10};332 let Inst{16-15} = imm17{14-13};333 let Inst{14-12} = funct3;334 let Inst{11-9} = imm17{2-0};335 let Inst{8} = imm17{15};336 let Inst{7} = imm17{9};337 let Inst{6-0} = OPC_CUSTOM_1.Value;338 let hasSideEffects = 0;339 let mayLoad = 0;340 let mayStore = 1;341}342 343// GP: SD344class NDSRVInstSDGP<bits<3> funct3, string opcodestr>345 : RVInst<(outs), (ins GPR:$rs2, simm20_lsb000:$imm17),346 opcodestr, "$rs2, ${imm17}", [], InstFormatOther> {347 bits<17> imm17;348 bits<5> rs2;349 350 let Inst{31} = imm17{16};351 let Inst{30-25} = imm17{7-2};352 let Inst{24-20} = rs2;353 let Inst{19-17} = imm17{11-9};354 let Inst{16-15} = imm17{13-12};355 let Inst{14-12} = funct3;356 let Inst{11-10} = imm17{1-0};357 let Inst{9-8} = imm17{15-14};358 let Inst{7} = imm17{8};359 let Inst{6-0} = OPC_CUSTOM_1.Value;360 let hasSideEffects = 0;361 let mayLoad = 0;362 let mayStore = 1;363}364 365class NDSRVInstVSINTLN<bits<5> funct5, string opcodestr>366 : RVInst<(outs VR:$vd), (ins GPRMemZeroOffset:$rs1),367 opcodestr, "$vd, ${rs1}", [], InstFormatR>,368 VLESchedMC {369 bits<5> rs1;370 bits<5> vd;371 372 let Inst{31-26} = 0b000001;373 let Inst{25} = 1;374 let Inst{24-20} = funct5;375 let Inst{19-15} = rs1;376 let Inst{14-12} = 0b100;377 let Inst{11-7} = vd;378 let Inst{6-0} = OPC_CUSTOM_2.Value;379 let hasSideEffects = 0;380 let mayLoad = 1;381 let mayStore = 0;382 let Uses = [VTYPE, VL];383}384 385class NDSRVInstVSINTCvt<bits<5> fucnt5, string opcodestr>386 : RVInst<(outs VR:$vd), (ins VR:$vs, VMaskOp:$vm),387 opcodestr, "$vd, $vs$vm", [], InstFormatR> {388 bits<5> vs;389 bits<5> vd;390 bit vm;391 392 let Inst{31-26} = 0b000000;393 let Inst{25} = vm;394 let Inst{24-20} = vs;395 let Inst{19-15} = fucnt5;396 let Inst{14-12} = 0b100;397 let Inst{11-7} = vd;398 let Inst{6-0} = OPC_CUSTOM_2.Value;399 let hasSideEffects = 0;400 let mayLoad = 0;401 let mayStore = 0;402 let Uses = [FRM, VL, VTYPE];403 let RVVConstraint = VMConstraint;404}405 406class NDSRVInstBFHCvt<bits<7> funct7, bits<5> rs1val, DAGOperand rdty,407 DAGOperand rs2ty, string opcodestr>408 : RVInstR<funct7, 0b100, OPC_CUSTOM_2, (outs rdty:$rd),409 (ins rs2ty:$rs2), opcodestr, "$rd, $rs2"> {410 let rs1 = rs1val;411 let hasSideEffects = 0;412 let mayLoad = 0;413 let mayStore = 0;414 let mayRaiseFPException = 1;415}416 417class NDSRVInstVFPMAD<bits<6> funct6, string opcodestr>418 : RVInst<(outs VR:$vd), (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm),419 opcodestr # "." # "vf", "$vd, $rs1, $vs2$vm", [], InstFormatR>,420 SchedBinaryMC<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF"> {421 bits<5> vs2;422 bits<5> rs1;423 bits<5> vd;424 bit vm;425 426 let Inst{31-26} = funct6;427 let Inst{25} = vm;428 let Inst{24-20} = vs2;429 let Inst{19-15} = rs1;430 let Inst{14-12} = 0b100;431 let Inst{11-7} = vd;432 let Inst{6-0} = OPC_CUSTOM_2.Value;433 let hasSideEffects = 0;434 let mayLoad = 0;435 let mayStore = 0;436 437 let RVVConstraint = VMConstraint;438}439 440class NDSRVInstVD4DOT<bits<6> funct6, string opcodestr>441 : RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2, VMaskOp:$vm),442 opcodestr # "." # "vv", "$vd, $vs1, $vs2$vm", [], InstFormatR>,443 SchedBinaryMC<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV"> {444 bits<5> vs2;445 bits<5> vs1;446 bits<5> vd;447 bit vm;448 449 let Inst{31-26} = funct6;450 let Inst{25} = vm;451 let Inst{24-20} = vs2;452 let Inst{19-15} = vs1;453 let Inst{14-12} = 0b100;454 let Inst{11-7} = vd;455 let Inst{6-0} = OPC_CUSTOM_2.Value;456 let hasSideEffects = 0;457 let mayLoad = 0;458 let mayStore = 0;459 460 let RVVConstraint = VMConstraint;461}462 463class NDSRVInstVBFHCvt<bits<5> vs1, string opcodestr>464 : RVInst<(outs VR:$vd), (ins VR:$vs2),465 opcodestr, "$vd, $vs2", [], InstFormatR> {466 bits<5> vs2;467 bits<5> vd;468 469 let Inst{31-25} = 0b0000000;470 let Inst{24-20} = vs2;471 let Inst{19-15} = vs1;472 let Inst{14-12} = 0b100;473 let Inst{11-7} = vd;474 let Inst{6-0} = OPC_CUSTOM_2.Value;475 let hasSideEffects = 0;476 let mayLoad = 0;477 let mayStore = 0;478 479 let Uses = [VL, VTYPE];480}481 482class NDSRVInstVLN<bits<5> funct5, string opcodestr>483 : RVInst<(outs VR:$vd), (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm),484 opcodestr, "$vd, ${rs1}$vm", [], InstFormatR>,485 VLESchedMC {486 bits<5> rs1;487 bits<5> vd;488 bit vm;489 490 let Inst{31-26} = 0b000001;491 let Inst{25} = vm;492 let Inst{24-20} = funct5;493 let Inst{19-15} = rs1;494 let Inst{14-12} = 0b100;495 let Inst{11-7} = vd;496 let Inst{6-0} = OPC_CUSTOM_2.Value;497 let hasSideEffects = 0;498 let mayLoad = 1;499 let mayStore = 0;500 501 let Uses = [VTYPE, VL];502 let RVVConstraint = VMConstraint;503}504 505class VPseudoVLN8NoMask<VReg RetClass, bit U> :506 RISCVVPseudo<(outs RetClass:$rd),507 (ins RetClass:$dest,508 GPRMemZeroOffset:$rs1,509 AVL:$vl, sew:$sew, vec_policy:$policy), []>,510 RISCVNDSVLN</*Masked*/0, /*Unsigned*/U, !logtwo(8), VLMul> {511 let mayLoad = 1;512 let mayStore = 0;513 let hasSideEffects = 0;514 let HasVLOp = 1;515 let HasSEWOp = 1;516 let HasVecPolicyOp = 1;517 let Constraints = "$rd = $dest";518}519 520class VPseudoVLN8Mask<VReg RetClass, bit U> :521 RISCVVPseudo<(outs GetVRegNoV0<RetClass>.R:$rd),522 (ins GetVRegNoV0<RetClass>.R:$passthru,523 GPRMemZeroOffset:$rs1,524 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy),525 []>,526 RISCVNDSVLN</*Masked*/1, /*Unsigned*/U, !logtwo(8), VLMul> {527 let mayLoad = 1;528 let mayStore = 0;529 let hasSideEffects = 0;530 let HasVLOp = 1;531 let HasSEWOp = 1;532 let HasVecPolicyOp = 1;533 let UsesMaskPolicy = 1;534 let Constraints = "$rd = $passthru";535}536 537//===----------------------------------------------------------------------===//538// Multiclass539//===----------------------------------------------------------------------===//540 541multiclass VPseudoVWCVT_S_BF16 {542 defvar constraint = "@earlyclobber $rd";543 foreach m = MxListFW in {544 let VLMul = m.value, SEW=16 in545 def "_" # m.MX : VPseudoUnaryNoMask<m.wvrclass, m.vrclass, constraint>,546 SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX, 16,547 forcePassthruRead=true>;548 }549}550 551multiclass VPseudoVNCVT_BF16_S {552 defvar constraint = "@earlyclobber $rd";553 foreach m = MxListFW in {554 let VLMul = m.value, SEW=16 in555 def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.wvrclass,556 constraint>,557 SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16,558 forcePassthruRead=true>;559 }560}561 562multiclass VPatConversionS_BF16<string intrinsic, string instruction> {563 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {564 defvar fvti = fvtiToFWti.Vti;565 defvar fwti = fvtiToFWti.Wti;566 let Predicates = [HasVendorXAndesVBFHCvt] in567 def : VPatUnaryNoMask<intrinsic, instruction, "BF16",568 fwti.Vector, fvti.Vector,569 fvti.Log2SEW, fvti.LMul,570 fwti.RegClass, fvti.RegClass>;571 }572}573 574multiclass VPatConversionBF16_S<string intrinsic, string instruction> {575 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {576 defvar fvti = fvtiToFWti.Vti;577 defvar fwti = fvtiToFWti.Wti;578 let Predicates = [HasVendorXAndesVBFHCvt] in579 def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "S",580 fvti.Vector, fwti.Vector,581 fvti.Log2SEW, fvti.LMul,582 fvti.RegClass, fwti.RegClass>;583 }584}585 586multiclass VPseudoVLN8<bit U> {587 foreach lmul = MxSet<8>.m in {588 defvar LInfo = lmul.MX;589 defvar vreg = lmul.vrclass;590 let VLMul = lmul.value in {591 def "_V_" # LInfo :592 VPseudoVLN8NoMask<vreg, U>,593 VLESched<LInfo>;594 def "_V_" # LInfo # "_MASK" :595 VPseudoVLN8Mask<vreg, U>,596 RISCVMaskedPseudo<MaskIdx=2>,597 VLESched<LInfo>;598 }599 }600}601 602let fprclass = !cast<RegisterClass>("FPR32") in603def SCALAR_F16_FPR32 : FPR_Info<16>;604 605let hasSideEffects = 0 in606multiclass VPseudoVFPMAD_VF_RM {607 foreach m = SCALAR_F16_FPR32.MxList in {608 defm "" : VPseudoBinaryV_VF_RM<m, SCALAR_F16_FPR32, 0>,609 SchedBinary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF",610 m.MX, SCALAR_F16_FPR32.SEW, forcePassthruRead=true>;611 }612}613 614multiclass VPatVFPMADBinaryV_VX_RM<string intrinsic, string instruction,615 list<VTypeInfo> vtilist> {616 foreach vti = vtilist in {617 defvar kind = "V"#vti.ScalarSuffix;618 defm : VPatBinaryRoundingMode<intrinsic,619 instruction#"_"#kind#"_"#vti.LMul.MX,620 vti.Vector, vti.Vector, f32, vti.Mask,621 vti.Log2SEW, vti.RegClass,622 vti.RegClass, FPR32>;623 }624}625 626multiclass VPseudoVD4DOT_VV {627 foreach m = [V_MF2, V_M1, V_M2, V_M4, V_M8] in {628 defm "" : VPseudoBinaryV_VV<m>,629 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,630 forcePassthruRead=true>;631 }632}633 634multiclass VPatTernaryVD4DOT_VV<string intrinsic, string instruction,635 list<VTypeInfoToWide> vtilist> {636 foreach vtiToWti = vtilist in {637 defvar vti = vtiToWti.Vti;638 defvar wti = vtiToWti.Wti;639 let Predicates = GetVTypePredicates<wti>.Predicates in640 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",641 wti.Vector, vti.Vector, vti.Vector,642 wti.Mask, wti.Log2SEW, vti.LMul,643 wti.RegClass, vti.RegClass, vti.RegClass>;644 }645}646 647//===----------------------------------------------------------------------===//648// XAndesPerf649//===----------------------------------------------------------------------===//650 651let DecoderNamespace = "XAndes" in {652 653let Predicates = [HasVendorXAndesPerf] in {654def NDS_BBC : NDSRVInstBB<0, "nds.bbc">;655def NDS_BBS : NDSRVInstBB<1, "nds.bbs">;656 657def NDS_BEQC : NDSRVInstBC<0b101, "nds.beqc">;658def NDS_BNEC : NDSRVInstBC<0b110, "nds.bnec">;659 660def NDS_BFOS : NDSRVInstBFO<0b011, "nds.bfos">;661def NDS_BFOZ : NDSRVInstBFO<0b010, "nds.bfoz">;662 663def NDS_LEA_H : NDSRVInstLEA<0b0000101, "nds.lea.h">;664def NDS_LEA_W : NDSRVInstLEA<0b0000110, "nds.lea.w">;665def NDS_LEA_D : NDSRVInstLEA<0b0000111, "nds.lea.d">;666 667let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in668def NDS_ADDIGP : NDSRVInstLBGP<0b01, "nds.addigp">;669 670def NDS_LBGP : NDSRVInstLBGP<0b00, "nds.lbgp">;671def NDS_LBUGP : NDSRVInstLBGP<0b10, "nds.lbugp">;672def NDS_LHGP : NDSRVInstLHGP<0b001, "nds.lhgp">;673def NDS_LHUGP : NDSRVInstLHGP<0b101, "nds.lhugp">;674def NDS_LWGP : NDSRVInstLWGP<0b010, "nds.lwgp">;675 676def NDS_SBGP : NDSRVInstSBGP<0b11, "nds.sbgp">;677def NDS_SHGP : NDSRVInstSHGP<0b000, "nds.shgp">;678def NDS_SWGP : NDSRVInstSWGP<0b100, "nds.swgp">;679 680def NDS_FFB : NDSRVInstRR<0b0010000, "nds.ffb">;681def NDS_FFZMISM : NDSRVInstRR<0b0010001, "nds.ffzmism">;682def NDS_FFMISM : NDSRVInstRR<0b0010010, "nds.ffmism">;683def NDS_FLMISM : NDSRVInstRR<0b0010011, "nds.flmism">;684} // Predicates = [HasVendorXAndesPerf]685 686let Predicates = [HasVendorXAndesPerf, IsRV64] in {687def NDS_LEA_B_ZE : NDSRVInstLEA<0b0001000, "nds.lea.b.ze">;688def NDS_LEA_H_ZE : NDSRVInstLEA<0b0001001, "nds.lea.h.ze">;689def NDS_LEA_W_ZE : NDSRVInstLEA<0b0001010, "nds.lea.w.ze">;690def NDS_LEA_D_ZE : NDSRVInstLEA<0b0001011, "nds.lea.d.ze">;691 692def NDS_LWUGP : NDSRVInstLWGP<0b110, "nds.lwugp">;693def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">;694 695def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">;696} // Predicates = [HasVendorXAndesPerf, IsRV64]697 698//===----------------------------------------------------------------------===//699// XAndesBFHCvt700//===----------------------------------------------------------------------===//701 702let Predicates = [HasVendorXAndesBFHCvt] in {703def NDS_FCVT_S_BF16 : NDSRVInstBFHCvt<0b0000000, 0b00010,704 FPR32, FPR16, "nds.fcvt.s.bf16">,705 Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;706def NDS_FCVT_BF16_S : NDSRVInstBFHCvt<0b0000000, 0b00011,707 FPR16, FPR32, "nds.fcvt.bf16.s">,708 Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;709}710 711//===----------------------------------------------------------------------===//712// XAndesVBFHCvt713//===----------------------------------------------------------------------===//714 715let Predicates = [HasVendorXAndesVBFHCvt], Constraints = "@earlyclobber $vd",716 mayRaiseFPException = true in {717let RVVConstraint = VS2Constraint, DestEEW = EEWSEWx2 in718def NDS_VFWCVT_S_BF16 : NDSRVInstVBFHCvt<0b00000, "nds.vfwcvt.s.bf16">;719let Uses = [FRM, VL, VTYPE] in720def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b00001, "nds.vfncvt.bf16.s">;721}722 723//===----------------------------------------------------------------------===//724// XAndesVSIntH725//===----------------------------------------------------------------------===//726 727let Predicates = [HasVendorXAndesVSIntH] in {728 def NDS_VFWCVT_F_N : NDSRVInstVSINTCvt<0b00100, "nds.vfwcvt.f.n.v">;729 def NDS_VFWCVT_F_NU : NDSRVInstVSINTCvt<0b00101, "nds.vfwcvt.f.nu.v">;730 def NDS_VFWCVT_F_B : NDSRVInstVSINTCvt<0b00110, "nds.vfwcvt.f.b.v">;731 def NDS_VFWCVT_F_BU : NDSRVInstVSINTCvt<0b00111, "nds.vfwcvt.f.bu.v">;732 def NDS_VLE4_V : NDSRVInstVSINTLN<0b00000, "nds.vle4.v">;733}734 735//===----------------------------------------------------------------------===//736// XAndesVSIntLoad737//===----------------------------------------------------------------------===//738 739let Predicates = [HasVendorXAndesVSIntLoad] in {740def NDS_VLN8_V : NDSRVInstVLN<0b00010, "nds.vln8.v">;741def NDS_VLNU8_V : NDSRVInstVLN<0b00011, "nds.vlnu8.v">;742}743 744//===----------------------------------------------------------------------===//745// XAndesVPackFPH746//===----------------------------------------------------------------------===//747 748let Predicates = [HasVendorXAndesVPackFPH],749 Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {750def NDS_VFPMADT_VF : NDSRVInstVFPMAD<0b000010, "nds.vfpmadt">;751def NDS_VFPMADB_VF : NDSRVInstVFPMAD<0b000011, "nds.vfpmadb">;752}753 754//===----------------------------------------------------------------------===//755// XAndesVDot756//===----------------------------------------------------------------------===//757 758let Predicates = [HasVendorXAndesVDot], Uses = [VL, VTYPE] in {759def NDS_VD4DOTS_VV : NDSRVInstVD4DOT<0b000100, "nds.vd4dots">;760def NDS_VD4DOTU_VV : NDSRVInstVD4DOT<0b000111, "nds.vd4dotu">;761def NDS_VD4DOTSU_VV : NDSRVInstVD4DOT<0b000101, "nds.vd4dotsu">;762}763} // DecoderNamespace = "XAndes"764 765//===----------------------------------------------------------------------===//766// Pseudo-instructions and codegen patterns767//===----------------------------------------------------------------------===//768 769class NDS_BBPat<CondCode Cond, NDSRVInstBB Inst>770 : Pat<(riscv_brcc (and(XLenVT GPR:$rs1), PowerOf2:$mask), 0, Cond,771 bb:$imm10),772 (Inst GPR:$rs1, (Log2 PowerOf2:$mask), bare_simm11_lsb0:$imm10)>;773 774class NDS_BCPat<CondCode Cond, NDSRVInstBC Inst>775 : Pat<(riscv_brcc (XLenVT GPR:$rs1), uimm7:$cimm, Cond, bb:$imm10),776 (Inst GPR:$rs1, uimm7:$cimm, bare_simm11_lsb0:$imm10)>;777 778defm CC_UImmLog2XLen_NDS : SelectCC_GPR_riirr<GPR, uimmlog2xlen>;779defm CC_UImm7_NDS : SelectCC_GPR_riirr<GPR, uimm7>;780 781class SelectNDS_BB<CondCode Cond>782 : Pat<(riscv_selectcc_frag:$cc (and(XLenVT GPR:$lhs), PowerOf2:$mask), 0,783 Cond, (XLenVT GPR:$truev), GPR:$falsev),784 (Select_GPR_Using_CC_UImmLog2XLen_NDS GPR:$lhs, (Log2 PowerOf2:$mask),785 (IntCCtoRISCVCC $cc), GPR:$truev, GPR:$falsev)>;786 787class SelectNDS_BC<CondCode Cond>788 : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), uimm7:$cimm, Cond,789 (XLenVT GPR:$truev), GPR:$falsev),790 (Select_GPR_Using_CC_UImm7_NDS GPR:$lhs, uimm7:$cimm,791 (IntCCtoRISCVCC $cc), GPR:$truev, GPR:$falsev)>;792 793let Predicates = [HasVendorXAndesPerf] in {794 795def : NDS_BBPat<SETEQ, NDS_BBC>;796def : NDS_BBPat<SETNE, NDS_BBS>;797 798def : SelectNDS_BB<SETEQ>;799def : SelectNDS_BB<SETNE>;800 801def : NDS_BCPat<SETEQ, NDS_BEQC>;802def : NDS_BCPat<SETNE, NDS_BNEC>;803 804def : SelectNDS_BC<SETEQ>;805def : SelectNDS_BC<SETNE>;806 807def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (NDS_BFOS GPR:$rs1, 15, 0)>;808def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (NDS_BFOS GPR:$rs1, 7, 0)>;809def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (NDS_BFOS GPR:$rs1, 0, 0)>;810 811defm : ShxAddPat<1, NDS_LEA_H>;812defm : ShxAddPat<2, NDS_LEA_W>;813defm : ShxAddPat<3, NDS_LEA_D>;814 815def : CSImm12MulBy4Pat<NDS_LEA_W>;816def : CSImm12MulBy8Pat<NDS_LEA_D>;817} // Predicates = [HasVendorXAndesPerf]818 819let Predicates = [HasVendorXAndesPerf, IsRV64] in {820 821defm : ADD_UWPat<NDS_LEA_B_ZE>;822 823defm : ShxAdd_UWPat<1, NDS_LEA_H_ZE>;824defm : ShxAdd_UWPat<2, NDS_LEA_W_ZE>;825defm : ShxAdd_UWPat<3, NDS_LEA_D_ZE>;826 827defm : Sh1Add_UWPat<NDS_LEA_H_ZE>;828defm : Sh2Add_UWPat<NDS_LEA_W_ZE>;829defm : Sh3Add_UWPat<NDS_LEA_D_ZE>;830 831def : Sh1AddPat<NDS_LEA_H_ZE>;832def : Sh2AddPat<NDS_LEA_W_ZE>;833def : Sh3AddPat<NDS_LEA_D_ZE>;834} // Predicates = [HasVendorXAndesPerf, IsRV64]835 836let Predicates = [HasVendorXAndesBFHCvt] in {837def : Pat<(fpextend (bf16 FPR16:$rs)),838 (NDS_FCVT_S_BF16 (bf16 FPR16:$rs))>;839def : Pat<(bf16 (fpround FPR32:$rs)),840 (NDS_FCVT_BF16_S FPR32:$rs)>;841 842let isCodeGenOnly = 1 in {843def NDS_FMV_BF16_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR16, GPR, "fmv.w.x">,844 Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;845def NDS_FMV_X_BF16 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR16, "fmv.x.w">,846 Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;847}848 849def : Pat<(riscv_nds_fmv_bf16_x GPR:$src), (NDS_FMV_BF16_X GPR:$src)>;850def : Pat<(riscv_nds_fmv_x_anyextbf16 (bf16 FPR16:$src)),851 (NDS_FMV_X_BF16 (bf16 FPR16:$src))>;852} // Predicates = [HasVendorXAndesBFHCvt]853 854// Use flh/fsh to load/store bf16 if zfh is enabled.855let Predicates = [HasStdExtZfh, HasVendorXAndesBFHCvt] in {856def : LdPat<load, FLH, bf16>;857def : StPat<store, FSH, FPR16, bf16>;858} // Predicates = [HasStdExtZfh, HasVendorXAndesBFHCvt]859 860let Predicates = [HasVendorXAndesVBFHCvt] in {861defm PseudoNDS_VFWCVT_S_BF16 : VPseudoVWCVT_S_BF16;862defm PseudoNDS_VFNCVT_BF16_S : VPseudoVNCVT_BF16_S;863} // Predicates = [HasVendorXAndesVBFHCvt]864 865defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16",866 "PseudoNDS_VFWCVT_S">;867defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s",868 "PseudoNDS_VFNCVT_BF16">;869 870let Predicates = [HasVendorXAndesVSIntLoad] in {871defm PseudoNDS_VLN8 : VPseudoVLN8<0>;872defm PseudoNDS_VLNU8 : VPseudoVLN8<1>;873} // Predicates = [HasVendorXAndesVSIntLoad]874 875let Predicates = [HasVendorXAndesVPackFPH],876 mayRaiseFPException = true in {877defm PseudoNDS_VFPMADT : VPseudoVFPMAD_VF_RM;878defm PseudoNDS_VFPMADB : VPseudoVFPMAD_VF_RM;879} // Predicates = [HasVendorXAndesVPackFPH]880 881defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT",882 AllFP16Vectors>;883defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB",884 AllFP16Vectors>;885 886let Predicates = [HasVendorXAndesVDot] in {887defm PseudoNDS_VD4DOTS : VPseudoVD4DOT_VV;888defm PseudoNDS_VD4DOTU : VPseudoVD4DOT_VV;889defm PseudoNDS_VD4DOTSU : VPseudoVD4DOT_VV;890}891 892defset list<VTypeInfoToWide> AllQuadWidenableVD4DOTVectors = {893 def : VTypeInfoToWide<VI8MF2, VI32MF2>;894 def : VTypeInfoToWide<VI8M1, VI32M1>;895 def : VTypeInfoToWide<VI8M2, VI32M2>;896 def : VTypeInfoToWide<VI8M4, VI32M4>;897 def : VTypeInfoToWide<VI8M8, VI32M8>;898 def : VTypeInfoToWide<VI16M1, VI64M1>;899 def : VTypeInfoToWide<VI16M2, VI64M2>;900 def : VTypeInfoToWide<VI16M4, VI64M4>;901 def : VTypeInfoToWide<VI16M8, VI64M8>;902}903 904defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS",905 AllQuadWidenableVD4DOTVectors>;906defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU",907 AllQuadWidenableVD4DOTVectors>;908defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU",909 AllQuadWidenableVD4DOTVectors>;910 911//===----------------------------------------------------------------------===//912// Pseudo-instructions for SFB (Short Forward Branch)913//===----------------------------------------------------------------------===//914 915let Predicates = [HasShortForwardBranchIALU], hasSideEffects = 0,916 mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in {917def PseudoCCNDS_BFOS : Pseudo<(outs GPR:$dst),918 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,919 GPR:$falsev, GPR:$rs1,920 uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,921 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,922 ReadSFBALU]>;923def PseudoCCNDS_BFOZ : Pseudo<(outs GPR:$dst),924 (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,925 GPR:$falsev, GPR:$rs1,926 uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>,927 Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,928 ReadSFBALU]>;929}930