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1//===-- RISCVInstrInfoXCV.td - CORE-V instructions ---------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the vendor extensions defined by Core-V extensions.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Operand and SDNode transformation definitions.15//===----------------------------------------------------------------------===//16 17def CVrrAsmOperand : AsmOperandClass {18 let Name = "RegReg";19 let ParserMethod = "parseRegReg";20}21 22def CVrr : Operand<i32>,23 ComplexPattern<i32, 2, "SelectAddrRegReg",[]> {24 let ParserMatchClass = CVrrAsmOperand;25 let PrintMethod = "printRegReg";26 let MIOperandInfo = (ops GPR:$base, GPR:$offset);27}28 29def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;30def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;31def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;32 33def CV_LO5: SDNodeXForm<imm, [{34 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1f, SDLoc(N),35 N->getValueType(0));36}]>;37 38def CV_HI5: SDNodeXForm<imm, [{39 return CurDAG->getTargetConstant(N->getZExtValue() >> 5, SDLoc(N),40 N->getValueType(0));41}]>;42 43def powerOf2Minus1 : ImmLeaf<XLenVT, [{ return isPowerOf2_32(Imm+1); }]>;44def trailing1sPlus1 : SDNodeXForm<imm, [{45 return CurDAG->getTargetConstant(46 llvm::countr_one(N->getZExtValue()) + 1,47 SDLoc(N), N->getValueType(0));48}]>;49 50//===----------------------------------------------------------------------===//51// Instruction Class Templates52//===----------------------------------------------------------------------===//53 54let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {55 class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,56 string opcodestr, string argstr>57 : RVInstIBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {58 bits<5> is3;59 bits<5> is2;60 let Inst{31-30} = funct2;61 let Inst{29-25} = is3;62 let Inst{24-20} = is2;63 }64 65 class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,66 Operand i3type = uimm5>67 : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),68 (ins GPR:$rs1, i3type:$is3, uimm5:$is2),69 opcodestr, "$rd, $rs1, $is3, $is2">;70 71 class CVBitManipRR<bits<7> funct7, string opcodestr>72 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),73 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;74 75 class CVBitManipR<bits<7> funct7, string opcodestr>76 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),77 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {78 let rs2 = 0b00000;79 }80} // hasSideEffects = 0, mayLoad = 0, mayStore = 081 82class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr>83 : RVInstR<funct7, funct3, OPC_CUSTOM_1,84 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),85 opcodestr, "$rd, $rs1, $rs2"> {86 let Constraints = "$rd = $rd_wb";87 let hasSideEffects = 0;88 let mayLoad = 0;89 let mayStore = 0;90}91 92class CVInstMacMulN<bits<2> funct2, bits<3> funct3, dag outs, dag ins,93 string opcodestr>94 : RVInstRBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr,95 "$rd, $rs1, $rs2, $imm5"> {96 bits<5> imm5;97 98 let Inst{31-30} = funct2;99 let Inst{29-25} = imm5;100 101 let hasSideEffects = 0;102 let mayLoad = 0;103 let mayStore = 0;104}105 106class CVInstMacN<bits<2> funct2, bits<3> funct3, string opcodestr>107 : CVInstMacMulN<funct2, funct3, (outs GPR:$rd_wb),108 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr> {109 let Constraints = "$rd = $rd_wb";110}111 112class CVInstMulN<bits<2> funct2, bits<3> funct3, string opcodestr>113 : CVInstMacMulN<funct2, funct3, (outs GPR:$rd),114 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;115 116let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {117 class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>118 : RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),119 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,120 "$rd, $rs1, $rs2, $imm5"> {121 bits<5> imm5;122 123 let Inst{31-30} = funct2;124 let Inst{29-25} = imm5;125 }126 127 class CVInstAluRR<bits<7> funct7, bits<3> funct3, string opcodestr>128 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),129 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;130 131 class CVInstAluRRNR<bits<7> funct7, bits<3> funct3, string opcodestr>132 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd_wb),133 (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {134 let Constraints = "$rd = $rd_wb";135 }136 137 class CVInstAluRI<bits<7> funct7, bits<3> funct3, string opcodestr>138 : RVInstIBase<funct3, OPC_CUSTOM_1, (outs GPR:$rd),139 (ins GPR:$rs1, uimm5:$imm5), opcodestr,140 "$rd, $rs1, $imm5"> {141 bits<5> imm5;142 143 let Inst{31-25} = funct7;144 let Inst{24-20} = imm5;145 }146 147 class CVInstAluR<bits<7> funct7, bits<3> funct3, string opcodestr>148 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins GPR:$rs1),149 opcodestr, "$rd, $rs1"> {150 let rs2 = 0b00000;151 }152} // hasSideEffects = 0, mayLoad = 0, mayStore = 0153 154class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,155 RISCVOpcode opcode, dag outs,156 dag ins, string opcodestr, string argstr>157 : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {158 let Inst{31-27} = funct5;159 let Inst{26} = F;160 let Inst{25} = funct1;161}162 163class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,164 dag outs, dag ins, string opcodestr, string argstr>165 : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {166 bits<6> imm6;167 168 let Inst{31-27} = funct5;169 let Inst{26} = F;170 let Inst{25} = imm6{0}; // funct1 unused171 let Inst{24-20} = imm6{5-1};172}173 174let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {175class CVSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,176 string opcodestr>177 : CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd),178 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;179 180class CVSIMDRRWb<bits<5> funct5, bit F, bit funct1, bits<3> funct3,181 string opcodestr>182 : CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd_wb),183 (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {184 let Constraints = "$rd = $rd_wb";185}186 187class CVSIMDRI<bits<5> funct5, bit F, bits<3> funct3, string opcodestr,188 Operand immtype = simm6>189 : CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM_3, (outs GPR:$rd),190 (ins GPR:$rs1, immtype:$imm6), opcodestr, "$rd, $rs1, $imm6">;191 192class CVSIMDRIWb<bits<5> funct5, bit F, bits<3> funct3, string opcodestr,193 Operand immtype = simm6>194 : CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM_3,195 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, immtype:$imm6),196 opcodestr, "$rd, $rs1, $imm6"> {197 let Constraints = "$rd = $rd_wb";198}199 200class CVSIMDRU<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>201 : CVSIMDRI<funct5, F, funct3, opcodestr, uimm6>;202 203class CVSIMDRUWb<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>204 : CVSIMDRIWb<funct5, F, funct3, opcodestr, uimm6>;205 206class CVSIMDR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,207 string opcodestr>208 : CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd),209 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {210 let rs2 = 0b00000;211}212} // hasSideEffects = 0, mayLoad = 0, mayStore = 0213 214multiclass CVSIMDBinarySigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {215 def CV_ # NAME # _H : CVSIMDRR<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;216 def CV_ # NAME # _B : CVSIMDRR<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;217 def CV_ # NAME # _SC_H : CVSIMDRR<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;218 def CV_ # NAME # _SC_B : CVSIMDRR<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;219 def CV_ # NAME # _SCI_H : CVSIMDRI<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;220 def CV_ # NAME # _SCI_B : CVSIMDRI<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;221}222 223multiclass CVSIMDBinaryUnsigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {224 def CV_ # NAME # _H : CVSIMDRR<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;225 def CV_ # NAME # _B : CVSIMDRR<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;226 def CV_ # NAME # _SC_H : CVSIMDRR<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;227 def CV_ # NAME # _SC_B : CVSIMDRR<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;228 def CV_ # NAME # _SCI_H : CVSIMDRU<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;229 def CV_ # NAME # _SCI_B : CVSIMDRU<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;230}231 232multiclass CVSIMDShift<bits<5> funct5, bit F, bit funct1, string mnemonic> {233 def CV_ # NAME # _H : CVSIMDRR<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;234 def CV_ # NAME # _B : CVSIMDRR<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;235 def CV_ # NAME # _SC_H : CVSIMDRR<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;236 def CV_ # NAME # _SC_B : CVSIMDRR<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;237 def CV_ # NAME # _SCI_H : CVSIMDRI<funct5, F, 0b110, "cv." # mnemonic # ".sci.h", uimm4>;238 def CV_ # NAME # _SCI_B : CVSIMDRI<funct5, F, 0b111, "cv." # mnemonic # ".sci.b", uimm3>;239}240 241multiclass CVSIMDBinarySignedWb<bits<5> funct5, bit F, bit funct1, string mnemonic> {242 def CV_ # NAME # _H : CVSIMDRRWb<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;243 def CV_ # NAME # _B : CVSIMDRRWb<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;244 def CV_ # NAME # _SC_H : CVSIMDRRWb<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;245 def CV_ # NAME # _SC_B : CVSIMDRRWb<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;246 def CV_ # NAME # _SCI_H : CVSIMDRIWb<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;247 def CV_ # NAME # _SCI_B : CVSIMDRIWb<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;248}249 250multiclass CVSIMDBinaryUnsignedWb<bits<5> funct5, bit F, bit funct1, string mnemonic> {251 def CV_ # NAME # _H : CVSIMDRRWb<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;252 def CV_ # NAME # _B : CVSIMDRRWb<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;253 def CV_ # NAME # _SC_H : CVSIMDRRWb<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;254 def CV_ # NAME # _SC_B : CVSIMDRRWb<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;255 def CV_ # NAME # _SCI_H : CVSIMDRUWb<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;256 def CV_ # NAME # _SCI_B : CVSIMDRUWb<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;257}258 259class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,260 string opcodestr, string argstr>261 : RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {262 bits<5> imm5;263 let rs2 = imm5;264 let isBranch = 1;265 let isTerminator = 1;266 let hasSideEffects = 0;267 let mayLoad = 0;268 let mayStore = 0;269}270 271let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {272class CVLoad_ri_inc<bits<3> funct3, string opcodestr>273 : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),274 (ins GPRMem:$rs1, simm12_lo:$imm12),275 opcodestr, "$rd, (${rs1}), ${imm12}"> {276 let Constraints = "$rs1_wb = $rs1";277}278 279class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>280 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb),281 (ins GPRMem:$rs1, GPR:$rs2),282 opcodestr, "$rd, (${rs1}), ${rs2}"> {283 let Constraints = "$rs1_wb = $rs1";284}285 286class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>287 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),288 (ins (CVrr $rs1, $rs2):$addr),289 opcodestr, "$rd, $addr">;290} // hasSideEffects = 0, mayLoad = 1, mayStore = 0291 292let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {293class CVStore_ri_inc<bits<3> funct3, string opcodestr>294 : RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),295 (ins GPR:$rs2, GPR:$rs1, simm12_lo:$imm12),296 opcodestr, "$rs2, (${rs1}), ${imm12}"> {297 let Constraints = "$rs1_wb = $rs1";298}299 300class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, string opcodestr>301 : RVInst<(outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3), opcodestr,302 "$rs2, (${rs1}), ${rs3}", [], InstFormatOther> {303 bits<5> rs3;304 bits<5> rs2;305 bits<5> rs1;306 307 let Inst{31-25} = funct7;308 let Inst{24-20} = rs2;309 let Inst{19-15} = rs1;310 let Inst{14-12} = funct3;311 let Inst{11-7} = rs3;312 let Inst{6-0} = OPC_CUSTOM_1.Value;313 let Constraints = "$rs1_wb = $rs1";314}315 316 317class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>318 : RVInst<(outs), (ins GPR:$rs2, (CVrr $rs1, $rs3):$addr), opcodestr,319 "$rs2, $addr", [], InstFormatOther> {320 bits<5> rs1;321 bits<5> rs2;322 bits<5> rs3;323 324 let Inst{31-25} = funct7;325 let Inst{24-20} = rs2;326 let Inst{19-15} = rs1;327 let Inst{14-12} = funct3;328 let Inst{11-7} = rs3;329 let Inst{6-0} = OPC_CUSTOM_1.Value;330}331} // hasSideEffects = 0, mayLoad = 0, mayStore = 1332 333class CVLoad_ri<bits<3> funct3, string opcodestr>334 : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),335 (ins GPRMem:$rs1, simm12_lo:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;336 337//===----------------------------------------------------------------------===//338// Instructions339//===----------------------------------------------------------------------===//340 341let DecoderNamespace = "XCV" in {342 343let Predicates = [HasVendorXCVbitmanip, IsRV32] in {344 def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;345 def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;346 347 def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;348 def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;349 def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;350 351 def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;352 def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;353 354 let Constraints = "$rd = $rd_wb" in {355 def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),356 (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),357 "cv.insert", "$rd, $rs1, $is3, $is2">;358 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in359 def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),360 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),361 "cv.insertr", "$rd, $rs1, $rs2">;362 }363 364 def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;365 def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;366 367 def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;368 def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;369 def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;370 def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;371 def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">;372} // Predicates = [HasVendorXCVbitmanip, IsRV32]373 374let Predicates = [HasVendorXCVmac, IsRV32] in {375 // 32x32 bit macs376 def CV_MAC : CVInstMac<0b1001000, 0b011, "cv.mac">,377 Sched<[]>;378 def CV_MSU : CVInstMac<0b1001001, 0b011, "cv.msu">,379 Sched<[]>;380 381 // Signed 16x16 bit macs with imm382 def CV_MACSN : CVInstMacN<0b00, 0b110, "cv.macsn">,383 Sched<[]>;384 def CV_MACHHSN : CVInstMacN<0b01, 0b110, "cv.machhsn">,385 Sched<[]>;386 def CV_MACSRN : CVInstMacN<0b10, 0b110, "cv.macsrn">,387 Sched<[]>;388 def CV_MACHHSRN : CVInstMacN<0b11, 0b110, "cv.machhsrn">,389 Sched<[]>;390 391 // Unsigned 16x16 bit macs with imm392 def CV_MACUN : CVInstMacN<0b00, 0b111, "cv.macun">,393 Sched<[]>;394 def CV_MACHHUN : CVInstMacN<0b01, 0b111, "cv.machhun">,395 Sched<[]>;396 def CV_MACURN : CVInstMacN<0b10, 0b111, "cv.macurn">,397 Sched<[]>;398 def CV_MACHHURN : CVInstMacN<0b11, 0b111, "cv.machhurn">,399 Sched<[]>;400 401 // Signed 16x16 bit muls with imm402 def CV_MULSN : CVInstMulN<0b00, 0b100, "cv.mulsn">,403 Sched<[]>;404 def CV_MULHHSN : CVInstMulN<0b01, 0b100, "cv.mulhhsn">,405 Sched<[]>;406 def CV_MULSRN : CVInstMulN<0b10, 0b100, "cv.mulsrn">,407 Sched<[]>;408 def CV_MULHHSRN : CVInstMulN<0b11, 0b100, "cv.mulhhsrn">,409 Sched<[]>;410 411 // Unsigned 16x16 bit muls with imm412 def CV_MULUN : CVInstMulN<0b00, 0b101, "cv.mulun">,413 Sched<[]>;414 def CV_MULHHUN : CVInstMulN<0b01, 0b101, "cv.mulhhun">,415 Sched<[]>;416 def CV_MULURN : CVInstMulN<0b10, 0b101, "cv.mulurn">,417 Sched<[]>;418 def CV_MULHHURN : CVInstMulN<0b11, 0b101, "cv.mulhhurn">,419 Sched<[]>;420} // Predicates = [HasVendorXCVmac, IsRV32]421 422let Predicates = [HasVendorXCValu, IsRV32] in {423 // General ALU Operations424 def CV_ABS : CVInstAluR<0b0101000, 0b011, "cv.abs">,425 Sched<[]>;426 def CV_SLE : CVInstAluRR<0b0101001, 0b011, "cv.sle">,427 Sched<[]>;428 def CV_SLEU : CVInstAluRR<0b0101010, 0b011, "cv.sleu">,429 Sched<[]>;430 def CV_MIN : CVInstAluRR<0b0101011, 0b011, "cv.min">,431 Sched<[]>;432 def CV_MINU : CVInstAluRR<0b0101100, 0b011, "cv.minu">,433 Sched<[]>;434 def CV_MAX : CVInstAluRR<0b0101101, 0b011, "cv.max">,435 Sched<[]>;436 def CV_MAXU : CVInstAluRR<0b0101110, 0b011, "cv.maxu">,437 Sched<[]>;438 def CV_EXTHS : CVInstAluR<0b0110000, 0b011, "cv.exths">,439 Sched<[]>;440 def CV_EXTHZ : CVInstAluR<0b0110001, 0b011, "cv.exthz">,441 Sched<[]>;442 def CV_EXTBS : CVInstAluR<0b0110010, 0b011, "cv.extbs">,443 Sched<[]>;444 def CV_EXTBZ : CVInstAluR<0b0110011, 0b011, "cv.extbz">,445 Sched<[]>;446 447 def CV_CLIP : CVInstAluRI<0b0111000, 0b011, "cv.clip">,448 Sched<[]>;449 def CV_CLIPU : CVInstAluRI<0b0111001, 0b011, "cv.clipu">,450 Sched<[]>;451 def CV_CLIPR : CVInstAluRR<0b0111010, 0b011, "cv.clipr">,452 Sched<[]>;453 def CV_CLIPUR : CVInstAluRR<0b0111011, 0b011, "cv.clipur">,454 Sched<[]>;455 456 def CV_ADDN : CVInstAluRRI<0b00, 0b010, "cv.addn">,457 Sched<[]>;458 def CV_ADDUN : CVInstAluRRI<0b01, 0b010, "cv.addun">,459 Sched<[]>;460 def CV_ADDRN : CVInstAluRRI<0b10, 0b010, "cv.addrn">,461 Sched<[]>;462 def CV_ADDURN : CVInstAluRRI<0b11, 0b010, "cv.addurn">,463 Sched<[]>;464 def CV_SUBN : CVInstAluRRI<0b00, 0b011, "cv.subn">,465 Sched<[]>;466 def CV_SUBUN : CVInstAluRRI<0b01, 0b011, "cv.subun">,467 Sched<[]>;468 def CV_SUBRN : CVInstAluRRI<0b10, 0b011, "cv.subrn">,469 Sched<[]>;470 def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,471 Sched<[]>;472 473 def CV_ADDNR : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,474 Sched<[]>;475 def CV_ADDUNR : CVInstAluRRNR<0b1000001, 0b011, "cv.addunr">,476 Sched<[]>;477 def CV_ADDRNR : CVInstAluRRNR<0b1000010, 0b011, "cv.addrnr">,478 Sched<[]>;479 def CV_ADDURNR : CVInstAluRRNR<0b1000011, 0b011, "cv.addurnr">,480 Sched<[]>;481 def CV_SUBNR : CVInstAluRRNR<0b1000100, 0b011, "cv.subnr">,482 Sched<[]>;483 def CV_SUBUNR : CVInstAluRRNR<0b1000101, 0b011, "cv.subunr">,484 Sched<[]>;485 def CV_SUBRNR : CVInstAluRRNR<0b1000110, 0b011, "cv.subrnr">,486 Sched<[]>;487 def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,488 Sched<[]>;489} // Predicates = [HasVendorXCValu, IsRV32]490 491let Predicates = [HasVendorXCVsimd, IsRV32] in {492 defm ADD : CVSIMDBinarySigned<0b00000, 0, 0, "add">;493 defm SUB : CVSIMDBinarySigned<0b00001, 0, 0, "sub">;494 defm AVG : CVSIMDBinarySigned<0b00010, 0, 0, "avg">;495 defm AVGU : CVSIMDBinaryUnsigned<0b00011, 0, 0, "avgu">;496 defm MIN : CVSIMDBinarySigned<0b00100, 0, 0, "min">;497 defm MINU : CVSIMDBinaryUnsigned<0b00101, 0, 0, "minu">;498 defm MAX : CVSIMDBinarySigned<0b00110, 0, 0, "max">;499 defm MAXU : CVSIMDBinaryUnsigned<0b00111, 0, 0, "maxu">;500 defm SRL : CVSIMDShift<0b01000, 0, 0, "srl">;501 defm SRA : CVSIMDShift<0b01001, 0, 0, "sra">;502 defm SLL : CVSIMDShift<0b01010, 0, 0, "sll">;503 defm OR : CVSIMDBinarySigned<0b01011, 0, 0, "or">;504 defm XOR : CVSIMDBinarySigned<0b01100, 0, 0, "xor">;505 defm AND : CVSIMDBinarySigned<0b01101, 0, 0, "and">;506 507 def CV_ABS_H : CVSIMDR<0b01110, 0, 0, 0b000, "cv.abs.h">;508 def CV_ABS_B : CVSIMDR<0b01110, 0, 0, 0b001, "cv.abs.b">;509 510 // 0b01111xx: UNDEF511 512 defm DOTUP : CVSIMDBinaryUnsigned<0b10000, 0, 0, "dotup">;513 defm DOTUSP : CVSIMDBinarySigned<0b10001, 0, 0, "dotusp">;514 defm DOTSP : CVSIMDBinarySigned<0b10010, 0, 0, "dotsp">;515 defm SDOTUP : CVSIMDBinaryUnsignedWb<0b10011, 0, 0, "sdotup">;516 defm SDOTUSP : CVSIMDBinarySignedWb<0b10100, 0, 0, "sdotusp">;517 defm SDOTSP : CVSIMDBinarySignedWb<0b10101, 0, 0, "sdotsp">;518 519 // 0b10110xx: UNDEF520 521 def CV_EXTRACT_H : CVSIMDRU<0b10111, 0, 0b000, "cv.extract.h">;522 def CV_EXTRACT_B : CVSIMDRU<0b10111, 0, 0b001, "cv.extract.b">;523 def CV_EXTRACTU_H : CVSIMDRU<0b10111, 0, 0b010, "cv.extractu.h">;524 def CV_EXTRACTU_B : CVSIMDRU<0b10111, 0, 0b011, "cv.extractu.b">;525 def CV_INSERT_H : CVSIMDRUWb<0b10111, 0, 0b100, "cv.insert.h">;526 def CV_INSERT_B : CVSIMDRUWb<0b10111, 0, 0b101, "cv.insert.b">;527 528 def CV_SHUFFLE_H : CVSIMDRR<0b11000, 0, 0, 0b000, "cv.shuffle.h">;529 def CV_SHUFFLE_B : CVSIMDRR<0b11000, 0, 0, 0b001, "cv.shuffle.b">;530 def CV_SHUFFLE_SCI_H : CVSIMDRU<0b11000, 0, 0b110, "cv.shuffle.sci.h">;531 def CV_SHUFFLEI0_SCI_B : CVSIMDRU<0b11000, 0, 0b111, "cv.shufflei0.sci.b">;532 533 def CV_SHUFFLEI1_SCI_B : CVSIMDRU<0b11001, 0, 0b111, "cv.shufflei1.sci.b">;534 535 def CV_SHUFFLEI2_SCI_B : CVSIMDRU<0b11010, 0, 0b111, "cv.shufflei2.sci.b">;536 537 def CV_SHUFFLEI3_SCI_B : CVSIMDRU<0b11011, 0, 0b111, "cv.shufflei3.sci.b">;538 539 def CV_SHUFFLE2_H : CVSIMDRRWb<0b11100, 0, 0, 0b000, "cv.shuffle2.h">;540 def CV_SHUFFLE2_B : CVSIMDRRWb<0b11100, 0, 0, 0b001, "cv.shuffle2.b">;541 542 // 0b11101xx: UNDEF543 544 def CV_PACK : CVSIMDRR<0b11110, 0, 0, 0b000, "cv.pack">;545 def CV_PACK_H : CVSIMDRR<0b11110, 0, 1, 0b000, "cv.pack.h">;546 547 def CV_PACKHI_B : CVSIMDRRWb<0b11111, 0, 1, 0b001, "cv.packhi.b">;548 def CV_PACKLO_B : CVSIMDRRWb<0b11111, 0, 0, 0b001, "cv.packlo.b">;549 550 defm CMPEQ : CVSIMDBinarySigned<0b00000, 1, 0, "cmpeq">;551 defm CMPNE : CVSIMDBinarySigned<0b00001, 1, 0, "cmpne">;552 defm CMPGT : CVSIMDBinarySigned<0b00010, 1, 0, "cmpgt">;553 defm CMPGE : CVSIMDBinarySigned<0b00011, 1, 0, "cmpge">;554 defm CMPLT : CVSIMDBinarySigned<0b00100, 1, 0, "cmplt">;555 defm CMPLE : CVSIMDBinarySigned<0b00101, 1, 0, "cmple">;556 defm CMPGTU : CVSIMDBinaryUnsigned<0b00110, 1, 0, "cmpgtu">;557 defm CMPGEU : CVSIMDBinaryUnsigned<0b00111, 1, 0, "cmpgeu">;558 defm CMPLTU : CVSIMDBinaryUnsigned<0b01000, 1, 0, "cmpltu">;559 defm CMPLEU : CVSIMDBinaryUnsigned<0b01001, 1, 0, "cmpleu">;560 561 def CV_CPLXMUL_R : CVSIMDRRWb<0b01010, 1, 0, 0b000, "cv.cplxmul.r">;562 def CV_CPLXMUL_I : CVSIMDRRWb<0b01010, 1, 1, 0b000, "cv.cplxmul.i">;563 def CV_CPLXMUL_R_DIV2 : CVSIMDRRWb<0b01010, 1, 0, 0b010, "cv.cplxmul.r.div2">;564 def CV_CPLXMUL_I_DIV2 : CVSIMDRRWb<0b01010, 1, 1, 0b010, "cv.cplxmul.i.div2">;565 def CV_CPLXMUL_R_DIV4 : CVSIMDRRWb<0b01010, 1, 0, 0b100, "cv.cplxmul.r.div4">;566 def CV_CPLXMUL_I_DIV4 : CVSIMDRRWb<0b01010, 1, 1, 0b100, "cv.cplxmul.i.div4">;567 def CV_CPLXMUL_R_DIV8 : CVSIMDRRWb<0b01010, 1, 0, 0b110, "cv.cplxmul.r.div8">;568 def CV_CPLXMUL_I_DIV8 : CVSIMDRRWb<0b01010, 1, 1, 0b110, "cv.cplxmul.i.div8">;569 570 def CV_CPLXCONJ : CVSIMDR<0b01011, 1, 0, 0b000, "cv.cplxconj">;571 572 // 0b01011xx: UNDEF573 574 def CV_SUBROTMJ : CVSIMDRR<0b01100, 1, 0, 0b000, "cv.subrotmj">;575 def CV_SUBROTMJ_DIV2 : CVSIMDRR<0b01100, 1, 0, 0b010, "cv.subrotmj.div2">;576 def CV_SUBROTMJ_DIV4 : CVSIMDRR<0b01100, 1, 0, 0b100, "cv.subrotmj.div4">;577 def CV_SUBROTMJ_DIV8 : CVSIMDRR<0b01100, 1, 0, 0b110, "cv.subrotmj.div8">;578 579 def CV_ADD_DIV2 : CVSIMDRR<0b01101, 1, 0, 0b010, "cv.add.div2">;580 def CV_ADD_DIV4 : CVSIMDRR<0b01101, 1, 0, 0b100, "cv.add.div4">;581 def CV_ADD_DIV8 : CVSIMDRR<0b01101, 1, 0, 0b110, "cv.add.div8">;582 583 def CV_SUB_DIV2 : CVSIMDRR<0b01110, 1, 0, 0b010, "cv.sub.div2">;584 def CV_SUB_DIV4 : CVSIMDRR<0b01110, 1, 0, 0b100, "cv.sub.div4">;585 def CV_SUB_DIV8 : CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">;586}587 588let Predicates = [HasVendorXCVbi, IsRV32] in {589 // Immediate branching operations590 def CV_BEQIMM : CVInstImmBranch<0b110, (outs),591 (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),592 "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;593 def CV_BNEIMM : CVInstImmBranch<0b111, (outs),594 (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),595 "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;596}597 598let Predicates = [HasVendorXCVmem, IsRV32] in {599 // Register-Immediate load with post-increment600 def CV_LB_ri_inc : CVLoad_ri_inc<0b000, "cv.lb">;601 def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">;602 def CV_LH_ri_inc : CVLoad_ri_inc<0b001, "cv.lh">;603 def CV_LHU_ri_inc : CVLoad_ri_inc<0b101, "cv.lhu">;604 def CV_LW_ri_inc : CVLoad_ri_inc<0b010, "cv.lw">;605 606 // Register-Register load with post-increment607 def CV_LB_rr_inc : CVLoad_rr_inc<0b0000000, 0b011, "cv.lb">;608 def CV_LBU_rr_inc : CVLoad_rr_inc<0b0001000, 0b011, "cv.lbu">;609 def CV_LH_rr_inc : CVLoad_rr_inc<0b0000001, 0b011, "cv.lh">;610 def CV_LHU_rr_inc : CVLoad_rr_inc<0b0001001, 0b011, "cv.lhu">;611 def CV_LW_rr_inc : CVLoad_rr_inc<0b0000010, 0b011, "cv.lw">;612 613 // Register-Register load614 def CV_LB_rr : CVLoad_rr<0b0000100, 0b011, "cv.lb">;615 def CV_LBU_rr : CVLoad_rr<0b0001100, 0b011, "cv.lbu">;616 def CV_LH_rr : CVLoad_rr<0b0000101, 0b011, "cv.lh">;617 def CV_LHU_rr : CVLoad_rr<0b0001101, 0b011, "cv.lhu">;618 def CV_LW_rr : CVLoad_rr<0b0000110, 0b011, "cv.lw">;619 620 // Register-Immediate store with post-increment621 def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">;622 def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">;623 def CV_SW_ri_inc : CVStore_ri_inc<0b010, "cv.sw">;624 625 // Register-Register store with post-increment626 def CV_SB_rr_inc : CVStore_rr_inc<0b011, 0b0010000, "cv.sb">;627 def CV_SH_rr_inc : CVStore_rr_inc<0b011, 0b0010001, "cv.sh">;628 def CV_SW_rr_inc : CVStore_rr_inc<0b011, 0b0010010, "cv.sw">;629 630 // Register-Register store631 def CV_SB_rr : CVStore_rr<0b011, 0b0010100, "cv.sb">;632 def CV_SH_rr : CVStore_rr<0b011, 0b0010101, "cv.sh">;633 def CV_SW_rr : CVStore_rr<0b011, 0b0010110, "cv.sw">;634}635 636let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 1,637 mayLoad = 1, mayStore = 0 in {638 def PseudoCV_ELW : PseudoLoad<"cv.elw">;639 // Event load640 def CV_ELW : CVLoad_ri<0b011, "cv.elw">;641}642 643} // DecoderNamespace = "XCV"644 645//===----------------------------------------------------------------------===//646// Aliases647//===----------------------------------------------------------------------===//648 649let Predicates = [HasVendorXCVmac, IsRV32] in {650 // Xcvmac Pseudo Instructions651 // Signed 16x16 bit muls652 def : InstAlias<"cv.muls $rd1, $rs1, $rs2",653 (CV_MULSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;654 def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2",655 (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;656 657 // Unsigned 16x16 bit muls658 def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",659 (CV_MULUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;660 def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",661 (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;662} // Predicates = [HasVendorXCVmac, IsRV32]663 664let Predicates = [HasVendorXCValu, IsRV32] in {665 def : MnemonicAlias<"cv.slet", "cv.sle">;666 def : MnemonicAlias<"cv.sletu", "cv.sleu">;667}668 669//===----------------------------------------------------------------------===//670// Patterns for load & store operations671//===----------------------------------------------------------------------===//672class CVLdrrPat<PatFrag LoadOp, RVInst Inst>673 : Pat<(i32 (LoadOp CVrr:$regreg)),674 (Inst CVrr:$regreg)>;675 676class CVStriPat<PatFrag StoreOp, RVInst Inst>677 : Pat<(StoreOp (i32 GPR:$rs2), GPR:$rs1, simm12_lo:$imm12),678 (Inst GPR:$rs2, GPR:$rs1, simm12_lo:$imm12)>;679 680class CVStrriPat<PatFrag StoreOp, RVInst Inst>681 : Pat<(StoreOp (i32 GPR:$rs2), GPR:$rs1, GPR:$rs3),682 (Inst GPR:$rs2, GPR:$rs1, GPR:$rs3)>;683 684class CVStrrPat<PatFrag StoreOp, RVInst Inst>685 : Pat<(StoreOp (i32 GPR:$rs2), CVrr:$regreg),686 (Inst GPR:$rs2, CVrr:$regreg)>;687 688let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {689 def : CVLdrrPat<sextloadi8, CV_LB_rr>;690 def : CVLdrrPat<zextloadi8, CV_LBU_rr>;691 def : CVLdrrPat<extloadi8, CV_LBU_rr>;692 def : CVLdrrPat<sextloadi16, CV_LH_rr>;693 def : CVLdrrPat<zextloadi16, CV_LHU_rr>;694 def : CVLdrrPat<extloadi16, CV_LHU_rr>;695 def : CVLdrrPat<load, CV_LW_rr>;696 697 def : CVStriPat<post_truncsti8, CV_SB_ri_inc>;698 def : CVStriPat<post_truncsti16, CV_SH_ri_inc>;699 def : CVStriPat<post_store, CV_SW_ri_inc>;700 701 def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;702 def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;703 def : CVStrriPat<post_store, CV_SW_rr_inc>;704 705 def : CVStrrPat<truncstorei8, CV_SB_rr>;706 def : CVStrrPat<truncstorei16, CV_SH_rr>;707 def : CVStrrPat<store, CV_SW_rr>;708}709 710let Predicates = [HasVendorXCVelw, IsRV32] in {711 def : Pat<(int_riscv_cv_elw_elw (XLenVT GPR:$rs1)), (PseudoCV_ELW GPR:$rs1)>;712 def : Pat<(int_riscv_cv_elw_elw (AddrRegImm (XLenVT GPR:$rs1), simm12_lo:$imm12)),713 (CV_ELW GPR:$rs1, simm12_lo:$imm12)>;714}715 716multiclass PatCoreVBitManip<Intrinsic intr> {717 def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;718 def : Pat<(intr GPR:$rs1, cv_uimm10:$imm),719 (!cast<RVInst>("CV_" # NAME)720 GPR:$rs1, (CV_HI5 cv_uimm10:$imm), (CV_LO5 cv_uimm10:$imm))>;721}722 723let Predicates = [HasVendorXCVbitmanip, IsRV32] in {724 defm EXTRACT : PatCoreVBitManip<int_riscv_cv_bitmanip_extract>;725 defm EXTRACTU : PatCoreVBitManip<int_riscv_cv_bitmanip_extractu>;726 defm BCLR : PatCoreVBitManip<int_riscv_cv_bitmanip_bclr>;727 defm BSET : PatCoreVBitManip<int_riscv_cv_bitmanip_bset>;728 729 def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, GPR:$rs2, GPR:$rd),730 (CV_INSERTR GPR:$rd, GPR:$rs1, GPR:$rs2)>;731 def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, cv_uimm10:$imm, GPR:$rd),732 (CV_INSERT GPR:$rd, GPR:$rs1, (CV_HI5 cv_uimm10:$imm),733 (CV_LO5 cv_uimm10:$imm))>;734 735 def : PatGpr<cttz, CV_FF1, i32>;736 def : PatGpr<ctlz, CV_FL1, i32>;737 def : PatGpr<int_riscv_cv_bitmanip_clb, CV_CLB>;738 def : PatGpr<ctpop, CV_CNT, i32>;739 740 def : PatGprGpr<rotr, CV_ROR, i32>;741 742 def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts,743 cv_tuimm2:$radix),744 (CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;745 def : Pat<(bitreverse (i32 GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;746}747 748class PatCoreVAluGpr<string intr, string asm> :749 PatGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),750 !cast<RVInst>("CV_" # asm)>;751class PatCoreVAluGprGpr <string intr, string asm> :752 PatGprGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),753 !cast<RVInst>("CV_" # asm)>;754 755multiclass PatCoreVAluGprImm<Intrinsic intr> {756 def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;757 def : Pat<(intr (XLenVT GPR:$rs1), powerOf2Minus1:$upperBound),758 (!cast<RVInst>("CV_" # NAME) GPR:$rs1,759 (trailing1sPlus1 imm:$upperBound))>;760}761 762multiclass PatCoreVAluGprGprImm<Intrinsic intr> {763 def : Pat<(intr GPR:$rs1, GPR:$rs2, GPR:$rs3),764 (!cast<RVInst>("CV_" # NAME # "R") GPR:$rs1, GPR:$rs2, GPR:$rs3)>;765 def : Pat<(intr GPR:$rs1, GPR:$rs2, uimm5:$imm),766 (!cast<RVInst>("CV_" # NAME) GPR:$rs1, GPR:$rs2, uimm5:$imm)>;767}768 769let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {770 def : PatGpr<abs, CV_ABS, i32>;771 def : PatGprGpr<setle, CV_SLE, i32>;772 def : PatGprGpr<setule, CV_SLEU, i32>;773 def : PatGprGpr<smin, CV_MIN, i32>;774 def : PatGprGpr<umin, CV_MINU, i32>;775 def : PatGprGpr<smax, CV_MAX, i32>;776 def : PatGprGpr<umax, CV_MAXU, i32>;777 778 def : Pat<(sext_inreg (i32 GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;779 def : Pat<(sext_inreg (i32 GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;780 def : Pat<(and (i32 GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;781 def : Pat<(and (i32 GPR:$rs1), 0xff), (CV_EXTBZ GPR:$rs1)>;782 783 defm CLIP : PatCoreVAluGprImm<int_riscv_cv_alu_clip>;784 defm CLIPU : PatCoreVAluGprImm<int_riscv_cv_alu_clipu>;785 defm ADDN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addN>;786 defm ADDUN : PatCoreVAluGprGprImm<int_riscv_cv_alu_adduN>;787 defm ADDRN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addRN>;788 defm ADDURN : PatCoreVAluGprGprImm<int_riscv_cv_alu_adduRN>;789 defm SUBN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subN>;790 defm SUBUN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subuN>;791 defm SUBRN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subRN>;792 defm SUBURN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subuRN>;793} // Predicates = [HasVendorXCValu, IsRV32]794 795//===----------------------------------------------------------------------===//796// Patterns for immediate branching operations797//===----------------------------------------------------------------------===//798 799let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {800 def : Pat<(riscv_brcc (i32 GPR:$rs1), simm5:$imm5, SETEQ, bb:$imm12),801 (CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;802 def : Pat<(riscv_brcc (i32 GPR:$rs1), simm5:$imm5, SETNE, bb:$imm12),803 (CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;804 805 defm CC_SImm5_CV : SelectCC_GPR_riirr<GPR, simm5>;806 807 class Selectbi<CondCode Cond>808 : Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,809 (i32 GPR:$truev), GPR:$falsev),810 (Select_GPR_Using_CC_SImm5_CV GPR:$lhs, simm5:$Constant,811 (IntCCtoRISCVCC $cc), GPR:$truev, GPR:$falsev)>;812 813 def : Selectbi<SETEQ>;814 def : Selectbi<SETNE>;815}816 817class PatCoreVMacGprGprGpr <string intr, string asm>818 : Pat<(!cast<Intrinsic>("int_riscv_cv_mac_" # intr) GPR:$rs1, GPR:$rs2, GPR:$rd),819 (!cast<RVInst>("CV_" # asm) GPR:$rd, GPR:$rs1, GPR:$rs2)>;820class PatCoreVMacGprGprGprUimm5 <string intr, string asm>821 : Pat<(!cast<Intrinsic>("int_riscv_cv_mac_" # intr) GPR:$rs1, GPR:$rs2, GPR:$rd, cv_tuimm5:$imm5),822 (!cast<RVInst>("CV_" # asm) GPR:$rd, GPR:$rs1, GPR:$rs2, cv_tuimm5:$imm5)>;823class PatCoreVMacGprGprUimm5 <string intr, string asm>824 : Pat<(!cast<Intrinsic>("int_riscv_cv_mac_" # intr) GPR:$rs1, GPR:$rs2, cv_tuimm5:$imm5),825 (!cast<RVInst>("CV_" # asm) GPR:$rs1, GPR:$rs2, cv_tuimm5:$imm5)>;826 827let Predicates = [HasVendorXCVmac] in {828 def : PatCoreVMacGprGprGpr<"mac", "MAC">;829 def : PatCoreVMacGprGprGpr<"msu", "MSU">;830 831 def : PatCoreVMacGprGprUimm5<"muluN", "MULUN">;832 def : PatCoreVMacGprGprUimm5<"mulhhuN", "MULHHUN">;833 def : PatCoreVMacGprGprUimm5<"mulsN", "MULSN">;834 def : PatCoreVMacGprGprUimm5<"mulhhsN", "MULHHSN">;835 def : PatCoreVMacGprGprUimm5<"muluRN", "MULURN">;836 def : PatCoreVMacGprGprUimm5<"mulhhuRN", "MULHHURN">;837 def : PatCoreVMacGprGprUimm5<"mulsRN", "MULSRN">;838 def : PatCoreVMacGprGprUimm5<"mulhhsRN", "MULHHSRN">;839 840 def : PatCoreVMacGprGprGprUimm5<"macuN", "MACUN">;841 def : PatCoreVMacGprGprGprUimm5<"machhuN", "MACHHUN">;842 def : PatCoreVMacGprGprGprUimm5<"macsN", "MACSN">;843 def : PatCoreVMacGprGprGprUimm5<"machhsN", "MACHHSN">;844 def : PatCoreVMacGprGprGprUimm5<"macuRN", "MACURN">;845 def : PatCoreVMacGprGprGprUimm5<"machhuRN", "MACHHURN">;846 def : PatCoreVMacGprGprGprUimm5<"macsRN", "MACSRN">;847 def : PatCoreVMacGprGprGprUimm5<"machhsRN", "MACHHSRN">;848}849