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1//===-- RISCVInstrInfoXMips.td -----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the vendor extensions defined by MIPS.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Operand definitions.15//===----------------------------------------------------------------------===//16 17// A 7-bit unsigned immediate where the least significant three bits are zero.18def uimm7_lsb000 : RISCVOp,19 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {20 let ParserMatchClass = UImmAsmOperand<7, "Lsb000">;21 let EncoderMethod = "getImmOpValue";22 let DecoderMethod = "decodeUImmOperand<7>";23 let OperandType = "OPERAND_UIMM7_LSB000";24 let MCOperandPredicate = [{25 int64_t Imm;26 if (!MCOp.evaluateAsConstantImm(Imm))27 return false;28 return isShiftedUInt<4, 3>(Imm);29 }];30}31 32// A 9-bit unsigned offset33def uimm9 : RISCVUImmOp<9>;34 35// Custom prefetch ADDR selector36def AddrRegImm9 : ComplexPattern<iPTR, 2, "SelectAddrRegImm9">;37 38//===----------------------------------------------------------------------===//39// MIPS custom instruction formats40//===----------------------------------------------------------------------===//41 42// Load double pair format.43class LDPFormat<dag outs, dag ins, string opcodestr, string argstr>44 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {45 bits<7> imm7;46 bits<5> rs1;47 bits<5> rd1;48 bits<5> rd2;49 50 let Inst{31-27} = rd2;51 let Inst{26-23} = imm7{6-3};52 let Inst{22-20} = 0b000;53 let Inst{19-15} = rs1;54 let Inst{14-12} = 0b100;55 let Inst{11-7} = rd1;56 let Inst{6-0} = OPC_CUSTOM_0.Value;57}58 59// Load word pair format.60class LWPFormat<dag outs, dag ins, string opcodestr, string argstr>61 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {62 bits<7> imm7;63 bits<5> rs1;64 bits<5> rd1;65 bits<5> rd2;66 67 let Inst{31-27} = rd2;68 let Inst{26-22} = imm7{6-2};69 let Inst{21-20} = 0b01;70 let Inst{19-15} = rs1;71 let Inst{14-12} = 0b100;72 let Inst{11-7} = rd1;73 let Inst{6-0} = OPC_CUSTOM_0.Value;74}75 76// Store double pair format.77class SDPFormat<dag outs, dag ins, string opcodestr, string argstr>78 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {79 bits<7> imm7;80 bits<5> rs3;81 bits<5> rs2;82 bits<5> rs1;83 84 let Inst{31-27} = rs3;85 let Inst{26-25} = imm7{6-5};86 let Inst{24-20} = rs2;87 let Inst{19-15} = rs1;88 let Inst{14-12} = 0b101;89 let Inst{11-10} = imm7{4-3};90 let Inst{9-7} = 0b000;91 let Inst{6-0} = OPC_CUSTOM_0.Value;92}93 94// Store word pair format.95class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>96 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {97 bits<7> imm7;98 bits<5> rs3;99 bits<5> rs2;100 bits<5> rs1;101 102 let Inst{31-27} = rs3;103 let Inst{26-25} = imm7{6-5};104 let Inst{24-20} = rs2;105 let Inst{19-15} = rs1;106 let Inst{14-12} = 0b101;107 let Inst{11-9} = imm7{4-2};108 let Inst{8-7} = 0b01;109 let Inst{6-0} = OPC_CUSTOM_0.Value;110}111 112// Prefetch format.113let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in114class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>115 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {116 bits<9> imm9;117 bits<5> rs1;118 bits<5> hint;119 120 let Inst{31-29} = 0b000;121 let Inst{28-20} = imm9;122 let Inst{19-15} = rs1;123 let Inst{14-12} = 0b000;124 let Inst{11-7} = hint;125 let Inst{6-0} = OPC_CUSTOM_0.Value;126}127 128// MIPS Custom Barrier Insns Format.129let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in130class MIPSExtInst_ri<bits<6> shimm5, string opcodestr>131 : RVInstIShift<0b00000, 0b001, OPC_OP_IMM, (outs), (ins), opcodestr, ""> {132 let shamt = shimm5;133 let rd = 0;134 let rs1 = 0;135}136 137//===----------------------------------------------------------------------===//138// MIPS extensions139//===----------------------------------------------------------------------===//140let Predicates = [HasVendorXMIPSEXECTL], DecoderNamespace = "XMIPS" in {141 def MIPS_EHB : MIPSExtInst_ri<0b000011, "mips.ehb">;142 def MIPS_IHB : MIPSExtInst_ri<0b000001, "mips.ihb">;143 def MIPS_PAUSE : MIPSExtInst_ri<0b000101, "mips.pause">;144}145 146let Predicates = [HasVendorXMIPSEXECTL] in {147 // Intrinsics148 def : Pat<(int_riscv_mips_pause), (MIPS_PAUSE)>;149 def : Pat<(int_riscv_mips_ihb), (MIPS_IHB)>;150 def : Pat<(int_riscv_mips_ehb), (MIPS_EHB)>;151}152 153let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in {154 def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),155 "mips.pref", "$hint, ${imm9}(${rs1})">,156 Sched<[]>;157}158 159let Predicates = [HasVendorXMIPSCBOP] in {160 // Prefetch Data Write.161 def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),162 (i32 1), timm, (i32 1)),163 (MIPS_PREF GPR:$rs1, uimm9:$imm9, 9)>;164 // Prefetch Data Read.165 def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),166 (i32 0), timm, (i32 1)),167 (MIPS_PREF GPR:$rs1, uimm9:$imm9, 8)>;168}169 170let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,171 DecoderNamespace = "XMIPS" in {172def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),173 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3),174 "mips.ccmov", "$rd, $rs2, $rs1, $rs3">,175 Sched<[]>;176}177 178let Predicates = [UseMIPSCCMovInsn] in {179def : Pat<(select (riscv_setne (XLenVT GPR:$rs2)),180 (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),181 (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;182def : Pat<(select (riscv_seteq (XLenVT GPR:$rs2)),183 (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),184 (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;185 186def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),187 (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;188}189 190let Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0,191 DecoderNamespace = "XMIPS" in {192let mayLoad = 1, mayStore = 0 in {193def MIPS_LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb00:$imm7),194 "mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,195 Sched<[WriteLDW, WriteLDW, ReadMemBase]>;196def MIPS_LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb000:$imm7),197 "mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,198 Sched<[WriteLDD, WriteLDD, ReadMemBase]>;199} // mayLoad = 1, mayStore = 0200 201let mayLoad = 0, mayStore = 1 in {202def MIPS_SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb00:$imm7),203 "mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,204 Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]>;205def MIPS_SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb000:$imm7),206 "mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,207 Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]>;208} // mayLoad = 0, mayStore = 1209} // Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, DecoderNamespace = "XMIPS"210