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1//===-- RISCVInstrInfoXsf.td - SiFive custom instructions --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the vendor extensions defined by SiFive.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// XSFVCP extension instructions.15//===----------------------------------------------------------------------===//16 17def VCIXVS2 : RISCVVConstraint<VS2Constraint.Value>;18def VCIXVS2VS1 : RISCVVConstraint<!or(VS2Constraint.Value,19 VS1Constraint.Value)>;20 21class VCIXType<bits<4> val> {22 bits<4> Val = val;23}24 25def VCIX_X : VCIXType<0b0000>;26def VCIX_XV : VCIXType<0b0010>;27def VCIX_XVV : VCIXType<0b1010>;28def VCIX_XVW : VCIXType<0b1111>;29 30// The payload and tsimm5 operands are all marked as ImmArg in the IR31// intrinsic and will be target constant, so use TImmLeaf rather than ImmLeaf.32class PayloadOp<int bitsNum> : RISCVOp, TImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);"> {33 let OperandType = "OPERAND_UIMM" # bitsNum;34}35 36def payload1 : PayloadOp<1>;37def payload2 : PayloadOp<2>;38def payload5 : PayloadOp<5>;39 40def tsimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {41 let ParserMatchClass = SImmAsmOperand<5>;42 let EncoderMethod = "getImmOpValue";43 let DecoderMethod = "decodeSImmOperand<5>";44 let MCOperandPredicate = [{45 int64_t Imm;46 if (MCOp.evaluateAsConstantImm(Imm))47 return isInt<5>(Imm);48 return MCOp.isBareSymbolRef();49 }];50}51 52class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> {53 dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);54}55 56class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,57 string opcodestr, string argstr>58 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {59 bits<5> rs2;60 bits<5> rs1;61 bits<5> rd;62 bits<2> funct6_lo2;63 bit vm;64 65 let Inst{31-28} = funct6_hi4;66 let Inst{27-26} = funct6_lo2;67 let Inst{25} = vm;68 let Inst{24-20} = rs2;69 let Inst{19-15} = rs1;70 let Inst{14-12} = funct3;71 let Inst{11-7} = rd;72 let Inst{6-0} = OPC_CUSTOM_2.Value;73 74 let Uses = [VL, VTYPE];75 let RVVConstraint = NoConstraint;76 let ElementsDependOn = EltDepsVLMask;77 let ReadsPastVL = 1;78}79 80class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,81 string opcodestr, string argstr>82 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {83 bits<5> rs2;84 bits<5> rs1;85 bits<5> rd;86 bit funct6_lo1;87 bit vm;88 89 let Inst{31-28} = funct6_hi4;90 let Inst{27} = 1;91 let Inst{26} = funct6_lo1;92 let Inst{25} = vm;93 let Inst{24-20} = rs2;94 let Inst{19-15} = rs1;95 let Inst{14-12} = funct3;96 let Inst{11-7} = rd;97 let Inst{6-0} = OPC_CUSTOM_2.Value;98 99 let Uses = [VL, VTYPE];100 let RVVConstraint = NoConstraint;101 let ElementsDependOn = EltDepsVLMask;102 let ReadsPastVL = 1;103}104 105class VCIXInfo<string suffix, VCIXType type, DAGOperand TyRd,106 DAGOperand TyRs2, DAGOperand TyRs1, bit HaveOutputDst> {107 string OpcodeStr = !if(HaveOutputDst, "sf.vc.v." # suffix,108 "sf.vc." # suffix);109 bits<4> Funct6_hi4 = type.Val;110 bits<3> Funct3 = !cond(!eq(TyRs1, VR): 0b000,111 !eq(TyRs1, GPR): 0b100,112 !eq(TyRs1, FPR32): 0b101,113 !eq(TyRs1, simm5): 0b011);114 dag Outs = !if(!not(HaveOutputDst), (outs),115 !if(!or(!eq(type, VCIX_XVV), !eq(type, VCIX_XVW)),116 (outs TyRd:$rd_wb), (outs TyRd:$rd)));117 dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2),118 (ins uimm1:$funct6_lo1)),119 !if(!and(HaveOutputDst, !or(!eq(type, VCIX_X),120 !eq(type, VCIX_XV))),121 (ins), (ins TyRd:$rd)),122 (ins TyRs2:$rs2),123 (ins TyRs1:$rs1),124 !if(!eq(type, VCIX_X), 1, 0)>.Ins;125 string Prototype = !if(!eq(type, VCIX_X), "$funct6_lo2, $rs2, $rd, $rs1",126 !if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1",127 "$funct6_lo1, $rd, $rs2, $rs1"));128 string Constraints = !if(!not(HaveOutputDst), "",129 !if(!or(!eq(type, VCIX_XVV),130 !eq(type, VCIX_XVW)), "$rd = $rd_wb", ""));131 RISCVVConstraint RVVConstraint = !if(!or(!not(HaveOutputDst),132 !ne(type, VCIX_XVW)), NoConstraint,133 !if(!eq(TyRs1, VR), VCIXVS2VS1, VCIXVS2));134}135 136class CustomSiFiveVCIX<VCIXInfo info>137 : RVInstVCCustom2<info.Funct6_hi4, info.Funct3, info.Outs,138 info.Ins, info.OpcodeStr, info.Prototype> {139 let Constraints = info.Constraints;140 let RVVConstraint = info.RVVConstraint;141}142 143class CustomSiFiveVCIF<VCIXInfo info>144 : RVInstVCFCustom2<info.Funct6_hi4, info.Funct3, info.Outs,145 info.Ins, info.OpcodeStr, info.Prototype> {146 let Constraints = info.Constraints;147 let RVVConstraint = info.RVVConstraint;148}149 150multiclass CustomSiFiveVCIXorVCIF<string suffix, VCIXType type,151 DAGOperand TyRd, DAGOperand TyRs2,152 DAGOperand TyRs1, bit HaveOutputDst> {153 defvar info = VCIXInfo<suffix, type, TyRd, TyRs2, TyRs1, HaveOutputDst>;154 if !eq(TyRs1, FPR32) then {155 def NAME : CustomSiFiveVCIF<info>;156 } else {157 def NAME : CustomSiFiveVCIX<info>;158 }159}160 161multiclass CustomSiFiveVCIX<string suffix, VCIXType type,162 DAGOperand InTyRd, DAGOperand InTyRs2,163 DAGOperand InTyRs1> {164 let vm = 1 in165 defm SF_VC_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, InTyRd, InTyRs2,166 InTyRs1, 0>;167 let vm = 0 in168 defm SF_VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2,169 InTyRs1, 1>;170}171 172// For XSfvqmaccdod/qoq and XSfvfwmaccqqq173class SiFiveVMACCScheds<string name> {174 defvar n = !tolower(name);175 defvar prefix = !if(!ne(!find(n, "fw"), -1), "FW", "Q");176 defvar suffix = !if(!ne(!find(n, "2x8x2"), -1), "DOD",177 !if(!eq(prefix, "Q"), "QOQ", "QQQ"));178 179 string read = "ReadSF_V" # prefix # "MACC_" # suffix;180 string write = "WriteSF_V" # prefix # "MACC_" # suffix;181}182 183let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {184class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>185 : RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2),186 opcodestr, "$rd, $rs1, $rs2">,187 SchedTernaryMC<SiFiveVMACCScheds<NAME>.write,188 SiFiveVMACCScheds<NAME>.read,189 SiFiveVMACCScheds<NAME>.read,190 SiFiveVMACCScheds<NAME>.read> {191 let vm = 1;192 let funct6_lo2 = funct6{1-0};193}194}195 196class CustomSiFiveVFNRCLIP<bits<6> funct6, RISCVVFormat opv, string opcodestr>197 : VALUVF<funct6, opv, opcodestr>,198 SchedBinaryMC<"WriteSF_VFNRClipV", "ReadSF_VFNRClipV", "ReadSF_VFNRClipF"> {199 let Inst{6-0} = OPC_CUSTOM_2.Value;200}201 202let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,203 hasSideEffects = 1, hasNoSchedulingInfo = 1, DecoderNamespace = "XSfvector" in {204 defm X : CustomSiFiveVCIX<"x", VCIX_X, uimm5, uimm5, GPR>, Sched<[]>;205 defm I : CustomSiFiveVCIX<"i", VCIX_X, uimm5, uimm5, simm5>, Sched<[]>;206 defm XV : CustomSiFiveVCIX<"xv", VCIX_XV, uimm5, VR, GPR>, Sched<[]>;207 defm IV : CustomSiFiveVCIX<"iv", VCIX_XV, uimm5, VR, simm5>, Sched<[]>;208 defm VV : CustomSiFiveVCIX<"vv", VCIX_XV, uimm5, VR, VR>, Sched<[]>;209 defm FV : CustomSiFiveVCIX<"fv", VCIX_XV, uimm5, VR, FPR32>, Sched<[]>;210 defm XVV : CustomSiFiveVCIX<"xvv", VCIX_XVV, VR, VR, GPR>, Sched<[]>;211 defm IVV : CustomSiFiveVCIX<"ivv", VCIX_XVV, VR, VR, simm5>, Sched<[]>;212 defm VVV : CustomSiFiveVCIX<"vvv", VCIX_XVV, VR, VR, VR>, Sched<[]>;213 defm FVV : CustomSiFiveVCIX<"fvv", VCIX_XVV, VR, VR, FPR32>, Sched<[]>;214 defm XVW : CustomSiFiveVCIX<"xvw", VCIX_XVW, VR, VR, GPR>, Sched<[]>;215 defm IVW : CustomSiFiveVCIX<"ivw", VCIX_XVW, VR, VR, simm5>, Sched<[]>;216 defm VVW : CustomSiFiveVCIX<"vvw", VCIX_XVW, VR, VR, VR>, Sched<[]>;217 defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>;218}219 220let Predicates = [HasVendorXSfvfexpAny], DecoderNamespace = "XSfvector" in {221 def SF_VFEXP_V : VALUVs2<0b010011, 0b00111, OPFVV, "sf.vfexp.v">,222 SchedUnaryMC<"WriteSF_VFExp", "ReadSF_VFExp">;223}224 225let Predicates = [HasVendorXSfvfexpa], DecoderNamespace = "XSfvector" in {226 def SF_VFEXPA_V : VALUVs2<0b010011, 0b00110, OPFVV, "sf.vfexpa.v">,227 SchedUnaryMC<"WriteSF_VFExpa", "ReadSF_VFExpa">;228}229 230let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvector",231 DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in {232 def SF_VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;233 def SF_VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">;234 def SF_VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">;235 def SF_VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">;236}237 238let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvector",239 DestEEW = EEWSEWx4, RVVConstraint=WidenVNoMask in {240 def SF_VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;241 def SF_VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;242 def SF_VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;243 def SF_VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;244}245 246let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvector",247 DestEEW = EEWSEWx2, RVVConstraint=WidenVNoMask in {248 def SF_VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;249}250 251let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvector",252 Uses = [FRM, VL, VTYPE] in {253 def SF_VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">;254 def SF_VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">;255}256 257class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :258 RISCVVPseudo<(outs),259 (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,260 AVL:$vl, sew:$sew), []> {261 let mayLoad = 0;262 let mayStore = 0;263 let HasVLOp = 1;264 let HasSEWOp = 1;265 let hasSideEffects = 0;266}267 268class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :269 RISCVVPseudo<(outs),270 (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,271 AVL:$vl, sew:$sew), []> {272 let mayLoad = 0;273 let mayStore = 0;274 let HasVLOp = 1;275 let HasSEWOp = 1;276 let hasSideEffects = 0;277}278 279class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,280 DAGOperand RS1Class> :281 RISCVVPseudo<(outs),282 (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,283 AVL:$vl, sew:$sew), []> {284 let mayLoad = 0;285 let mayStore = 0;286 let HasVLOp = 1;287 let HasSEWOp = 1;288 let hasSideEffects = 0;289}290 291class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :292 RISCVVPseudo<(outs RDClass:$rd),293 (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,294 AVL:$vl, sew:$sew), []> {295 let mayLoad = 0;296 let mayStore = 0;297 let HasVLOp = 1;298 let HasSEWOp = 1;299 let hasSideEffects = 0;300}301 302class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,303 DAGOperand RS1Class> :304 RISCVVPseudo<(outs RDClass:$rd),305 (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,306 AVL:$vl, sew:$sew), []> {307 let mayLoad = 0;308 let mayStore = 0;309 let HasVLOp = 1;310 let HasSEWOp = 1;311 let hasSideEffects = 0;312}313 314class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,315 DAGOperand RS1Class> :316 RISCVVPseudo<(outs RDClass:$rd),317 (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,318 AVL:$vl, sew:$sew), []> {319 let mayLoad = 0;320 let mayStore = 0;321 let HasVLOp = 1;322 let HasSEWOp = 1;323 let hasSideEffects = 0;324 let Constraints = "$rd = $rs3";325}326 327multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,328 Operand OpClass = payload2> {329 let VLMul = m.value in {330 let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {331 def "PseudoSF_VC_" # NAME # "_SE_" # m.MX332 : VPseudoVC_X<OpClass, RS1Class>,333 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;334 def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX335 : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>,336 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;337 }338 def "PseudoSF_VC_V_" # NAME # "_" # m.MX339 : VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>,340 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;341 }342}343 344multiclass VPseudoVC_XV<LMULInfo m, DAGOperand RS1Class,345 Operand OpClass = payload2> {346 let VLMul = m.value in {347 let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {348 def "PseudoSF_VC_" # NAME # "_SE_" # m.MX349 : VPseudoVC_XV<OpClass, m.vrclass, RS1Class>,350 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;351 def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX352 : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>,353 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;354 }355 def "PseudoSF_VC_V_" # NAME # "_" # m.MX356 : VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>,357 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;358 }359}360 361multiclass VPseudoVC_XVV<LMULInfo m, DAGOperand RS1Class,362 Operand OpClass = payload2> {363 let VLMul = m.value in {364 let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {365 def "PseudoSF_VC_" # NAME # "_SE_" # m.MX366 : VPseudoVC_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,367 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;368 def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX369 : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,370 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;371 }372 def "PseudoSF_VC_V_" # NAME # "_" # m.MX373 : VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,374 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;375 }376}377 378multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,379 Operand OpClass = payload2> {380 let VLMul = m.value in {381 let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in382 def "PseudoSF_VC_" # NAME # "_SE_" # m.MX383 : VPseudoVC_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,384 Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;385 let Constraints = "@earlyclobber $rd, $rd = $rs3" in {386 let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in387 def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX388 : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,389 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;390 def "PseudoSF_VC_V_" # NAME # "_" # m.MX391 : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,392 Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;393 }394 }395}396 397multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type> {398 defvar SchedWriteName = SiFiveVMACCScheds<NAME>.write;399 defvar SchedReadName = SiFiveVMACCScheds<NAME>.read;400 def "Pseudo" # NAME # "_" # mx401 : VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type,402 "@earlyclobber $rd">,403 SchedTernary<SchedWriteName, SchedReadName, SchedReadName,404 SchedReadName, mx>;405}406 407multiclass VPseudoSiFiveVQMACCDOD {408 foreach m = MxListVF8 in409 let VLMul = m.value in410 defm NAME : VPseudoSiFiveVMACC<m.MX, m.vrclass, m.vrclass>;411}412 413multiclass VPseudoSiFiveVQMACCQOQ {414 foreach m = [V_MF2, V_M1, V_M2, V_M4] in415 let VLMul = m.value in416 defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass>;417}418 419multiclass VPseudoSiFiveVFWMACC {420 foreach m = MxListFW in421 let VLMul = m.value in422 defm NAME : VPseudoSiFiveVMACC<m.MX, m.wvrclass, m.vrclass>;423}424 425multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> {426 foreach i = 0-4 in427 let hasSideEffects = 0, hasPostISelHook = 1 in428 defm "Pseudo" # NAME : VPseudoBinaryRoundingMode<MxListW[i].vrclass,429 MxListVF4[i].vrclass,430 FPR32, MxListW[i],431 Constraint, /*sew*/0,432 UsesVXRM=0>,433 SchedBinary<"WriteSF_VFNRClipV", "ReadSF_VFNRClipV",434 "ReadSF_VFNRClipF",435 MxListW[i].MX>;436}437 438let Predicates = [HasVendorXSfvcp] in {439 foreach m = MxList in {440 defm X : VPseudoVC_X<m, GPR>;441 defm I : VPseudoVC_X<m, tsimm5>;442 defm XV : VPseudoVC_XV<m, GPR>;443 defm IV : VPseudoVC_XV<m, tsimm5>;444 defm VV : VPseudoVC_XV<m, m.vrclass>;445 defm XVV : VPseudoVC_XVV<m, GPR>;446 defm IVV : VPseudoVC_XVV<m, tsimm5>;447 defm VVV : VPseudoVC_XVV<m, m.vrclass>;448 }449 foreach f = FPList in {450 foreach m = f.MxList in {451 let AltFmtType = IS_NOT_ALTFMT in {452 defm f.FX # "V" : VPseudoVC_XV<m, f.fprclass, payload1>;453 defm f.FX # "VV" : VPseudoVC_XVV<m, f.fprclass, payload1>;454 }455 }456 }457 foreach m = MxListW in {458 defm XVW : VPseudoVC_XVW<m, GPR>;459 defm IVW : VPseudoVC_XVW<m, tsimm5>;460 defm VVW : VPseudoVC_XVW<m, m.vrclass>;461 }462 foreach f = FPListW in {463 foreach m = f.MxList in464 let AltFmtType = IS_NOT_ALTFMT in465 defm f.FX # "VW" : VPseudoVC_XVW<m, f.fprclass, payload1>;466 }467}468 469let Predicates = [HasVendorXSfvqmaccdod] in {470 defm SF_VQMACCU_2x8x2 : VPseudoSiFiveVQMACCDOD;471 defm SF_VQMACC_2x8x2 : VPseudoSiFiveVQMACCDOD;472 defm SF_VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD;473 defm SF_VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD;474}475 476let Predicates = [HasVendorXSfvqmaccqoq] in {477 defm SF_VQMACCU_4x8x4 : VPseudoSiFiveVQMACCQOQ;478 defm SF_VQMACC_4x8x4 : VPseudoSiFiveVQMACCQOQ;479 defm SF_VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ;480 defm SF_VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ;481}482 483let Predicates = [HasVendorXSfvfwmaccqqq] in {484 defm SF_VFWMACC_4x4x4 : VPseudoSiFiveVFWMACC;485}486 487let Predicates = [HasVendorXSfvfnrclipxfqf], AltFmtType = IS_NOT_ALTFMT in {488 defm SF_VFNRCLIP_XU_F_QF : VPseudoSiFiveVFNRCLIP;489 defm SF_VFNRCLIP_X_F_QF : VPseudoSiFiveVFNRCLIP;490}491 492class VFExpSchedSEWSet<string mx, bit IsBF16, bit IsApprox> {493 defvar BaseSet = SchedSEWSet<mx, isF=1>.val;494 list<int> val = !if(IsBF16, !listremove(BaseSet, [32, 64]),495 !if(IsApprox, BaseSet, !listremove(BaseSet, [64])));496}497multiclass VPseudoVFExp_V<bit IsBF16 = false, bit IsApprox = false> {498 defvar SchedSuffix = !if(IsApprox, "VFExpa", "VFExp");499 500 foreach m = MxListF in {501 defvar mx = m.MX;502 foreach e = VFExpSchedSEWSet<mx, IsBF16, IsApprox>.val in {503 let VLMul = m.value in {504 def "_V_" # mx # "_E" # e505 : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,506 SchedUnary<"WriteSF_" # SchedSuffix, "ReadSF_" # SchedSuffix,507 mx, e, forcePassthruRead=true>;508 def "_V_" # mx # "_E" # e # "_MASK"509 : VPseudoUnaryMask<m.vrclass, m.vrclass>,510 RISCVMaskedPseudo<MaskIdx = 2>,511 SchedUnary<"WriteSF_" # SchedSuffix, "ReadSF_" # SchedSuffix,512 mx, e, forcePassthruRead=true>;513 }514 }515 }516}517 518let Predicates = [HasVendorXSfvfbfexp16e], hasSideEffects = 0 in {519 let AltFmtType = IS_ALTFMT in {520 defm PseudoSF_VFEXP_ALT : VPseudoVFExp_V<IsBF16=true>;521 }522}523 524let Predicates = [HasVendorXSfvfexpAnyFloat], hasSideEffects = 0 in {525 let AltFmtType = IS_NOT_ALTFMT in {526 defm PseudoSF_VFEXP : VPseudoVFExp_V;527 }528}529 530let Predicates = [HasVendorXSfvfexpa], AltFmtType = IS_NOT_ALTFMT in {531 defm PseudoSF_VFEXPA : VPseudoVFExp_V<IsApprox=true>;532}533 534// SDNode535def SDT_SF_VC_V_X : SDTypeProfile<1, 4, [SDTCisVec<0>,536 SDTCisVT<1, XLenVT>,537 SDTCisSameAs<1, 2>,538 SDTCisSameAs<1, 3>,539 SDTCisSameAs<1, 4>]>;540 541def SDT_SF_VC_XV : SDTypeProfile<0, 5, [SDTCisSameAs<0, 1>,542 SDTCisVec<2>,543 SDTCisSameAs<0, 4>,544 SDTCisVT<0, XLenVT>]>;545 546def SDT_SF_VC_V_XV : SDTypeProfile<1, 4, [SDTCisVec<0>,547 SDTCisVT<1, XLenVT>,548 SDTCisSameAs<0, 2>,549 SDTCisSameAs<1, 4>]>;550 551def SDT_SF_VC_XVV : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>,552 SDTCisVec<1>,553 SDTCisSameAs<1, 2>,554 SDTCisSameAs<0, 4>]>;555 556def SDT_SF_VC_V_XVV : SDTypeProfile<1, 5, [SDTCisVec<0>,557 SDTCisVT<1, XLenVT>,558 SDTCisSameAs<0, 2>,559 SDTCisSameAs<0, 3>,560 SDTCisSameAs<1, 5>]>;561 562def SDT_SF_VC_XVW : SDTypeProfile<0, 5, [SDTCisVT<0, XLenVT>,563 SDTCisVec<1>, SDTCisVec<2>,564 SDTCisSameAs<0, 4>]>;565 566def SDT_SF_VC_V_XVW : SDTypeProfile<1, 5, [SDTCisVec<0>,567 SDTCisVT<1, XLenVT>,568 SDTCisSameAs<0, 2>,569 SDTCisVec<3>,570 SDTCisSameAs<1, 5>]>;571 572def sf_vc_v_x_se : RVSDNode<"SF_VC_V_X_SE", SDT_SF_VC_V_X, [SDNPHasChain]>;573def sf_vc_v_i_se : RVSDNode<"SF_VC_V_I_SE", SDT_SF_VC_V_X, [SDNPHasChain]>;574def sf_vc_vv_se : RVSDNode<"SF_VC_VV_SE", SDT_SF_VC_XV, [SDNPHasChain]>;575def sf_vc_xv_se : RVSDNode<"SF_VC_XV_SE", SDT_SF_VC_XV, [SDNPHasChain]>;576def sf_vc_iv_se : RVSDNode<"SF_VC_IV_SE", SDT_SF_VC_XV, [SDNPHasChain]>;577def sf_vc_fv_se : RVSDNode<"SF_VC_FV_SE", SDT_SF_VC_XV, [SDNPHasChain]>;578def sf_vc_v_vv_se : RVSDNode<"SF_VC_V_VV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>;579def sf_vc_v_xv_se : RVSDNode<"SF_VC_V_XV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>;580def sf_vc_v_iv_se : RVSDNode<"SF_VC_V_IV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>;581def sf_vc_v_fv_se : RVSDNode<"SF_VC_V_FV_SE", SDT_SF_VC_V_XV, [SDNPHasChain]>;582def sf_vc_vvv_se : RVSDNode<"SF_VC_VVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>;583def sf_vc_xvv_se : RVSDNode<"SF_VC_XVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>;584def sf_vc_ivv_se : RVSDNode<"SF_VC_IVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>;585def sf_vc_fvv_se : RVSDNode<"SF_VC_FVV_SE", SDT_SF_VC_XVV, [SDNPHasChain]>;586def sf_vc_v_vvv_se : RVSDNode<"SF_VC_V_VVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>;587def sf_vc_v_xvv_se : RVSDNode<"SF_VC_V_XVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>;588def sf_vc_v_ivv_se : RVSDNode<"SF_VC_V_IVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>;589def sf_vc_v_fvv_se : RVSDNode<"SF_VC_V_FVV_SE", SDT_SF_VC_V_XVV, [SDNPHasChain]>;590def sf_vc_vvw_se : RVSDNode<"SF_VC_VVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>;591def sf_vc_xvw_se : RVSDNode<"SF_VC_XVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>;592def sf_vc_ivw_se : RVSDNode<"SF_VC_IVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>;593def sf_vc_fvw_se : RVSDNode<"SF_VC_FVW_SE", SDT_SF_VC_XVW, [SDNPHasChain]>;594def sf_vc_v_vvw_se : RVSDNode<"SF_VC_V_VVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>;595def sf_vc_v_xvw_se : RVSDNode<"SF_VC_V_XVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>;596def sf_vc_v_ivw_se : RVSDNode<"SF_VC_V_IVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>;597def sf_vc_v_fvw_se : RVSDNode<"SF_VC_V_FVW_SE", SDT_SF_VC_V_XVW, [SDNPHasChain]>;598 599class VPatVC_OP4_ISD<SDPatternOperator op,600 string inst,601 ValueType op2_type,602 ValueType op3_type,603 ValueType op4_type,604 int sew,605 DAGOperand op2_kind,606 DAGOperand op3_kind,607 DAGOperand op4_kind,608 Operand op1_kind = payload2> :609 Pat<(op610 (XLenVT op1_kind:$op1),611 (op2_type op2_kind:$op2),612 (op3_type op3_kind:$op3),613 (op4_type op4_kind:$op4),614 VLOpFrag),615 (!cast<Instruction>(inst)616 (XLenVT op1_kind:$op1),617 (op2_type op2_kind:$op2),618 (op3_type op3_kind:$op3),619 (op4_type op4_kind:$op4),620 GPR:$vl, sew)>;621 622class VPatVC_V_OP4_ISD<SDPatternOperator op,623 string inst,624 ValueType result_type,625 ValueType op2_type,626 ValueType op3_type,627 ValueType op4_type,628 int sew,629 DAGOperand op2_kind,630 DAGOperand op3_kind,631 DAGOperand op4_kind,632 Operand op1_kind = payload2> :633 Pat<(result_type (op634 (XLenVT op1_kind:$op1),635 (op2_type op2_kind:$op2),636 (op3_type op3_kind:$op3),637 (op4_type op4_kind:$op4),638 VLOpFrag)),639 (!cast<Instruction>(inst)640 (XLenVT op1_kind:$op1),641 (op2_type op2_kind:$op2),642 (op3_type op3_kind:$op3),643 (op4_type op4_kind:$op4),644 GPR:$vl, sew)>;645 646 647class VPatVC_V_OP3_ISD<SDPatternOperator op,648 string inst,649 ValueType result_type,650 ValueType op2_type,651 ValueType op3_type,652 int sew,653 DAGOperand op2_kind,654 DAGOperand op3_kind,655 Operand op1_kind = payload2> :656 Pat<(result_type (op657 (XLenVT op1_kind:$op1),658 (op2_type op2_kind:$op2),659 (op3_type op3_kind:$op3),660 VLOpFrag)),661 (!cast<Instruction>(inst)662 (XLenVT op1_kind:$op1),663 (op2_type op2_kind:$op2),664 (op3_type op3_kind:$op3),665 GPR:$vl, sew)>;666 667class VPatVC_OP4<string intrinsic_name,668 string inst,669 ValueType op2_type,670 ValueType op3_type,671 ValueType op4_type,672 int sew,673 DAGOperand op2_kind,674 DAGOperand op3_kind,675 DAGOperand op4_kind,676 Operand op1_kind = payload2> :677 Pat<(!cast<Intrinsic>(intrinsic_name)678 (XLenVT op1_kind:$op1),679 (op2_type op2_kind:$op2),680 (op3_type op3_kind:$op3),681 (op4_type op4_kind:$op4),682 VLOpFrag),683 (!cast<Instruction>(inst)684 (XLenVT op1_kind:$op1),685 (op2_type op2_kind:$op2),686 (op3_type op3_kind:$op3),687 (op4_type op4_kind:$op4),688 GPR:$vl, sew)>;689 690class VPatVC_V_OP4<string intrinsic_name,691 string inst,692 ValueType result_type,693 ValueType op2_type,694 ValueType op3_type,695 ValueType op4_type,696 int sew,697 DAGOperand op2_kind,698 DAGOperand op3_kind,699 DAGOperand op4_kind,700 Operand op1_kind = payload2> :701 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)702 (XLenVT op1_kind:$op1),703 (op2_type op2_kind:$op2),704 (op3_type op3_kind:$op3),705 (op4_type op4_kind:$op4),706 VLOpFrag)),707 (!cast<Instruction>(inst)708 (XLenVT op1_kind:$op1),709 (op2_type op2_kind:$op2),710 (op3_type op3_kind:$op3),711 (op4_type op4_kind:$op4),712 GPR:$vl, sew)>;713 714class VPatVC_V_OP3<string intrinsic_name,715 string inst,716 ValueType result_type,717 ValueType op2_type,718 ValueType op3_type,719 int sew,720 DAGOperand op2_kind,721 DAGOperand op3_kind,722 Operand op1_kind = payload2> :723 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)724 (XLenVT op1_kind:$op1),725 (op2_type op2_kind:$op2),726 (op3_type op3_kind:$op3),727 VLOpFrag)),728 (!cast<Instruction>(inst)729 (XLenVT op1_kind:$op1),730 (op2_type op2_kind:$op2),731 (op3_type op3_kind:$op3),732 GPR:$vl, sew)>;733 734multiclass VPatVC_X<string intrinsic_suffix, string instruction_suffix,735 VTypeInfo vti, ValueType type, DAGOperand kind> {736 def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"),737 "PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,738 vti.Vector, XLenVT, type, vti.Log2SEW,739 payload5, kind>;740 def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix,741 "PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,742 vti.Vector, XLenVT, type, vti.Log2SEW,743 payload5, kind>;744}745 746multiclass VPatVC_XV<string intrinsic_suffix, string instruction_suffix,747 VTypeInfo vti, ValueType type, DAGOperand kind,748 Operand op1_kind = payload2> {749 def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"),750 "PseudoSF_VC_" # instruction_suffix # "_SE_" # vti.LMul.MX,751 XLenVT, vti.Vector, type, vti.Log2SEW,752 payload5, vti.RegClass, kind, op1_kind>;753 def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"),754 "PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,755 vti.Vector, vti.Vector, type, vti.Log2SEW,756 vti.RegClass, kind, op1_kind>;757 def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix,758 "PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,759 vti.Vector, vti.Vector, type, vti.Log2SEW,760 vti.RegClass, kind, op1_kind>;761}762 763multiclass VPatVC_XVV<string intrinsic_suffix, string instruction_suffix,764 VTypeInfo wti, VTypeInfo vti, ValueType type, DAGOperand kind,765 Operand op1_kind = payload2> {766 def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"),767 "PseudoSF_VC_" # instruction_suffix # "_SE_" # vti.LMul.MX,768 wti.Vector, vti.Vector, type, vti.Log2SEW,769 wti.RegClass, vti.RegClass, kind, op1_kind>;770 def : VPatVC_V_OP4_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"),771 "PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,772 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW,773 wti.RegClass, vti.RegClass, kind, op1_kind>;774 def : VPatVC_V_OP4<"int_riscv_sf_vc_v_" # intrinsic_suffix,775 "PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,776 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW,777 wti.RegClass, vti.RegClass, kind, op1_kind>;778}779 780class GetFTypeInfo<int Sew> {781 ValueType Scalar = !cond(!eq(Sew, 16) : f16,782 !eq(Sew, 32) : f32,783 !eq(Sew, 64) : f64);784 RegisterClass ScalarRegClass = !cond(!eq(Sew, 16) : FPR16,785 !eq(Sew, 32) : FPR32,786 !eq(Sew, 64) : FPR64);787 788 string ScalarSuffix = !cond(!eq(Scalar, f16) : "FPR16",789 !eq(Scalar, f32) : "FPR32",790 !eq(Scalar, f64) : "FPR64");791}792 793multiclass VPatVMACC<string intrinsic, string instruction, string kind,794 list<VTypeInfoToWide> info_pairs, ValueType vec_m1> {795 foreach pair = info_pairs in {796 defvar VdInfo = pair.Wti;797 defvar Vs2Info = pair.Vti;798 let Predicates = [HasVInstructions] in799 def : VPatTernaryNoMaskWithPolicy<"int_riscv_sf_" # intrinsic,800 "Pseudo" # instruction, kind, VdInfo.Vector,801 vec_m1, Vs2Info.Vector,802 Vs2Info.Log2SEW, Vs2Info.LMul,803 VdInfo.RegClass, VR, Vs2Info.RegClass>;804 }805}806 807defset list<VTypeInfoToWide> VQMACCDODInfoPairs = {808 def : VTypeInfoToWide<VI8M1, VI32M1>;809 def : VTypeInfoToWide<VI8M2, VI32M2>;810 def : VTypeInfoToWide<VI8M4, VI32M4>;811 def : VTypeInfoToWide<VI8M8, VI32M8>;812}813 814defset list<VTypeInfoToWide> VQMACCQOQInfoPairs = {815 def : VTypeInfoToWide<VI8MF2, VI32M1>;816 def : VTypeInfoToWide<VI8M1, VI32M2>;817 def : VTypeInfoToWide<VI8M2, VI32M4>;818 def : VTypeInfoToWide<VI8M4, VI32M8>;819}820 821multiclass VPatVQMACCDOD<string intrinsic, string instruction, string kind>822 : VPatVMACC<intrinsic, instruction, kind, VQMACCDODInfoPairs, vint8m1_t>;823 824multiclass VPatVQMACCQOQ<string intrinsic, string instruction, string kind>825 : VPatVMACC<intrinsic, instruction, kind, VQMACCQOQInfoPairs, vint8m1_t>;826 827multiclass VPatVFWMACC<string intrinsic, string instruction, string kind>828 : VPatVMACC<intrinsic, instruction, kind, AllWidenableBF16ToFloatVectors,829 vbfloat16m1_t>;830 831defset list<VTypeInfoToWide> VFNRCLIPInfoPairs = {832 def : VTypeInfoToWide<VI8MF8, VF32MF2>;833 def : VTypeInfoToWide<VI8MF4, VF32M1>;834 def : VTypeInfoToWide<VI8MF2, VF32M2>;835 def : VTypeInfoToWide<VI8M1, VF32M4>;836 def : VTypeInfoToWide<VI8M2, VF32M8>;837}838 839multiclass VPatVFNRCLIP<string intrinsic, string instruction> {840 foreach pair = VFNRCLIPInfoPairs in {841 defvar Vti = pair.Vti;842 defvar Wti = pair.Wti;843 defm : VPatBinaryRoundingMode<"int_riscv_sf_" # intrinsic,844 "Pseudo" # instruction # "_" # Vti.LMul.MX,845 Vti.Vector, Wti.Vector, Wti.Scalar, Vti.Mask,846 Vti.Log2SEW, Vti.RegClass,847 Wti.RegClass, Wti.ScalarRegClass>;848 }849}850 851let Predicates = [HasVendorXSfvcp] in {852 foreach vti = AllIntegerVectors in {853 defm : VPatVC_X<"x", "X", vti, XLenVT, GPR>;854 defm : VPatVC_X<"i", "I", vti, XLenVT, tsimm5>;855 defm : VPatVC_XV<"xv", "XV", vti, XLenVT, GPR>;856 defm : VPatVC_XV<"iv", "IV", vti, XLenVT, tsimm5>;857 defm : VPatVC_XV<"vv", "VV", vti, vti.Vector, vti.RegClass>;858 defm : VPatVC_XVV<"xvv", "XVV", vti, vti, XLenVT, GPR>;859 defm : VPatVC_XVV<"ivv", "IVV", vti, vti, XLenVT, tsimm5>;860 defm : VPatVC_XVV<"vvv", "VVV", vti, vti, vti.Vector, vti.RegClass>;861 862 if !ne(vti.SEW, 8) then {863 defvar finfo = GetFTypeInfo<vti.SEW>;864 defm : VPatVC_XV<"fv", finfo.ScalarSuffix # "V", vti, finfo.Scalar,865 finfo.ScalarRegClass, payload1>;866 defm : VPatVC_XVV<"fvv", finfo.ScalarSuffix # "VV", vti, vti, finfo.Scalar,867 finfo.ScalarRegClass, payload1>;868 }869 }870 foreach VtiToWti = AllWidenableIntVectors in {871 defvar vti = VtiToWti.Vti;872 defvar wti = VtiToWti.Wti;873 defvar iinfo = GetIntVTypeInfo<vti>.Vti;874 defm : VPatVC_XVV<"xvw", "XVW", wti, vti, iinfo.Scalar, iinfo.ScalarRegClass>;875 defm : VPatVC_XVV<"ivw", "IVW", wti, vti, XLenVT, tsimm5>;876 defm : VPatVC_XVV<"vvw", "VVW", wti, vti, vti.Vector, vti.RegClass>;877 878 if !ne(vti.SEW, 8) then {879 defvar finfo = GetFTypeInfo<vti.SEW>;880 defm : VPatVC_XVV<"fvw", finfo.ScalarSuffix # "VW", wti, vti, finfo.Scalar,881 finfo.ScalarRegClass, payload1>;882 }883 }884}885 886let Predicates = [HasVendorXSfvqmaccdod] in {887 defm : VPatVQMACCDOD<"vqmaccu_2x8x2", "SF_VQMACCU", "2x8x2">;888 defm : VPatVQMACCDOD<"vqmacc_2x8x2", "SF_VQMACC", "2x8x2">;889 defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "SF_VQMACCUS", "2x8x2">;890 defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "SF_VQMACCSU", "2x8x2">;891}892 893let Predicates = [HasVendorXSfvqmaccqoq] in {894 defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "SF_VQMACCU", "4x8x4">;895 defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "SF_VQMACC", "4x8x4">;896 defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "SF_VQMACCUS", "4x8x4">;897 defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "SF_VQMACCSU", "4x8x4">;898}899 900let Predicates = [HasVendorXSfvfwmaccqqq] in {901 defm : VPatVFWMACC<"vfwmacc_4x4x4", "SF_VFWMACC", "4x4x4">;902}903 904let Predicates = [HasVendorXSfvfnrclipxfqf] in {905 defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "SF_VFNRCLIP_XU_F_QF">;906 defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "SF_VFNRCLIP_X_F_QF">;907}908 909let Predicates = [HasVendorXSiFivecdiscarddlone] in {910 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,911 DecoderNamespace = "XSfsystem" in912 def SF_CDISCARD_D_L1913 : RVInstIUnary<0b111111000010, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),914 "sf.cdiscard.d.l1", "$rs1">, Sched<[]> {915 let rd = 0;916 }917 def : InstAlias<"sf.cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>;918} // Predicates = [HasVendorXSifivecdiscarddlone]919 920let Predicates = [HasVendorXSiFivecflushdlone] in {921 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,922 DecoderNamespace = "XSfsystem" in923 def SF_CFLUSH_D_L1924 : RVInstIUnary<0b111111000000, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),925 "sf.cflush.d.l1", "$rs1">, Sched<[]> {926 let rd = 0;927 }928 def : InstAlias<"sf.cflush.d.l1", (SF_CFLUSH_D_L1 X0)>;929} // Predicates = [HasVendorXSifivecflushdlone]930 931let Predicates = [HasVendorXSfcease] in {932 let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,933 DecoderNamespace = "XSfcease" in934 def SF_CEASE : Priv<"sf.cease", 0b0011000>, Sched<[]> {935 let rd = 0b00000;936 let rs1 = 0b00000;937 let rs2 = 0b00101;938}939}940 941let Predicates = [HasVendorXSfvfbfexp16e] in {942 defm : VPatUnaryV_V<"int_riscv_sf_vfexp", "PseudoSF_VFEXP_ALT",943 AllBF16Vectors,944 isSEWAware=1>;945}946 947let Predicates = [HasVendorXSfvfexp16e] in {948 defm : VPatUnaryV_V<"int_riscv_sf_vfexp", "PseudoSF_VFEXP",949 [VF16MF4, VF16MF2, VF16M1, VF16M2, VF16M4, VF16M8],950 isSEWAware=1>;951}952 953let Predicates = [HasVendorXSfvfexp32e] in {954 defm : VPatUnaryV_V<"int_riscv_sf_vfexp", "PseudoSF_VFEXP",955 [VF32MF2, VF32M1, VF32M2, VF32M4, VF32M8], isSEWAware=1>;956}957 958let Predicates = [HasVendorXSfvfexpa] in {959 defm : VPatUnaryV_V<"int_riscv_sf_vfexpa", "PseudoSF_VFEXPA",960 [VF32MF2, VF32M1, VF32M2, VF32M4, VF32M8], isSEWAware=1>;961}962 963let Predicates = [HasVendorXSfvfexpa, HasVInstructionsF16] in {964 defm : VPatUnaryV_V<"int_riscv_sf_vfexpa", "PseudoSF_VFEXPA",965 [VF16MF4, VF16MF2, VF16M1, VF16M2, VF16M4, VF16M8],966 isSEWAware=1>;967}968 969let Predicates = [HasVendorXSfvfexpa64e] in {970 defm : VPatUnaryV_V<"int_riscv_sf_vfexpa", "PseudoSF_VFEXPA",971 [VF64M1, VF64M2, VF64M4, VF64M8], isSEWAware=1>;972}973