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1//===-- RISCVInstrInfoXsfmm.td - SiFive matrix multiply ----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Xsfmm* vendor extensions defined by SiFive.10//11//===----------------------------------------------------------------------===//12 13def XSfmmVTypeAsmOperand : AsmOperandClass {14 let Name = "XSfmmVType";15 let ParserMethod = "parseXSfmmVType";16 let RenderMethod = "addVTypeIOperands";17}18 19def XSfmmVTypeOp : RISCVOp {20 let ParserMatchClass = XSfmmVTypeAsmOperand;21 let PrintMethod = "printXSfmmVType";22 let OperandType = "OPERAND_XSFMM_VTYPE";23 let MCOperandPredicate = [{24 int64_t Imm;25 if (!MCOp.evaluateAsConstantImm(Imm))26 return false;27 if (!isUInt<32>(Imm))28 return false;29 return RISCVVType::isValidXSfmmVType(Imm);30 }];31}32 33let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in34class SFInstSetSingle<dag outs, dag ins, bits<5> rs2, string opcodestr,35 string argstr>36 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {37 bits<5> rs1;38 bits<5> rd;39 40 let Inst{31-25} = 0b1000010;41 let Inst{24-20} = rs2;42 let Inst{19-15} = rs1;43 let Inst{14-12} = OPCFG.Value;44 let Inst{11-7} = rd;45 let Inst{6-0} = OPC_OP_V.Value;46 47 let Defs = [VTYPE, VL];48}49 50class SFInstTileMemOp<dag outs, dag ins, bits<3> nf, RISCVOpcode opcode,51 string opcodestr, string argstr>52 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {53 bits<5> rs2;54 bits<5> rs1;55 56 let Inst{31-29} = nf;57 let Inst{28} = 1;58 let Inst{27-26} = MOPLDUnitStride.Value;59 let Inst{25} = 1;60 let Inst{24-20} = rs2;61 let Inst{19-15} = rs1;62 let Inst{14-12} = 0b111;63 let Inst{11-7} = 0b00000;64 let Inst{6-0} = opcode.Value;65 66 let Uses = [VTYPE, VL];67 let ReadsPastVL = 1;68}69 70let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in71class SFInstTileLoad<bits<3> nf, string opcodestr>72 : SFInstTileMemOp<(outs), (ins GPR:$rs2, GPRMemZeroOffset:$rs1), nf,73 OPC_LOAD_FP, opcodestr, "$rs2, ${rs1}">;74 75let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in76class SFInstTileStore<bits<3> nf, string opcodestr>77 : SFInstTileMemOp<(outs), (ins GPR:$rs2, GPRMemZeroOffset:$rs1), nf,78 OPC_STORE_FP, opcodestr, "$rs2, ${rs1}">;79 80let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in81class SFInstTileMoveOp<bits<6> funct6, dag outs, dag ins, string opcodestr,82 string argstr>83 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {84 bits<5> rs2;85 bits<5> rs1;86 bits<5> vd;87 88 let Inst{31-26} = funct6;89 let Inst{25} = 1;90 let Inst{24-20} = rs2;91 let Inst{19-15} = rs1;92 let Inst{14-12} = OPMVX.Value;93 let Inst{11-7} = vd;94 let Inst{6-0} = OPC_OP_V.Value;95 96 let Uses = [VTYPE, VL];97 let ReadsPastVL = 1;98}99 100let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in101class SFInstMatmulF<dag outs, dag ins, string opcodestr, string argstr>102 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {103 bits<5> vs2;104 bits<5> vs1;105 bits<4> rd;106 107 let Inst{31-26} = 0b111100;108 let Inst{25} = 1;109 let Inst{24-20} = vs2;110 let Inst{19-15} = vs1;111 let Inst{14-12} = OPFVV.Value;112 let Inst{11-9} = rd{3-1};113 let Inst{8-7} = 0b00;114 let Inst{6-0} = OPC_OP_VE.Value;115 116 let Uses = [VTYPE, VL];117 let ReadsPastVL = 1;118}119 120let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in121class SFInstMatmulF8<bit a, bit b, dag outs, dag ins,122 string opcodestr, string argstr>123 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {124 bits<5> vs2;125 bits<5> vs1;126 bits<4> rd;127 128 let Inst{31-27} = 0b11111;129 let Inst{26} = a;130 let Inst{25} = 1;131 let Inst{24-20} = vs2;132 let Inst{19-15} = vs1;133 let Inst{14-12} = OPFVV.Value;134 let Inst{11-10} = rd{3-2};135 let Inst{9-8} = 0b00;136 let Inst{7} = b;137 let Inst{6-0} = OPC_OP_VE.Value;138 139 let Uses = [VTYPE, VL];140 let ReadsPastVL = 1;141}142 143 144class F8Encode<bit encoding, string name> {145 bit Encoding = encoding;146 string Name = name;147}148 149defvar F8Encodes = [F8Encode<0b0, "e5m2">,150 F8Encode<0b1, "e4m3">];151 152let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in153class SFInstMatmulI8<bit funct6_1, bit a, bit b, dag outs, dag ins,154 string opcodestr, string argstr>155 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {156 bits<5> vs2;157 bits<5> vs1;158 bits<4> rd;159 160 let Inst{31-28} = 0b1111;161 let Inst{27} = funct6_1;162 let Inst{26} = a;163 let Inst{25} = 1;164 let Inst{24-20} = vs2;165 let Inst{19-15} = vs1;166 let Inst{14-12} = OPIVV.Value;167 let Inst{11-10} = rd{3-2};168 let Inst{9-8} = 0b00;169 let Inst{7} = b;170 let Inst{6-0} = OPC_OP_VE.Value;171 172 let Uses = [VTYPE, VL];173 let ReadsPastVL = 1;174}175 176class I8Encode<bit encoding, string name> {177 bit Encoding = encoding;178 string Name = name;179}180 181defvar I8Encodes = [I8Encode<0, "u">,182 I8Encode<1, "s">];183 184let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in185class SFInstSetZero<dag outs, dag ins, string opcodestr, string argstr>186 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {187 bits<5> vs2;188 bits<5> vs1;189 bits<4> rd;190 191 let Inst{31-26} = 0b010000;192 let Inst{25} = 1;193 let Inst{24-20} = 0b11110;194 let Inst{19-15} = 0b00000;195 let Inst{14-12} = OPMVX.Value;196 let Inst{11-8} = rd;197 let Inst{7} = 0;198 let Inst{6-0} = OPC_OP_V.Value;199 200 let Uses = [VTYPE, VL];201}202 203let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in204class SFInstVtDiscard<string opcodestr>205 : RVInst<(outs), (ins), opcodestr, "", [], InstFormatR> {206 let Inst{31-26} = 0b010000;207 let Inst{25} = 1;208 let Inst{24-20} = 0b11100;209 let Inst{19-15} = 0b00000;210 let Inst{14-12} = OPMVX.Value;211 let Inst{11-7} = 0b00000;212 let Inst{6-0} = OPC_OP_V.Value;213}214 215let Predicates = [HasVendorXSfmmbase] in216def : InstAlias<"sf.vsettnt $rd, $rs1, $vtypei",217 (VSETVLI GPR:$rd, GPR:$rs1, XSfmmVTypeOp:$vtypei)>;218 219let DecoderNamespace = "XSfvector" in {220 221let Predicates = [HasVendorXSfmmbase] in {222 def SF_VSETTN : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00000,223 "sf.vsettn", "$rd, $rs1">;224 def SF_VSETTM : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00001,225 "sf.vsettm", "$rd, $rs1">;226 def SF_VSETTK : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00010,227 "sf.vsettk", "$rd, $rs1">;228 def SF_VTDISCARD : SFInstVtDiscard<"sf.vtdiscard">;229 230 def SF_VTMV_V_T : SFInstTileMoveOp<0b010000, (outs VR:$vd), (ins GPR:$rs1),231 "sf.vtmv.v.t", "$vd, $rs1"> {232 let rs2 = 0b11111;233 }234 def SF_VTMV_T_V : SFInstTileMoveOp<0b010111, (outs), (ins GPR:$rs1, VR:$rs2),235 "sf.vtmv.t.v", "$rs1, $rs2"> {236 let vd = 0b00000;237 }238 239 def SF_VTZERO_T : SFInstSetZero<(outs), (ins TR:$rd), "sf.vtzero.t", "$rd">;240 241 def SF_VLTE8 : SFInstTileLoad<0b000, "sf.vlte8">;242 def SF_VLTE16 : SFInstTileLoad<0b001, "sf.vlte16">;243 def SF_VLTE32 : SFInstTileLoad<0b010, "sf.vlte32">;244 def SF_VLTE64 : SFInstTileLoad<0b011, "sf.vlte64">;245 246 def SF_VSTE8 : SFInstTileStore<0b000, "sf.vste8">;247 def SF_VSTE16 : SFInstTileStore<0b001, "sf.vste16">;248 def SF_VSTE32 : SFInstTileStore<0b010, "sf.vste32">;249 def SF_VSTE64 : SFInstTileStore<0b011, "sf.vste64">;250} // Predicates = [HasVendorXSfmmbase]251 252let Predicates = [HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f] in {253 let Uses = [FRM], mayRaiseFPException = true in254 def SF_MM_F_F : SFInstMatmulF<(outs), (ins TRM2:$rd, VR:$vs2, VR:$vs1),255 "sf.mm.f.f", "$rd, $vs2, $vs1">;256} // Predicates = [HasVendorXSfmm32a16fOrXSfmm64a32fOrXSfmm64a64f]257 258let Predicates = [HasVendorXSfmm32a8i] in {259 foreach a = I8Encodes in260 foreach b = I8Encodes in261 def SF_MM_#!toupper(a.Name)#_#!toupper(b.Name)262 : SFInstMatmulI8<0, a.Encoding, b.Encoding,263 (outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),264 "sf.mm."#a.Name#"."#b.Name, "$rd, $vs2, $vs1">;265} // Predicates = [HasVendorXSfmm32a8i]266 267let Predicates = [HasVendorXSfmm32a8f] in {268let Uses = [FRM], mayRaiseFPException = true in {269 foreach a = F8Encodes in270 foreach b = F8Encodes in271 def SF_MM_#!toupper(a.Name)#_#!toupper(b.Name)272 : SFInstMatmulF8<a.Encoding, b.Encoding,273 (outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),274 "sf.mm."#a.Name#"."#b.Name, "$rd, $vs2, $vs1">;275}276} // Predicates = [HasVendorXSfmm32a8f]277 278} // DecoderNamespace = "XSfvector"279 280class VPseudoSF_VTileLoad281 : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,282 ixlenimm:$twiden)> {283 let mayLoad = 1;284 let mayStore = 0;285 let HasVLOp = 1; // Tn286 let HasSEWOp = 1;287 let HasTWidenOp = 1;288 let hasSideEffects = 1;289}290 291class VPseudoSF_VTileStore292 : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,293 ixlenimm:$twiden)> {294 let mayLoad = 0;295 let mayStore = 1;296 let HasVLOp = 1; // Tn297 let HasSEWOp = 1;298 let HasTWidenOp = 1;299 let hasSideEffects = 1;300}301 302class VPseudoSF_VTileMove_V_T303 : RISCVVPseudo<(outs VRM8:$vd), (ins GPR:$rs1, AVL:$atn, ixlenimm:$sew,304 ixlenimm:$twiden)> {305 let mayLoad = 0;306 let mayStore = 0;307 let HasVLOp = 1; // Tn308 let HasSEWOp = 1;309 let HasTWidenOp = 1;310 let hasSideEffects = 1;311}312 313class VPseudoSF_VTileMove_T_V314 : RISCVVPseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, AVL:$atn, ixlenimm:$sew,315 ixlenimm:$twiden)> {316 let mayLoad = 0;317 let mayStore = 0;318 let HasVLOp = 1; // Tn319 let HasSEWOp = 1;320 let HasTWidenOp = 1;321 let hasSideEffects = 1;322}323 324class VPseudoSF_MatMul<RegisterClass mtd_class>325 : RISCVVPseudo<(outs),326 (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, AVL:$atm, AVL:$atn,327 AVL:$atk, ixlenimm:$sew, ixlenimm:$twiden)> {328 let mayLoad = 0;329 let mayStore = 0;330 let HasTmOp = 1;331 let HasVLOp = 1; // Tn332 let HasTkOp = 1;333 let HasSEWOp = 1;334 let HasTWidenOp = 1;335 let hasSideEffects = 1;336}337 338class VPseudoSF_MatMul_FRM<RegisterClass mtd_class>339 : RISCVVPseudo<(outs),340 (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, ixlenimm:$frm,341 AVL:$atm, AVL:$atn, AVL:$atk, ixlenimm:$sew,342 ixlenimm:$twiden), []> {343 let mayLoad = 0;344 let mayStore = 0;345 let HasTmOp = 1;346 let HasVLOp = 1; // Tn347 let HasTkOp = 1;348 let HasSEWOp = 1;349 let HasRoundModeOp = 1;350 let hasPostISelHook = 1;351 let HasTWidenOp = 1;352 let hasSideEffects = 1;353 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);354}355 356let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {357let Defs = [VL, VTYPE] in {358 def PseudoSF_VSETTNT359 : Pseudo<(outs GPR:$rd),360 (ins GPRNoX0:$rs1, XSfmmVTypeOp:$vtypei), []>,361 PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,362 Sched<[WriteVSETVLI, ReadVSETVLI]>;363 def PseudoSF_VSETTNTX0364 : Pseudo<(outs GPRNoX0:$rd),365 (ins GPRX0:$rs1, XSfmmVTypeOp:$vtypei), []>,366 PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,367 Sched<[WriteVSETVLI, ReadVSETVLI]>;368 def PseudoSF_VSETTNTX0X0369 : Pseudo<(outs GPRX0:$rd),370 (ins GPRX0:$rs1, XSfmmVTypeOp:$vtypei), []>,371 PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>,372 Sched<[WriteVSETVLI, ReadVSETVLI]>;373}374 375let Defs = [VTYPE], Uses = [VTYPE], HasTWidenOp = 1, HasSEWOp = 1 in {376 def PseudoSF_VSETTM377 : Pseudo<(outs GPR:$rd),378 (ins GPR:$rs1, ixlenimm:$log2sew, ixlenimm:$twiden), []>,379 PseudoInstExpansion<(SF_VSETTM GPR:$rd, GPR:$rs1)>,380 Sched<[WriteVSETVLI, ReadVSETVLI]>;381 def PseudoSF_VSETTK382 : Pseudo<(outs GPR:$rd),383 (ins GPR:$rs1, ixlenimm:$logwsew, ixlenimm:$twiden), []>,384 PseudoInstExpansion<(SF_VSETTK GPR:$rd, GPR:$rs1)>,385 Sched<[WriteVSETVLI, ReadVSETVLI]>;386}387}388 389foreach eew = [8, 16, 32, 64] in {390 def PseudoSF_VLTE # eew : VPseudoSF_VTileLoad;391 def PseudoSF_VSTE # eew : VPseudoSF_VTileStore;392}393 394def PseudoSF_VTMV_T_V : VPseudoSF_VTileMove_T_V;395def PseudoSF_VTMV_V_T : VPseudoSF_VTileMove_V_T;396 397foreach a = I8Encodes in398 foreach b = I8Encodes in399 def PseudoSF_MM_ # !toupper(a.Name) # _ # !toupper(b.Name)400 : VPseudoSF_MatMul<TRM4>;401 402let AltFmtType = IS_NOT_ALTFMT in403 def PseudoSF_MM_F_F : VPseudoSF_MatMul_FRM<TRM2>;404let AltFmtType = IS_ALTFMT in405 def PseudoSF_MM_F_F_ALT : VPseudoSF_MatMul_FRM<TRM2>;406 407foreach e1 = [5, 4] in408 foreach e2 = [5, 4] in409 def PseudoSF_MM_E # e1 # M # !sub(7, e1) # _E # e2 # M # !sub(7, e2)410 : VPseudoSF_MatMul_FRM<TRM4>;411 412let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {413 let HasVLOp = 1, HasTmOp = 1, HasTWidenOp = 1, HasSEWOp = 1 in414 def PseudoSF_VTZERO_T415 : RISCVVPseudo<(outs),416 (ins TR:$rd, AVL:$atm, AVL:$atn, ixlenimm:$sew,417 ixlenimm:$twiden)>;418 def PseudoSF_VTDISCARD : RISCVVPseudo<(outs), (ins), []>;419}420 421class VPatXSfmmTileStore<string intrinsic_name,422 string inst_name,423 int log2sew> :424 Pat<(!cast<Intrinsic>(intrinsic_name)425 (XLenVT GPR:$rs2),426 (XLenVT GPR:$rs1),427 (XLenVT AVL:$tn)),428 (!cast<Instruction>(inst_name)429 (XLenVT GPR:$rs2),430 (XLenVT GPR:$rs1),431 GPR:$tn, log2sew, 1)>;432 433class VPatXSfmmTileMove_T_V<string intrinsic_name,434 string inst_name,435 ValueType reg_type,436 int log2sew> :437 Pat<(!cast<Intrinsic>(intrinsic_name)438 (XLenVT GPR:$rs1),439 (reg_type VRM8:$vs2),440 (XLenVT AVL:$atn)),441 (!cast<Instruction>(inst_name)442 (XLenVT GPR:$rs1),443 (reg_type VRM8:$vs2),444 GPR:$atn, log2sew, 1)>;445 446class VPatXSfmmTileMove_V_T<string intrinsic_name,447 string inst_name,448 ValueType result_type,449 int log2sew> :450 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)451 (XLenVT GPR:$rs1),452 (XLenVT AVL:$atn))),453 (!cast<Instruction>(inst_name)454 (XLenVT GPR:$rs1),455 GPR:$atn, log2sew, 1)>;456 457class VPatXSfmmVTDiscard<string intrinsic_name,458 string inst_name> :459 Pat<(!cast<Intrinsic>(intrinsic_name)),460 (!cast<Instruction>(inst_name))>;461 462foreach eew = [8, 16, 32, 64] in463 def : VPatXSfmmTileStore<"int_riscv_sf_vste" # eew, "PseudoSF_VSTE" # eew, !logtwo(eew)>;464 465foreach vti = [VI8M8, VI16M8, VI32M8, VI64M8, VF16M8, VF32M8, VF64M8, VBF16M8] in {466 def : VPatXSfmmTileMove_T_V<"int_riscv_sf_vtmv_t_v", "PseudoSF_VTMV_T_V", vti.Vector, vti.Log2SEW>;467 def : VPatXSfmmTileMove_V_T<"int_riscv_sf_vtmv_v_t", "PseudoSF_VTMV_V_T", vti.Vector, vti.Log2SEW>;468}469 470def : VPatXSfmmVTDiscard<"int_riscv_sf_vtdiscard", "PseudoSF_VTDISCARD">;471