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1//===-- RISCVInstrInfoXTHead.td ----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the vendor extensions defined by T-Head of Alibaba.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// T-HEAD specific DAG Nodes.15//===----------------------------------------------------------------------===//16 17def SDT_LoadPair : SDTypeProfile<2, 2, [SDTCisSameAs<0, 1>,18 SDTCisSameAs<1, 3>,19 SDTCisPtrTy<2>,20 SDTCisVT<3, XLenVT>]>;21def SDT_StorePair : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,22 SDTCisSameAs<1, 3>,23 SDTCisPtrTy<2>,24 SDTCisVT<3, XLenVT>]>;25 26def th_lwud : RVSDNode<"TH_LWUD", SDT_LoadPair,27 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;28def th_lwd : RVSDNode<"TH_LWD", SDT_LoadPair,29 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;30def th_ldd : RVSDNode<"TH_LDD", SDT_LoadPair,31 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;32def th_swd : RVSDNode<"TH_SWD", SDT_StorePair,33 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;34def th_sdd : RVSDNode<"TH_SDD", SDT_StorePair,35 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;36 37def ImmThreeAsmOperand : AsmOperandClass {38 let Name = "ImmThree";39 let RenderMethod = "addImmOperands";40 let DiagnosticType = !strconcat("Invalid", Name);41 let DiagnosticString = "operand must be constant 3";42}43 44def immthree : RISCVOp {45 let ParserMatchClass = ImmThreeAsmOperand;46 let OperandType = "OPERAND_THREE";47 let DecoderMethod = "decodeImmThreeOperand";48}49 50def ImmFourAsmOperand : AsmOperandClass {51 let Name = "ImmFour";52 let RenderMethod = "addImmOperands";53 let DiagnosticType = !strconcat("Invalid", Name);54 let DiagnosticString = "operand must be constant 4";55}56 57def immfour : RISCVOp {58 let ParserMatchClass = ImmFourAsmOperand;59 let OperandType = "OPERAND_FOUR";60 let DecoderMethod = "decodeImmFourOperand";61}62 63def tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;64 65//===----------------------------------------------------------------------===//66// Instruction class templates67//===----------------------------------------------------------------------===//68 69class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,70 string opcodestr, string argstr>71 : RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {72 let Inst{26} = 0;73 let Inst{6-0} = OPC_CUSTOM_0.Value;74 let DecoderNamespace = "XTHead";75}76 77class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,78 string opcodestr, string argstr>79 : RVInstVX<funct6, opv, outs, ins, opcodestr, argstr> {80 let Inst{26} = 1;81 let Inst{6-0} = OPC_CUSTOM_0.Value;82 let DecoderNamespace = "XTHead";83}84 85let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {86// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)87class THVdotALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr,88 bit EarlyClobber>89 : THInstVdotVV<funct6, opv, (outs VR:$vd_wb),90 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),91 opcodestr, "$vd, $vs1, $vs2$vm"> {92 let Constraints = !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb",93 "$vd = $vd_wb");94}95 96// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)97class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,98 bit EarlyClobber>99 : THInstVdotVX<funct6, opv, (outs VR:$vd_wb),100 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),101 opcodestr, "$vd, $rs1, $vs2$vm"> {102 let Constraints = !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb",103 "$vd = $vd_wb");104}105} // hasSideEffects = 0, mayLoad = 0, mayStore = 0106 107let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in108class THShiftALU_rri<bits<3> funct3, string opcodestr>109 : RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),110 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),111 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {112 bits<2> uimm2;113 let Inst{31-27} = 0;114 let Inst{26-25} = uimm2;115}116 117let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in118class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>119 : RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),120 (ins GPR:$rs1, uimmlog2xlen:$shamt),121 opcodestr, "$rd, $rs1, $shamt">;122 123let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in124class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>125 : RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),126 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),127 opcodestr, "$rd, $rs1, $msb, $lsb"> {128 bits<6> msb;129 bits<6> lsb;130 let Inst{31-26} = msb;131 let Inst{25-20} = lsb;132}133 134let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in135class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>136 : RVInstIUnary<{funct5, funct2, 0b00000}, 0b001, OPC_CUSTOM_0,137 (outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;138 139let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in140class THShiftW_ri<bits<7> funct7, bits<3> funct3, string opcodestr>141 : RVInstIShiftW<funct7, funct3, OPC_CUSTOM_0, (outs GPR:$rd),142 (ins GPR:$rs1, uimm5:$shamt),143 opcodestr, "$rd, $rs1, $shamt">;144 145let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in146class THCondMov_rr<bits<7> funct7, string opcodestr>147 : RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),148 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),149 opcodestr, "$rd, $rs1, $rs2"> {150 let Constraints = "$rd_wb = $rd";151}152 153let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in154class THMulAccumulate_rr<bits<7> funct7, string opcodestr>155 : RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),156 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),157 opcodestr, "$rd, $rs1, $rs2"> {158 let Constraints = "$rd_wb = $rd";159}160 161let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in162class THLoadPair<bits<5> funct5, string opcodestr, Operand consttype>163 : RVInstRBase<0b100, OPC_CUSTOM_0,164 (outs GPR:$rd, GPR:$rs2),165 (ins GPR:$rs1, uimm2:$uimm2, consttype:$const3or4),166 opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {167 bits<2> uimm2;168 bits<0> const3or4;169 let Inst{31-27} = funct5;170 let Inst{26-25} = uimm2;171 let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";172}173 174let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in175class THStorePair<bits<5> funct5, string opcodestr, Operand consttype>176 : RVInstRBase<0b101, OPC_CUSTOM_0, (outs),177 (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, consttype:$const3or4),178 opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {179 bits<2> uimm2;180 bits<0> const3or4;181 let Inst{31-27} = funct5;182 let Inst{26-25} = uimm2;183}184 185let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in186class THCacheInst_r<bits<5> funct5, string opcodestr>187 : RVInstR<0b0000001, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1),188 opcodestr, "$rs1"> {189 let rd = 0;190 let rs2 = funct5;191}192 193let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in194class THCacheInst_rr<bits<7> funct7, string opcodestr>195 : RVInstR<funct7, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1, GPR:$rs2),196 opcodestr, "$rs1, $rs2"> {197 let rd = 0;198}199 200let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in201class THCacheInst_void<bits<5> funct5, string opcodestr>202 : RVInstR<0b0000000, 0, OPC_CUSTOM_0, (outs), (ins), opcodestr, ""> {203 let rd = 0;204 let rs1 = 0;205 let rs2 = funct5;206}207 208let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {209class THLoadIndexed<RegisterClass Ty, bits<5> funct5, string opcodestr>210 : RVInstRBase<!if(!eq(Ty, GPR), 0b100, 0b110), OPC_CUSTOM_0,211 (outs Ty:$rd), (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),212 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {213 bits<2> uimm2;214 let Inst{31-27} = funct5;215 let Inst{26-25} = uimm2;216}217 218class THLoadUpdate<bits<5> funct5, string opcodestr>219 : RVInstIBase<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),220 (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),221 opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {222 bits<5> simm5;223 bits<2> uimm2;224 let Inst{31-27} = funct5;225 let Inst{26-25} = uimm2;226 let Inst{24-20} = simm5;227 let Constraints = "@earlyclobber $rd, $rs1_wb = $rs1";228}229}230 231let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {232class THStoreIndexed<RegisterClass StTy, bits<5> funct5, string opcodestr>233 : RVInstRBase<!if(!eq(StTy, GPR), 0b101, 0b111), OPC_CUSTOM_0,234 (outs), (ins StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2),235 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {236 bits<2> uimm2;237 let Inst{31-27} = funct5;238 let Inst{26-25} = uimm2;239}240 241class THStoreUpdate<bits<5> funct5, string opcodestr>242 : RVInstIBase<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),243 (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),244 opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {245 bits<5> simm5;246 bits<2> uimm2;247 let Inst{31-27} = funct5;248 let Inst{26-25} = uimm2;249 let Inst{24-20} = simm5;250 let Constraints = "$rs1_up = $rs1";251}252}253 254//===----------------------------------------------------------------------===//255// Combination of instruction classes.256// Use these multiclasses to define instructions more easily.257//===----------------------------------------------------------------------===//258 259multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {260 let RVVConstraint = WidenV, ElementsDependOn = EltDepsVLMask in261 def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx", EarlyClobber=1>;262}263 264multiclass THVdotVMAQA<string opcodestr, bits<6> funct6>265 : THVdotVMAQA_VX<opcodestr, funct6> {266 let RVVConstraint = WidenV, ElementsDependOn = EltDepsVLMask in267 def _VV : THVdotALUrVV<funct6, OPMVX, opcodestr # ".vv", EarlyClobber=1>;268}269 270//===----------------------------------------------------------------------===//271// Instructions272//===----------------------------------------------------------------------===//273 274let DecoderNamespace = "XTHead" in {275let Predicates = [HasVendorXTHeadBa] in276def TH_ADDSL : THShiftALU_rri<0b001, "th.addsl">,277 Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;278 279let Predicates = [HasVendorXTHeadBb] in {280def TH_SRRI : THShift_ri<0b00010, 0b001, "th.srri">;281def TH_EXT : THBitfieldExtract_rii<0b010, "th.ext">;282def TH_EXTU : THBitfieldExtract_rii<0b011, "th.extu">;283def TH_FF0 : THRev_r<0b10000, 0b10, "th.ff0">;284def TH_FF1 : THRev_r<0b10000, 0b11, "th.ff1">;285def TH_REV : THRev_r<0b10000, 0b01, "th.rev">;286def TH_TSTNBZ : THRev_r<0b10000, 0b00, "th.tstnbz">;287} // Predicates = [HasVendorXTHeadBb]288 289let Predicates = [HasVendorXTHeadBb, IsRV64],290 IsSignExtendingOpW = 1 in {291def TH_SRRIW : THShiftW_ri<0b0001010, 0b001, "th.srriw">;292def TH_REVW : THRev_r<0b10010, 0b00, "th.revw">;293} // Predicates = [HasVendorXTHeadBb, IsRV64]294 295let Predicates = [HasVendorXTHeadBs],296 IsSignExtendingOpW = 1 in297def TH_TST : THShift_ri<0b10001, 0b001, "th.tst">,298 Sched<[WriteSingleBitImm, ReadSingleBitImm]>;299 300let Predicates = [HasVendorXTHeadCondMov] in {301def TH_MVEQZ : THCondMov_rr<0b0100000, "th.mveqz">;302def TH_MVNEZ : THCondMov_rr<0b0100001, "th.mvnez">;303} // Predicates = [HasVendorXTHeadCondMov]304 305let Predicates = [HasVendorXTHeadMac] in {306def TH_MULA : THMulAccumulate_rr<0b0010000, "th.mula">;307def TH_MULS : THMulAccumulate_rr<0b0010001, "th.muls">;308} // Predicates = [HasVendorXTHeadMac]309 310let Predicates = [HasVendorXTHeadMac], IsSignExtendingOpW = 1 in {311def TH_MULAH : THMulAccumulate_rr<0b0010100, "th.mulah">;312def TH_MULSH : THMulAccumulate_rr<0b0010101, "th.mulsh">;313} // Predicates = [HasVendorXTHeadMac], IsSignExtendingOpW = 1314 315let Predicates = [HasVendorXTHeadMac, IsRV64], IsSignExtendingOpW = 1 in {316def TH_MULAW : THMulAccumulate_rr<0b0010010, "th.mulaw">;317def TH_MULSW : THMulAccumulate_rr<0b0010011, "th.mulsw">;318} // Predicates = [HasVendorXTHeadMac, IsRV64]319 320let Predicates = [HasVendorXTHeadMemPair] in {321def TH_LWUD : THLoadPair<0b11110, "th.lwud", immthree>,322 Sched<[WriteLDW, WriteLDW, ReadMemBase]>;323def TH_SWD : THStorePair<0b11100, "th.swd", immthree>,324 Sched<[WriteSTW, WriteSTW, ReadStoreData, ReadMemBase]>;325let IsSignExtendingOpW = 1 in326def TH_LWD : THLoadPair<0b11100, "th.lwd", immthree>,327 Sched<[WriteLDW, WriteLDW, ReadMemBase]>;328}329 330let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {331def TH_LDD : THLoadPair<0b11111, "th.ldd", immfour>,332 Sched<[WriteLDD, WriteLDD, ReadMemBase]>;333def TH_SDD : THStorePair<0b11111, "th.sdd", immfour>,334 Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;335}336 337let Predicates = [HasVendorXTHeadMemIdx] in {338// T-Head Load/Store + Update instructions.339def TH_LBIA : THLoadUpdate<0b00011, "th.lbia">,340 Sched<[WriteLDB, ReadMemBase]>;341def TH_LBIB : THLoadUpdate<0b00001, "th.lbib">,342 Sched<[WriteLDB, ReadMemBase]>;343def TH_LBUIA : THLoadUpdate<0b10011, "th.lbuia">,344 Sched<[WriteLDB, ReadMemBase]>;345def TH_LBUIB : THLoadUpdate<0b10001, "th.lbuib">,346 Sched<[WriteLDB, ReadMemBase]>;347 348def TH_LHIA : THLoadUpdate<0b00111, "th.lhia">,349 Sched<[WriteLDH, ReadMemBase]>;350def TH_LHIB : THLoadUpdate<0b00101, "th.lhib">,351 Sched<[WriteLDH, ReadMemBase]>;352def TH_LHUIA : THLoadUpdate<0b10111, "th.lhuia">,353 Sched<[WriteLDH, ReadMemBase]>;354def TH_LHUIB : THLoadUpdate<0b10101, "th.lhuib">,355 Sched<[WriteLDH, ReadMemBase]>;356 357def TH_LWIA : THLoadUpdate<0b01011, "th.lwia">,358 Sched<[WriteLDW, ReadMemBase]>;359def TH_LWIB : THLoadUpdate<0b01001, "th.lwib">,360 Sched<[WriteLDW, ReadMemBase]>;361 362def TH_SBIA : THStoreUpdate<0b00011, "th.sbia">,363 Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;364def TH_SBIB : THStoreUpdate<0b00001, "th.sbib">,365 Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;366 367def TH_SHIA : THStoreUpdate<0b00111, "th.shia">,368 Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;369def TH_SHIB : THStoreUpdate<0b00101, "th.shib">,370 Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;371 372def TH_SWIA : THStoreUpdate<0b01011, "th.swia">,373 Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;374def TH_SWIB : THStoreUpdate<0b01001, "th.swib">,375 Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;376 377// T-Head Load/Store Indexed instructions.378def TH_LRB : THLoadIndexed<GPR, 0b00000, "th.lrb">,379 Sched<[WriteLDB, ReadMemBase]>;380def TH_LRBU : THLoadIndexed<GPR, 0b10000, "th.lrbu">,381 Sched<[WriteLDB, ReadMemBase]>;382def TH_LURB : THLoadIndexed<GPR, 0b00010, "th.lurb">,383 Sched<[WriteLDB, ReadMemBase]>;384def TH_LURBU : THLoadIndexed<GPR, 0b10010, "th.lurbu">,385 Sched<[WriteLDB, ReadMemBase]>;386 387def TH_LRH : THLoadIndexed<GPR, 0b00100, "th.lrh">,388 Sched<[WriteLDH, ReadMemBase]>;389def TH_LRHU : THLoadIndexed<GPR, 0b10100, "th.lrhu">,390 Sched<[WriteLDH, ReadMemBase]>;391def TH_LURH : THLoadIndexed<GPR, 0b00110, "th.lurh">,392 Sched<[WriteLDB, ReadMemBase]>;393def TH_LURHU : THLoadIndexed<GPR, 0b10110, "th.lurhu">,394 Sched<[WriteLDB, ReadMemBase]>;395 396def TH_LRW : THLoadIndexed<GPR, 0b01000, "th.lrw">,397 Sched<[WriteLDW, ReadMemBase]>;398def TH_LURW : THLoadIndexed<GPR, 0b01010, "th.lurw">,399 Sched<[WriteLDB, ReadMemBase]>;400 401def TH_SRB : THStoreIndexed<GPR, 0b00000, "th.srb">,402 Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;403def TH_SURB : THStoreIndexed<GPR, 0b00010, "th.surb">,404 Sched<[WriteLDB, ReadMemBase]>;405 406def TH_SRH : THStoreIndexed<GPR, 0b00100, "th.srh">,407 Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;408def TH_SURH : THStoreIndexed<GPR, 0b00110, "th.surh">,409 Sched<[WriteLDB, ReadMemBase]>;410 411def TH_SRW : THStoreIndexed<GPR, 0b01000, "th.srw">,412 Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;413def TH_SURW : THStoreIndexed<GPR, 0b01010, "th.surw">,414 Sched<[WriteLDB, ReadMemBase]>;415}416 417let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {418// T-Head Load/Store + Update instructions.419def TH_LWUIA : THLoadUpdate<0b11011, "th.lwuia">,420 Sched<[WriteLDH, ReadMemBase]>;421def TH_LWUIB : THLoadUpdate<0b11001, "th.lwuib">,422 Sched<[WriteLDH, ReadMemBase]>;423 424def TH_LDIA : THLoadUpdate<0b01111, "th.ldia">,425 Sched<[WriteLDW, ReadMemBase]>;426def TH_LDIB : THLoadUpdate<0b01101, "th.ldib">,427 Sched<[WriteLDW, ReadMemBase]>;428 429def TH_SDIA : THStoreUpdate<0b01111, "th.sdia">,430 Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;431def TH_SDIB : THStoreUpdate<0b01101, "th.sdib">,432 Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;433 434// T-Head Load/Store Indexed instructions.435def TH_LRWU : THLoadIndexed<GPR, 0b11000, "th.lrwu">,436 Sched<[WriteLDW, ReadMemBase]>;437def TH_LURWU : THLoadIndexed<GPR, 0b11010, "th.lurwu">,438 Sched<[WriteLDB, ReadMemBase]>;439 440def TH_LRD : THLoadIndexed<GPR, 0b01100, "th.lrd">,441 Sched<[WriteLDW, ReadMemBase]>;442def TH_LURD : THLoadIndexed<GPR, 0b01110, "th.lurd">,443 Sched<[WriteLDB, ReadMemBase]>;444 445def TH_SRD : THStoreIndexed<GPR, 0b01100, "th.srd">,446 Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;447def TH_SURD : THStoreIndexed<GPR, 0b01110, "th.surd">,448 Sched<[WriteLDB, ReadMemBase]>;449}450 451// T-Head Load/Store Indexed instructions for floating point registers.452 453let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF] in {454def TH_FLRW : THLoadIndexed<FPR32, 0b01000, "th.flrw">,455 Sched<[WriteFLD32, ReadFMemBase]>;456def TH_FSRW : THStoreIndexed<FPR32, 0b01000, "th.fsrw">,457 Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]>;458}459 460let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD] in {461def TH_FLRD : THLoadIndexed<FPR64, 0b01100, "th.flrd">,462 Sched<[WriteFLD64, ReadFMemBase]>;463def TH_FSRD : THStoreIndexed<FPR64, 0b01100, "th.fsrd">,464 Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]>;465}466 467let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF, IsRV64] in {468def TH_FLURW : THLoadIndexed<FPR32, 0b01010, "th.flurw">,469 Sched<[WriteFLD32, ReadFMemBase]>;470def TH_FSURW : THStoreIndexed<FPR32, 0b01010, "th.fsurw">,471 Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]>;472}473 474let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD, IsRV64] in {475def TH_FLURD : THLoadIndexed<FPR64, 0b01110, "th.flurd">,476 Sched<[WriteFLD64, ReadFMemBase]>;477def TH_FSURD : THStoreIndexed<FPR64, 0b01110, "th.fsurd">,478 Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]>;479}480} // DecoderNamespace = "XTHead"481 482let Predicates = [HasVendorXTHeadVdot] in {483defm TH_VMAQA : THVdotVMAQA<"th.vmaqa", 0b100000>;484defm TH_VMAQAU : THVdotVMAQA<"th.vmaqau", 0b100010>;485defm TH_VMAQASU : THVdotVMAQA<"th.vmaqasu", 0b100100>;486defm TH_VMAQAUS : THVdotVMAQA_VX<"th.vmaqaus",0b100110>;487}488 489// Associate LMUL with tablegen records of register classes.490def THVdotV_M1 : LMULInfo<0b000, 8, VR, VR, VR, VR, VR, "M1">;491def THVdotV_M2 : LMULInfo<0b001, 16, VRM2, VRM2, VR, VR, VR, "M2">;492def THVdotV_M4 : LMULInfo<0b010, 32, VRM4, VRM4, VRM2, VR, VR, "M4">;493def THVdotV_M8 : LMULInfo<0b011, 64, VRM8, VRM8, VRM4, VRM2, VR, "M8">;494 495defvar MxListTHVdot = [V_MF2, THVdotV_M1, THVdotV_M2, THVdotV_M4, THVdotV_M8];496 497defset list<VTypeInfoToWide> AllQuadWidenableInt8NoVLMulVectors = {498 def : VTypeInfoToWide<VI8MF2, VI32MF2>;499 def : VTypeInfoToWide<VI8M1, VI32M1>;500 def : VTypeInfoToWide<VI8M2, VI32M2>;501 def : VTypeInfoToWide<VI8M4, VI32M4>;502 def : VTypeInfoToWide<VI8M8, VI32M8>;503}504 505//===----------------------------------------------------------------------===//506// Combination of instruction classes.507// Use these multiclasses to define instructions more easily.508//===----------------------------------------------------------------------===//509 510multiclass VPseudoVMAQA_VV_VX {511 foreach m = MxListTHVdot in {512 // TODO: Add Sched513 defm "" : VPseudoTernaryW_VV<m>;514 defm "" : VPseudoTernaryW_VX<m>;515 }516}517 518multiclass VPseudoVMAQA_VX {519 foreach m = MxListTHVdot in {520 // TODO: Add Sched521 defm "" : VPseudoTernaryW_VX<m>;522 }523}524 525multiclass VPatTernaryVMAQA_VV<string intrinsic, string instruction,526 list<VTypeInfoToWide> vtilist> {527 foreach vtiToWti = vtilist in {528 defvar vti = vtiToWti.Vti;529 defvar wti = vtiToWti.Wti;530 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",531 wti.Vector, vti.Vector, vti.Vector,532 vti.Mask, wti.Log2SEW, vti.LMul,533 wti.RegClass, vti.RegClass, vti.RegClass>;534 }535}536 537multiclass VPatTernaryVMAQA_VX<string intrinsic, string instruction,538 list<VTypeInfoToWide> vtilist> {539 foreach vtiToWti = vtilist in {540 defvar vti = vtiToWti.Vti;541 defvar wti = vtiToWti.Wti;542 defm : VPatTernaryWithPolicy<intrinsic, instruction,543 "V"#vti.ScalarSuffix,544 wti.Vector, vti.Scalar, vti.Vector,545 vti.Mask, wti.Log2SEW, vti.LMul,546 wti.RegClass, vti.ScalarRegClass, vti.RegClass>;547 }548}549 550multiclass VPatTernaryVMAQA_VV_VX<string intrinsic, string instruction,551 list<VTypeInfoToWide> vtilist>552 : VPatTernaryVMAQA_VV<intrinsic, instruction, vtilist>,553 VPatTernaryVMAQA_VX<intrinsic, instruction, vtilist>;554 555//===----------------------------------------------------------------------===//556// Pseudo-instructions and codegen patterns557//===----------------------------------------------------------------------===//558 559let Predicates = [HasVendorXTHeadBa] in {560def : Pat<(add_like_non_imm12 (shl GPR:$rs2, uimm2:$uimm2), (XLenVT GPR:$rs1)),561 (TH_ADDSL GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;562def : Pat<(XLenVT (riscv_shl_add GPR:$rs2, tuimm2:$uimm2, GPR:$rs1)),563 (TH_ADDSL GPR:$rs1, GPR:$rs2, tuimm2:$uimm2)>;564 565// Reuse complex patterns from StdExtZba566def : Pat<(add_like_non_imm12 sh1add_op:$rs2, (XLenVT GPR:$rs1)),567 (TH_ADDSL GPR:$rs1, sh1add_op:$rs2, 1)>;568def : Pat<(add_like_non_imm12 sh2add_op:$rs2, (XLenVT GPR:$rs1)),569 (TH_ADDSL GPR:$rs1, sh2add_op:$rs2, 2)>;570def : Pat<(add_like_non_imm12 sh3add_op:$rs2, (XLenVT GPR:$rs1)),571 (TH_ADDSL GPR:$rs1, sh3add_op:$rs2, 3)>;572 573def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy4:$i),574 (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), CSImm12MulBy4:$i)), 2)>;575def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy8:$i),576 (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), CSImm12MulBy8:$i)), 3)>;577} // Predicates = [HasVendorXTHeadBa]578 579let Predicates = [HasVendorXTHeadBb] in {580def : PatGprImm<rotr, TH_SRRI, uimmlog2xlen>;581// There's no encoding for a rotate-left-immediate in X-THead-Bb, as582// it can be implemented with th.srri by negating the immediate.583def : Pat<(rotl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt),584 (TH_SRRI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;585def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (TH_EXT GPR:$rs1, 15, 0)>;586def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (TH_EXT GPR:$rs1, 7, 0)>;587def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (TH_EXT GPR:$rs1, 0, 0)>;588def : PatGpr<ctlz, TH_FF1>;589def : Pat<(XLenVT (ctlz (xor (XLenVT GPR:$rs1), -1))), (TH_FF0 GPR:$rs1)>;590def : PatGpr<bswap, TH_REV>;591} // Predicates = [HasVendorXTHeadBb]592 593let Predicates = [HasVendorXTHeadBb, IsRV64] in {594def : PatGprImm<riscv_rorw, TH_SRRIW, uimm5>;595def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),596 (TH_SRRIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;597def : Pat<(i64 (sra (bswap GPR:$rs1), (i64 32))),598 (TH_REVW GPR:$rs1)>;599def : Pat<(binop_allwusers<srl> (bswap GPR:$rs1), (i64 32)),600 (TH_REVW GPR:$rs1)>;601} // Predicates = [HasVendorXTHeadBb, IsRV64]602 603let Predicates = [HasVendorXTHeadBs] in {604def : Pat<(and (srl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt), 1),605 (TH_TST GPR:$rs1, uimmlog2xlen:$shamt)>;606def : Pat<(XLenVT (seteq (and (XLenVT GPR:$rs1), SingleBitSetMask:$mask), 0)),607 (TH_TST (XLenVT (XORI GPR:$rs1, -1)), SingleBitSetMask:$mask)>;608} // Predicates = [HasVendorXTHeadBs]609 610let Predicates = [HasVendorXTHeadCondMov] in {611def : Pat<(select (XLenVT GPR:$cond), (XLenVT GPR:$a), (XLenVT GPR:$b)),612 (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;613def : Pat<(select (XLenVT GPR:$cond), (XLenVT GPR:$a), (XLenVT 0)),614 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;615def : Pat<(select (XLenVT GPR:$cond), (XLenVT 0), (XLenVT GPR:$b)),616 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;617 618def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT GPR:$b)),619 (TH_MVNEZ GPR:$a, GPR:$b, GPR:$cond)>;620def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT GPR:$b)),621 (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;622def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT 0)),623 (TH_MVNEZ GPR:$a, (XLenVT X0), GPR:$cond)>;624def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT 0)),625 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;626def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT 0), (XLenVT GPR:$b)),627 (TH_MVEQZ GPR:$b, (XLenVT X0), GPR:$cond)>;628def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT 0), (XLenVT GPR:$b)),629 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;630} // Predicates = [HasVendorXTHeadCondMov]631 632let Predicates = [HasVendorXTHeadMac] in {633def : Pat<(add GPR:$rd, (mul (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))),634 (TH_MULA GPR:$rd, GPR:$rs1, GPR:$rs2)>;635def : Pat<(sub GPR:$rd, (mul (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))),636 (TH_MULS GPR:$rd, GPR:$rs1, GPR:$rs2)>;637} // Predicates = [HasVendorXTHeadMac]638 639let Predicates = [HasVendorXTHeadMac, IsRV64] in {640// mulaw, mulsw are available only in RV64.641def : Pat<(binop_allwusers<add> GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),642 (TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;643def : Pat<(binop_allwusers<sub> GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),644 (TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;645// mulah, mulsh produce a sign-extended result.646def : Pat<(binop_allwusers<add> GPR:$rd, (mul647 (sexti16 (i64 GPR:$rs1)),648 (sexti16 (i64 GPR:$rs2)))),649 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;650def : Pat<(binop_allwusers<sub> GPR:$rd, (mul651 (sexti16 (i64 GPR:$rs1)),652 (sexti16 (i64 GPR:$rs2)))),653 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;654} // Predicates = [HasVendorXTHeadMac, IsRV64]655 656let Predicates = [HasVendorXTHeadMac, IsRV32] in {657def : Pat<(i32 (add GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),658 (sexti16 (i32 GPR:$rs2))))),659 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;660def : Pat<(i32 (sub GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),661 (sexti16 (i32 GPR:$rs2))))),662 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;663} // Predicates = [HasVendorXTHeadMac, IsRV32]664 665let Predicates = [HasVendorXTHeadVdot] in {666defm PseudoTH_VMAQA : VPseudoVMAQA_VV_VX;667defm PseudoTH_VMAQAU : VPseudoVMAQA_VV_VX;668defm PseudoTH_VMAQASU : VPseudoVMAQA_VV_VX;669defm PseudoTH_VMAQAUS : VPseudoVMAQA_VX;670}671 672let Predicates = [HasVendorXTHeadVdot] in {673defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa", "PseudoTH_VMAQA",674 AllQuadWidenableInt8NoVLMulVectors>;675defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTH_VMAQAU",676 AllQuadWidenableInt8NoVLMulVectors>;677defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTH_VMAQASU",678 AllQuadWidenableInt8NoVLMulVectors>;679defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus", "PseudoTH_VMAQAUS",680 AllQuadWidenableInt8NoVLMulVectors>;681}682 683def uimm2_3_XFORM : SDNodeXForm<imm, [{684 return CurDAG->getTargetConstant((N->getZExtValue() >> 3) & 0x3,685 SDLoc(N), Subtarget->getXLenVT());686}]>;687 688def uimm2_3 : Operand<XLenVT>, ImmLeaf<XLenVT, [{689 return isShiftedUInt<2, 3>(Imm);690}], uimm2_3_XFORM>;691 692def uimm2_4_XFORM : SDNodeXForm<imm, [{693 return CurDAG->getTargetConstant((N->getZExtValue() >> 4) & 0x3,694 SDLoc(N), Subtarget->getXLenVT());695}]>;696 697def uimm2_4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{698 return isShiftedUInt<2, 4>(Imm);699}], uimm2_4_XFORM>;700 701let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {702def : Pat<(th_lwud GPR:$rs1, (i64 uimm2_3:$uimm2_3)),703 (TH_LWUD GPR:$rs1, uimm2_3:$uimm2_3, 3)>;704def : Pat<(th_ldd GPR:$rs1, (i64 uimm2_4:$uimm2_4)),705 (TH_LDD GPR:$rs1, uimm2_4:$uimm2_4, 4)>;706 707def : Pat<(th_sdd (i64 GPR:$rd1), GPR:$rd2, GPR:$rs1, uimm2_4:$uimm2_4),708 (TH_SDD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_4:$uimm2_4, 4)>;709}710 711let Predicates = [HasVendorXTHeadMemPair] in {712 def : Pat<(th_lwd GPR:$rs1, uimm2_3:$uimm2_3), (TH_LWD GPR:$rs1, uimm2_3:$uimm2_3, 3)>;713 def : Pat<(th_swd GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3),714 (TH_SWD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3, 3)>;715}716 717let Predicates = [HasVendorXTHeadCmo], DecoderNamespace = "XTHead" in {718def TH_DCACHE_CSW : THCacheInst_r<0b00001, "th.dcache.csw">;719def TH_DCACHE_ISW : THCacheInst_r<0b00010, "th.dcache.isw">;720def TH_DCACHE_CISW : THCacheInst_r<0b00011, "th.dcache.cisw">;721def TH_DCACHE_CVAL1 : THCacheInst_r<0b00100, "th.dcache.cval1">;722def TH_DCACHE_CVA : THCacheInst_r<0b00101, "th.dcache.cva">;723def TH_DCACHE_IVA : THCacheInst_r<0b00110, "th.dcache.iva">;724def TH_DCACHE_CIVA : THCacheInst_r<0b00111, "th.dcache.civa">;725def TH_DCACHE_CPAL1 : THCacheInst_r<0b01000, "th.dcache.cpal1">;726def TH_DCACHE_CPA : THCacheInst_r<0b01001, "th.dcache.cpa">;727def TH_DCACHE_IPA : THCacheInst_r<0b01010, "th.dcache.ipa">;728def TH_DCACHE_CIPA : THCacheInst_r<0b01011, "th.dcache.cipa">;729def TH_ICACHE_IVA : THCacheInst_r<0b10000, "th.icache.iva">;730def TH_ICACHE_IPA : THCacheInst_r<0b11000, "th.icache.ipa">;731 732def TH_DCACHE_CALL : THCacheInst_void<0b00001, "th.dcache.call">;733def TH_DCACHE_IALL : THCacheInst_void<0b00010, "th.dcache.iall">;734def TH_DCACHE_CIALL : THCacheInst_void<0b00011, "th.dcache.ciall">;735def TH_ICACHE_IALL : THCacheInst_void<0b10000, "th.icache.iall">;736def TH_ICACHE_IALLS : THCacheInst_void<0b10001, "th.icache.ialls">;737def TH_L2CACHE_CALL : THCacheInst_void<0b10101, "th.l2cache.call">;738def TH_L2CACHE_IALL : THCacheInst_void<0b10110, "th.l2cache.iall">;739def TH_L2CACHE_CIALL : THCacheInst_void<0b10111, "th.l2cache.ciall">;740}741 742let Predicates = [HasVendorXTHeadSync], DecoderNamespace = "XTHead" in {743def TH_SFENCE_VMAS : THCacheInst_rr<0b0000010, "th.sfence.vmas">;744def TH_SYNC : THCacheInst_void<0b11000, "th.sync">;745def TH_SYNC_S : THCacheInst_void<0b11001, "th.sync.s">;746def TH_SYNC_I : THCacheInst_void<0b11010, "th.sync.i">;747def TH_SYNC_IS : THCacheInst_void<0b11011, "th.sync.is">;748}749 750def AddrRegRegScale3 : AddrRegRegScale<3>;751def AddrRegZextRegScale3 : AddrRegZextRegScale<3>;752 753multiclass LdIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT> {754def : Pat<(vt (LoadOp (AddrRegRegScale3 (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2))),755 (Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;756}757 758multiclass LdZextIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = i64> {759def : Pat<(vt (LoadOp (AddrRegZextRegScale3 (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2))),760 (Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;761}762 763multiclass StIdxPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,764 ValueType vt = XLenVT> {765def : Pat<(StoreOp (vt StTy:$rd),766 (AddrRegRegScale3 (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2)),767 (Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;768}769 770multiclass StZextIdxPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,771 ValueType vt = i64> {772def : Pat<(StoreOp (vt StTy:$rd),773 (AddrRegZextRegScale3 (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2)),774 (Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;775}776 777let Predicates = [HasVendorXTHeadMemIdx] in {778defm : LdIdxPat<extloadi8, TH_LRB>;779defm : LdIdxPat<sextloadi8, TH_LRB>;780defm : LdIdxPat<zextloadi8, TH_LRBU>;781 782defm : LdIdxPat<extloadi16, TH_LRH>;783defm : LdIdxPat<sextloadi16, TH_LRH>;784defm : LdIdxPat<zextloadi16, TH_LRHU>;785 786defm : StIdxPat<truncstorei8, TH_SRB, GPR>;787defm : StIdxPat<truncstorei16, TH_SRH, GPR>;788}789 790let Predicates = [HasVendorXTHeadMemIdx, IsRV32] in {791defm : LdIdxPat<load, TH_LRW, i32>;792defm : StIdxPat<store, TH_SRW, GPR, i32>;793}794 795let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {796defm : LdZextIdxPat<extloadi8, TH_LURB>;797defm : LdZextIdxPat<sextloadi8, TH_LURB>;798defm : LdZextIdxPat<zextloadi8, TH_LURBU>;799 800defm : LdZextIdxPat<extloadi16, TH_LURH>;801defm : LdZextIdxPat<sextloadi16, TH_LURH>;802defm : LdZextIdxPat<zextloadi16, TH_LURHU>;803 804defm : LdIdxPat<extloadi32, TH_LRW, i64>;805defm : LdIdxPat<sextloadi32, TH_LRW, i64>;806defm : LdIdxPat<zextloadi32, TH_LRWU, i64>;807 808defm : LdZextIdxPat<extloadi32, TH_LURW>;809defm : LdZextIdxPat<sextloadi32, TH_LURW>;810defm : LdZextIdxPat<zextloadi32, TH_LURWU>;811 812defm : LdIdxPat<load, TH_LRD, i64>;813defm : LdZextIdxPat<load, TH_LURD>;814 815defm : StZextIdxPat<truncstorei8, TH_SURB, GPR>;816defm : StZextIdxPat<truncstorei16, TH_SURH, GPR>;817defm : StIdxPat<truncstorei32, TH_SRW, GPR, i64>;818defm : StZextIdxPat<truncstorei32, TH_SURW, GPR, i64>;819defm : StIdxPat<store, TH_SRD, GPR, i64>;820defm : StZextIdxPat<store, TH_SURD, GPR>;821}822 823let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF] in {824defm : LdIdxPat<load, TH_FLRW, f32>;825defm : StIdxPat<store, TH_FSRW, FPR32, f32>;826}827 828let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD] in {829defm : LdIdxPat<load, TH_FLRD, f64>;830defm : StIdxPat<store, TH_FSRD, FPR64, f64>;831}832 833let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtF, IsRV64] in {834defm : LdZextIdxPat<load, TH_FLURW, f32>;835defm : StZextIdxPat<store, TH_FSURW, FPR32, f32>;836}837 838let Predicates = [HasVendorXTHeadFMemIdx, HasStdExtD, IsRV64] in {839defm : LdZextIdxPat<load, TH_FLURD, f64>;840defm : StZextIdxPat<store, TH_FSURD, FPR64, f64>;841}842 843def simm5shl2 : ComplexPattern<XLenVT, 2, "selectSimm5Shl2">;844 845multiclass StoreUpdatePat<PatFrag st, Instruction Inst, ValueType vt = XLenVT> {846def : Pat<(st (vt GPR:$rd), GPR:$rs1, (simm5shl2 simm5:$simm5, uimm2:$uimm2)),847 (Inst GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2)>;848}849 850let Predicates = [HasVendorXTHeadMemIdx] in {851defm : StoreUpdatePat<post_truncsti8, TH_SBIA>;852defm : StoreUpdatePat<pre_truncsti8, TH_SBIB>;853defm : StoreUpdatePat<post_truncsti16, TH_SHIA>;854defm : StoreUpdatePat<pre_truncsti16, TH_SHIB>;855 856defm : StoreUpdatePat<post_store, TH_SWIA, i32>;857defm : StoreUpdatePat<pre_store, TH_SWIB, i32>;858}859 860let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {861defm : StoreUpdatePat<post_truncsti32, TH_SWIA, i64>;862defm : StoreUpdatePat<pre_truncsti32, TH_SWIB, i64>;863defm : StoreUpdatePat<post_store, TH_SDIA, i64>;864defm : StoreUpdatePat<pre_store, TH_SDIB, i64>;865}866