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1//===---------------- RISCVInstrInfoXqccmp.td --------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes Qualcomm's Xqccmp extension.10//11// Xqccmp is broadly equivalent to (and incompatible with) Zcmp except the12// following changes:13//14// - The registers are pushed in the opposite order, so `ra` and `fp` are15// closest to the incoming stack pointer (to be compatible with the16// frame-pointer convention), and17//18// - There is a new `qc.cm.pushfp` instruction which is `qc.cm.push` but it sets19// `fp` to the incoming stack pointer value, as expected by the frame-pointer20// convention.21//22//===----------------------------------------------------------------------===//23 24//===----------------------------------------------------------------------===//25// Operand and SDNode transformation definitions.26//===----------------------------------------------------------------------===//27 28def RegListS0AsmOperand : AsmOperandClass {29 let Name = "RegListS0";30 let ParserMethod = "parseRegListS0";31 let RenderMethod = "addRegListOperands";32 let DiagnosticType = "InvalidRegListS0";33 let DiagnosticString = "operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}";34}35 36def reglist_s0 : RISCVOp<OtherVT> {37 let ParserMatchClass = RegListS0AsmOperand;38 let PrintMethod = "printRegList";39 let DecoderMethod = "decodeXqccmpRlistS0";40 let EncoderMethod = "getRlistS0OpValue";41 let MCOperandPredicate = [{42 int64_t Imm;43 if (!MCOp.evaluateAsConstantImm(Imm))44 return false;45 // 0~4 invalid for `qc.cm.pushfp`46 return isUInt<4>(Imm) && Imm >= RISCVZC::RA_S0;47 }];48 49 string OperandType = "OPERAND_RLIST_S0";50}51 52//===----------------------------------------------------------------------===//53// Instruction Formats54//===----------------------------------------------------------------------===//55 56//===----------------------------------------------------------------------===//57// Instruction Class Templates58//===----------------------------------------------------------------------===//59 60class RVInstXqccmpCPPPFP<bits<5> funct5, string opcodestr,61 DAGOperand immtype = stackadj>62 : RVInst16<(outs), (ins reglist_s0:$rlist, immtype:$stackadj),63 opcodestr, "$rlist, $stackadj", [], InstFormatOther> {64 bits<4> rlist;65 bits<16> stackadj;66 67 let Inst{1-0} = 0b10;68 let Inst{3-2} = stackadj{5-4};69 let Inst{7-4} = rlist;70 let Inst{12-8} = funct5;71 let Inst{15-13} = 0b101;72}73 74//===----------------------------------------------------------------------===//75// Instructions76//===----------------------------------------------------------------------===//77 78let DecoderNamespace = "Xqccmp", Predicates = [HasVendorXqccmp] in {79 80let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {81let Defs = [X10, X11] in82def QC_CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),83 (ins SR07:$rs1, SR07:$rs2), "qc.cm.mva01s", "$rs1, $rs2">,84 Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;85 86let Uses = [X10, X11] in87def QC_CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),88 (ins), "qc.cm.mvsa01", "$rs1, $rs2">,89 Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;90} // hasSideEffects = 0, mayLoad = 0, mayStore = 091 92let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in93def QC_CM_PUSH : RVInstZcCPPP<0b11000, "qc.cm.push", negstackadj>,94 Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,95 ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,96 ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,97 ReadStoreData, ReadStoreData, ReadStoreData]>;98 99let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2, X8] in100def QC_CM_PUSHFP : RVInstXqccmpCPPPFP<0b11001, "qc.cm.pushfp", negstackadj>,101 Sched<[WriteIALU, WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,102 ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,103 ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,104 ReadStoreData, ReadStoreData, ReadStoreData]>;105 106let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,107 Uses = [X2], Defs = [X2] in108def QC_CM_POPRET : RVInstZcCPPP<0b11110, "qc.cm.popret">,109 Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,110 WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,111 WriteLDW, WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;112 113let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,114 Uses = [X2], Defs = [X2, X10] in115def QC_CM_POPRETZ : RVInstZcCPPP<0b11100, "qc.cm.popretz">,116 Sched<[WriteIALU, WriteIALU, WriteLDW, WriteLDW, WriteLDW,117 WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,118 WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,119 ReadIALU]>;120 121let hasSideEffects = 0, mayLoad = 1, mayStore = 0,122 Uses = [X2], Defs = [X2] in123def QC_CM_POP : RVInstZcCPPP<0b11010, "qc.cm.pop">,124 Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,125 WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,126 WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;127 128} // DecoderNamespace = "Xqccmp", Predicates = [HasVendorXqccmp]129 130//===----------------------------------------------------------------------===//131// Aliases132//===----------------------------------------------------------------------===//133 134