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1//===-- RISCVInstrInfoXwch.td ------------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the vendor extension(s) defined by WCH.10//11//===----------------------------------------------------------------------===//12 13class QKStackInst<bits<2> funct2, dag outs, dag ins,14 string opcodestr, string argstr>15 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatOther> {16 bits<3> rd_rs2;17 18 let Inst{15-11} = 0b10000;19 let Inst{6-5} = funct2;20 let Inst{4-2} = rd_rs2;21 let Inst{1-0} = 0b00;22}23 24//===----------------------------------------------------------------------===//25// Operand definitions.26//===----------------------------------------------------------------------===//27 28// A 5-bit unsigned immediate where the least significant bit is zero.29def uimm5_lsb0 : RISCVOp,30 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 1>(Imm);}]> {31 let ParserMatchClass = UImmAsmOperand<5, "Lsb0">;32 let EncoderMethod = "getImmOpValue";33 let DecoderMethod = "decodeUImmOperand<5>";34 let OperandType = "OPERAND_UIMM5_LSB0";35 let MCOperandPredicate = [{36 int64_t Imm;37 if (!MCOp.evaluateAsConstantImm(Imm))38 return false;39 return isShiftedUInt<4, 1>(Imm);40 }];41}42 43// A 6-bit unsigned immediate where the least significant bit is zero.44def uimm6_lsb0 : RISCVOp,45 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 1>(Imm);}]> {46 let ParserMatchClass = UImmAsmOperand<6, "Lsb0">;47 let EncoderMethod = "getImmOpValue";48 let DecoderMethod = "decodeUImmOperand<6>";49 let OperandType = "OPERAND_UIMM6_LSB0";50 let MCOperandPredicate = [{51 int64_t Imm;52 if (!MCOp.evaluateAsConstantImm(Imm))53 return false;54 return isShiftedUInt<5, 1>(Imm);55 }];56}57 58//===----------------------------------------------------------------------===//59// Instructions60//===----------------------------------------------------------------------===//61let Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc" in {62 63let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in64def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd),65 (ins GPRCMem:$rs1, uimm5:$imm),66 "qk.c.lbu", "$rd, ${imm}(${rs1})">,67 Sched<[WriteLDB, ReadMemBase]> {68 bits<5> imm;69 let Inst{12} = imm{0};70 let Inst{11-10} = imm{4-3};71 let Inst{6-5} = imm{2-1};72}73let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in74def QK_C_SB : RVInst16CS<0b101, 0b00, (outs),75 (ins GPRC:$rs2, GPRCMem:$rs1,76 uimm5:$imm),77 "qk.c.sb", "$rs2, ${imm}(${rs1})">,78 Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {79 bits<5> imm;80 let Inst{12} = imm{0};81 let Inst{11-10} = imm{4-3};82 let Inst{6-5} = imm{2-1};83}84 85let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in86def QK_C_LHU : RVInst16CL<0b001, 0b10, (outs GPRC:$rd),87 (ins GPRCMem:$rs1, uimm6_lsb0:$imm),88 "qk.c.lhu", "$rd, ${imm}(${rs1})">,89 Sched<[WriteLDH, ReadMemBase]> {90 bits<6> imm;91 let Inst{12-10} = imm{5-3};92 let Inst{6-5} = imm{2-1};93}94let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in95def QK_C_SH : RVInst16CS<0b101, 0b10, (outs),96 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),97 "qk.c.sh", "$rs2, ${imm}(${rs1})">,98 Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {99 bits<6> imm;100 let Inst{12-10} = imm{5-3};101 let Inst{6-5} = imm{2-1};102}103 104let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in105def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),106 (ins SPMem:$rs1, uimm4:$imm),107 "qk.c.lbusp", "$rd_rs2, ${imm}(${rs1})">,108 Sched<[WriteLDB, ReadMemBase]> {109 bits<0> rs1;110 bits<4> imm;111 let Inst{10-7} = imm;112}113let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in114def QK_C_SBSP : QKStackInst<0b10, (outs),115 (ins GPRC:$rd_rs2, SPMem:$rs1,116 uimm4:$imm),117 "qk.c.sbsp", "$rd_rs2, ${imm}(${rs1})">,118 Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {119 bits<0> rs1;120 bits<4> imm;121 let Inst{10-7} = imm;122}123 124let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in125def QK_C_LHUSP : QKStackInst<0b01, (outs GPRC:$rd_rs2),126 (ins SPMem:$rs1, uimm5_lsb0:$imm),127 "qk.c.lhusp", "$rd_rs2, ${imm}(${rs1})">,128 Sched<[WriteLDH, ReadMemBase]> {129 bits<0> rs1;130 bits<5> imm;131 let Inst{10-8} = imm{3-1};132 let Inst{7} = imm{4};133}134let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in135def QK_C_SHSP : QKStackInst<0b11, (outs),136 (ins GPRC:$rd_rs2, SPMem:$rs1, uimm5_lsb0:$imm),137 "qk.c.shsp", "$rd_rs2, ${imm}(${rs1})">,138 Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {139 bits<0> rs1;140 bits<5> imm;141 let Inst{10-8} = imm{3-1};142 let Inst{7} = imm{4};143}144 145} // Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc"146 147//===----------------------------------------------------------------------===//148// Assembler Pseudo Instructions149//===----------------------------------------------------------------------===//150 151let EmitPriority = 0 in {152let Predicates = [HasVendorXwchc] in {153def : InstAlias<"qk.c.lbu $rd, (${rs1})", (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, 0)>;154def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, 0)>;155def : InstAlias<"qk.c.lhu $rd, (${rs1})", (QK_C_LHU GPRC:$rd, GPRCMem:$rs1, 0)>;156def : InstAlias<"qk.c.sh $rs2, (${rs1})", (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, 0)>;157def : InstAlias<"qk.c.lbusp $rd, (${rs1})", (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, 0)>;158def : InstAlias<"qk.c.sbsp $rs2, (${rs1})", (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, 0)>;159def : InstAlias<"qk.c.lhusp $rd, (${rs1})", (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, 0)>;160def : InstAlias<"qk.c.shsp $rs2, (${rs1})", (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, 0)>;161}162}163 164//===----------------------------------------------------------------------===/165// Compress Instruction tablegen backend.166//===----------------------------------------------------------------------===//167 168let Predicates = [HasVendorXwchc] in {169def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm5:$imm),170 (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, uimm5:$imm)>;171def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm5:$imm),172 (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, uimm5:$imm)>;173def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm),174 (QK_C_LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm)>;175def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),176 (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm)>;177def : CompressPat<(LBU GPRC:$rd, SPMem:$rs1, uimm4:$imm),178 (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, uimm4:$imm)>;179def : CompressPat<(SB GPRC:$rs2, SPMem:$rs1, uimm4:$imm),180 (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, uimm4:$imm)>;181def : CompressPat<(LHU GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm),182 (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm)>;183def : CompressPat<(SH GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm),184 (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm)>;185}186