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1//===-- RISCVInstrInfoZalasr.td ---------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the Zalasr (Load-Acquire10// and Store-Release) extension11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Instruction class templates16//===----------------------------------------------------------------------===//17 18let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in19class LAQ_r<bit aq, bit rl, bits<3> funct3, string opcodestr>20 : RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO,21 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),22 opcodestr, "$rd, $rs1"> {23 let rs2 = 0;24}25 26let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in27class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr>28 : RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO,29 (outs), (ins GPR:$rs2, GPRMemZeroOffset:$rs1),30 opcodestr, "$rs2, $rs1"> {31 let rd = 0;32}33 34multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> {35 def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">;36 def _AQRL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;37}38 39multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> {40 def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">;41 def _AQRL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;42}43 44//===----------------------------------------------------------------------===//45// Instructions46//===----------------------------------------------------------------------===//47 48let Predicates = [HasStdExtZalasr], IsSignExtendingOpW = 1 in {49defm LB : LAQ_r_aq_rl<0b000, "lb">;50defm LH : LAQ_r_aq_rl<0b001, "lh">;51defm LW : LAQ_r_aq_rl<0b010, "lw">;52defm SB : SRL_r_aq_rl<0b000, "sb">;53defm SH : SRL_r_aq_rl<0b001, "sh">;54defm SW : SRL_r_aq_rl<0b010, "sw">;55} // Predicates = [HasStdExtZalasr]56 57let Predicates = [HasStdExtZalasr, IsRV64] in {58defm LD : LAQ_r_aq_rl<0b011, "ld">;59defm SD : SRL_r_aq_rl<0b011, "sd">;60} // Predicates = [HasStdExtZalasr, IsRV64]61 62//===----------------------------------------------------------------------===//63// Pseudo-instructions and codegen patterns64//===----------------------------------------------------------------------===//65 66class PatLAQ<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>67 : Pat<(vt (OpNode (XLenVT GPRMemZeroOffset:$rs1))),68 (Inst GPRMemZeroOffset:$rs1)>;69 70// n.b. this switches order of arguments71// to deal with the fact that SRL has addr, data72// while atomic_store has data, addr73class PatSRL<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>74 : Pat<(OpNode (vt GPR:$rs2), (XLenVT GPRMemZeroOffset:$rs1)),75 (Inst GPR:$rs2, GPRMemZeroOffset:$rs1)>;76 77 78let Predicates = [HasStdExtZalasr] in {79 // the sequentially consistent loads use80 // .aq instead of .aqrl to match the psABI/A.781 def : PatLAQ<acquiring_load<atomic_load_asext_8>, LB_AQ>;82 def : PatLAQ<seq_cst_load<atomic_load_asext_8>, LB_AQ>;83 84 def : PatLAQ<acquiring_load<atomic_load_asext_16>, LH_AQ>;85 def : PatLAQ<seq_cst_load<atomic_load_asext_16>, LH_AQ>;86 87 // the sequentially consistent stores use88 // .rl instead of .aqrl to match the psABI/A.789 def : PatSRL<releasing_store<atomic_store_8>, SB_RL>;90 def : PatSRL<seq_cst_store<atomic_store_8>, SB_RL>;91 92 def : PatSRL<releasing_store<atomic_store_16>, SH_RL>;93 def : PatSRL<seq_cst_store<atomic_store_16>, SH_RL>;94 95 def : PatSRL<releasing_store<atomic_store_32>, SW_RL>;96 def : PatSRL<seq_cst_store<atomic_store_32>, SW_RL>;97}98 99let Predicates = [HasStdExtZalasr, IsRV32] in {100 def : PatLAQ<acquiring_load<atomic_load_nonext_32>, LW_AQ, i32>;101 def : PatLAQ<seq_cst_load<atomic_load_nonext_32>, LW_AQ, i32>;102} // Predicates = [HasStdExtZalasr, IsRV32]103 104let Predicates = [HasStdExtZalasr, IsRV64] in {105 def : PatLAQ<acquiring_load<atomic_load_asext_32>, LW_AQ, i64>;106 def : PatLAQ<seq_cst_load<atomic_load_asext_32>, LW_AQ, i64>;107 108 def : PatLAQ<acquiring_load<atomic_load_nonext_64>, LD_AQ, i64>;109 def : PatLAQ<seq_cst_load<atomic_load_nonext_64>, LD_AQ, i64>;110 111 def : PatSRL<releasing_store<atomic_store_64>, SD_RL, i64>;112 def : PatSRL<seq_cst_store<atomic_store_64>, SD_RL, i64>;113} // Predicates = [HasStdExtZalasr, IsRV64]114