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1//===-- RISCVInstrInfoZclsd.td -----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Zclsd',10// Compressed Load/Store pair instructions extension.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Instruction Class Templates16//===----------------------------------------------------------------------===//17 18def GPRPairNoX0RV32Operand : AsmOperandClass {19 let Name = "GPRPairNoX0RV32";20 let ParserMethod = "parseGPRPair<false>";21 let PredicateMethod = "isGPRPairNoX0";22 let RenderMethod = "addRegOperands";23}24 25def GPRPairNoX0RV32 : RegisterOperand<GPRPairNoX0> {26 let ParserMatchClass = GPRPairNoX0RV32Operand;27}28 29def GPRPairCRV32Operand : AsmOperandClass {30 let Name = "GPRPairCRV32";31 let ParserMethod = "parseGPRPair<false>";32 let PredicateMethod = "isGPRPairC";33 let RenderMethod = "addRegOperands";34}35 36def GPRPairCRV32 : RegisterOperand<GPRPairC> {37 let ParserMatchClass = GPRPairCRV32Operand;38}39 40//===----------------------------------------------------------------------===//41// Instructions42//===----------------------------------------------------------------------===//43 44let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in {45def C_LDSP_RV32 : CStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, uimm9_lsb000>,46 Sched<[WriteLDD, ReadMemBase]> {47 let Inst{4-2} = imm{8-6};48}49 50def C_SDSP_RV32 : CStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>,51 Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {52 let Inst{9-7} = imm{8-6};53}54 55def C_LD_RV32 : CLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,56 Sched<[WriteLDD, ReadMemBase]> {57 bits<8> imm;58 let Inst{12-10} = imm{5-3};59 let Inst{6-5} = imm{7-6};60}61 62def C_SD_RV32 : CStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,63 Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {64 bits<8> imm;65 let Inst{12-10} = imm{5-3};66 let Inst{6-5} = imm{7-6};67}68}// Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap"69 70//===----------------------------------------------------------------------===//71// Assembler Pseudo Instructions72//===----------------------------------------------------------------------===//73 74let Predicates = [HasStdExtZclsd, IsRV32] in {75def : InstAlias<"c.ld $rd, (${rs1})",76 (C_LD_RV32 GPRPairCRV32:$rd, GPRCMem:$rs1, 0), 0>;77def : InstAlias<"c.sd $rs2, (${rs1})",78 (C_SD_RV32 GPRPairCRV32:$rs2, GPRCMem:$rs1, 0), 0>;79def : InstAlias<"c.ldsp $rd, (${rs1})",80 (C_LDSP_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, 0), 0>;81def : InstAlias<"c.sdsp $rs2, (${rs1})",82 (C_SDSP_RV32 GPRPairRV32:$rs2, SPMem:$rs1, 0), 0>;83}84 85//===----------------------------------------------------------------------===//86// Compress Instruction tablegen backend.87//===----------------------------------------------------------------------===//88 89let Predicates = [HasStdExtZclsd, IsRV32] in {90def : CompressPat<(LD_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, uimm9_lsb000:$imm),91 (C_LDSP_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;92def : CompressPat<(SD_RV32 GPRPairRV32:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),93 (C_SDSP_RV32 GPRPairRV32:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;94def : CompressPat<(LD_RV32 GPRPairCRV32:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),95 (C_LD_RV32 GPRPairCRV32:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;96def : CompressPat<(SD_RV32 GPRPairCRV32:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),97 (C_SD_RV32 GPRPairCRV32:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;98} // Predicates = [HasStdExtZclsd, IsRV32]99