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1//===-- RISCVInstrInfoZcmop.td -----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard Compressed10// May-Be-Operations Extension (Zcmop).11//12//===----------------------------------------------------------------------===//13 14let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in15class CMOPInst<bits<3> imm3, string opcodestr>16 : RVInst16CI<0b011, 0b01, (outs), (ins), opcodestr, ""> {17 let Inst{6-2} = 0;18 let Inst{7} = 1;19 let Inst{10-8} = imm3;20 let Inst{12-11} = 0;21}22 23foreach n = [1, 3, 5, 7, 9, 11, 13, 15] in {24 let Predicates = [HasStdExtZcmop] in25 def C_MOP_ # n : CMOPInst<!srl(n, 1), "c.mop." # n>, Sched<[]>;26}27