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1//===-- RISCVInstrInfoZfa.td - RISC-V 'Zfa' instructions ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Zfa'10// additional floating-point extension, version 1.0.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// RISC-V specific DAG Nodes.16//===----------------------------------------------------------------------===//17 18def SDT_RISCVFLI19 : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, XLenVT>]>;20 21// Zfa fli instruction for constant materialization.22def riscv_fli : RVSDNode<"FLI", SDT_RISCVFLI>;23 24//===----------------------------------------------------------------------===//25// Operand and SDNode transformation definitions.26//===----------------------------------------------------------------------===//27 28// 5-bit floating-point immediate encodings.29def LoadFPImmOperand : AsmOperandClass {30 let Name = "LoadFPImm";31 let ParserMethod = "parseFPImm";32 let RenderMethod = "addFPImmOperands";33 let DiagnosticType = "InvalidLoadFPImm";34 let DiagnosticString = "operand must be a valid floating-point constant";35}36 37def loadfpimm : Operand<XLenVT> {38 let ParserMatchClass = LoadFPImmOperand;39 let PrintMethod = "printFPImmOperand";40 let OperandType = "OPERAND_UIMM5";41 let OperandNamespace = "RISCVOp";42}43 44def RTZArg : AsmOperandClass {45 let Name = "RTZArg";46 let RenderMethod = "addFRMArgOperands";47 let DiagnosticType = "InvalidRTZArg";48 let DiagnosticString = "operand must be 'rtz' floating-point rounding mode";49 let ParserMethod = "parseFRMArg";50}51 52def rtzarg : Operand<XLenVT> {53 let ParserMatchClass = RTZArg;54 let PrintMethod = "printFRMArg";55 let DecoderMethod = "decodeRTZArg";56 let OperandType = "OPERAND_RTZARG";57 let OperandNamespace = "RISCVOp";58}59 60//===----------------------------------------------------------------------===//61// Instruction class templates62//===----------------------------------------------------------------------===//63 64let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in65class FPBinaryOp_rr<bits<7> funct7, bits<3> funct3, DAGOperand rdty,66 DAGOperand rsty, string opcodestr>67 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd),68 (ins rsty:$rs1, rsty:$rs2), opcodestr, "$rd, $rs1, $rs2">;69 70let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in71class FPFLI_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3,72 DAGOperand rdty, string opcodestr>73 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd),74 (ins loadfpimm:$imm), opcodestr, "$rd, $imm"> {75 bits<5> imm;76 77 let rs2 = rs2val;78 let rs1 = imm;79}80 81let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,82 UseNamedOperandTable = 1, hasPostISelHook = 1 in83class FPUnaryOp_r_rtz<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,84 DAGOperand rs1ty, string opcodestr>85 : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),86 (ins rs1ty:$rs1, rtzarg:$frm), opcodestr,87 "$rd, $rs1$frm"> {88 let rs2 = rs2val;89}90 91//===----------------------------------------------------------------------===//92// Instructions93//===----------------------------------------------------------------------===//94 95let Predicates = [HasStdExtZfa] in {96let isReMaterializable = 1, isAsCheapAsAMove = 1 in97def FLI_S : FPFLI_r<0b1111000, 0b00001, 0b000, FPR32, "fli.s">,98 Sched<[WriteFLI32]>;99 100let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in {101def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, Commutable=1>;102def FMAXM_S: FPALU_rr<0b0010100, 0b011, "fmaxm.s", FPR32, Commutable=1>;103}104 105def FROUND_S : FPUnaryOp_r_frm<0b0100000, 0b00100, FPR32, FPR32, "fround.s">,106 Sched<[WriteFRoundF32, ReadFRoundF32]>;107def FROUNDNX_S : FPUnaryOp_r_frm<0b0100000, 0b00101, FPR32, FPR32, "froundnx.s">,108 Sched<[WriteFRoundF32, ReadFRoundF32]>;109 110let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in {111def FLTQ_S : FPCmp_rr<0b1010000, 0b101, "fltq.s", FPR32>;112def FLEQ_S : FPCmp_rr<0b1010000, 0b100, "fleq.s", FPR32>;113}114} // Predicates = [HasStdExtZfa]115 116let Predicates = [HasStdExtZfa, HasStdExtD] in {117let isReMaterializable = 1, isAsCheapAsAMove = 1 in118def FLI_D : FPFLI_r<0b1111001, 0b00001, 0b000, FPR64, "fli.d">,119 Sched<[WriteFLI64]>;120 121let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {122def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, Commutable=1>;123def FMAXM_D: FPALU_rr<0b0010101, 0b011, "fmaxm.d", FPR64, Commutable=1>;124}125 126def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">,127 Sched<[WriteFRoundF64, ReadFRoundF64]>;128def FROUNDNX_D : FPUnaryOp_r_frm<0b0100001, 0b00101, FPR64, FPR64, "froundnx.d">,129 Sched<[WriteFRoundF64, ReadFRoundF64]>;130 131let IsSignExtendingOpW = 1 in132def FCVTMOD_W_D133 : FPUnaryOp_r_rtz<0b1100001, 0b01000, GPR, FPR64, "fcvtmod.w.d">,134 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;135 136let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in {137def FLTQ_D : FPCmp_rr<0b1010001, 0b101, "fltq.d", FPR64>;138def FLEQ_D : FPCmp_rr<0b1010001, 0b100, "fleq.d", FPR64>;139}140} // Predicates = [HasStdExtZfa, HasStdExtD]141 142let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {143let mayRaiseFPException = 0 in {144def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,145 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;146def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,147 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64, ReadFMovI64ToF64]>;148}149 150let isCodeGenOnly = 1, mayRaiseFPException = 0 in151def FMV_X_W_FPR64 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR64,152 "fmv.x.w">,153 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;154} // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]155 156let Predicates = [HasStdExtZfa, HasStdExtZfhOrZvfh] in157let isReMaterializable = 1, isAsCheapAsAMove = 1 in158def FLI_H : FPFLI_r<0b1111010, 0b00001, 0b000, FPR16, "fli.h">,159 Sched<[WriteFLI16]>;160 161let Predicates = [HasStdExtZfa, HasStdExtZfh] in {162let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {163def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, Commutable=1>;164def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, Commutable=1>;165}166 167def FROUND_H : FPUnaryOp_r_frm<0b0100010, 0b00100, FPR16, FPR16, "fround.h">,168 Sched<[WriteFRoundF16, ReadFRoundF16]>;169def FROUNDNX_H : FPUnaryOp_r_frm<0b0100010, 0b00101, FPR16, FPR16, "froundnx.h">,170 Sched<[WriteFRoundF16, ReadFRoundF16]>;171 172let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in {173def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16>;174def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;175}176} // Predicates = [HasStdExtZfa, HasStdExtZfh]177 178let Predicates = [HasStdExtZfa, HasStdExtQ] in {179let isReMaterializable = 1, isAsCheapAsAMove = 1 in180def FLI_Q : FPFLI_r<0b1111011, 0b00001, 0b000, FPR128, "fli.q">,181 Sched<[WriteFLI128]>;182 183let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {184def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;185def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;186}187 188def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">,189 Sched<[WriteFRoundF128, ReadFRoundF128]>;190def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 191 "froundnx.q">,192 Sched<[WriteFRoundF128, ReadFRoundF128]>;193 194let SchedRW = [WriteFCmp128, ReadFCmp128, ReadFCmp128] in {195def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;196def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;197}198} // Predicates = [HasStdExtZfa, HasStdExtQ]199 200let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {201 let mayRaiseFPException = 0 in {202 def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b00001, 0b000, GPR, FPR128, "fmvh.x.q">;203 def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;204 }205} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]206 207//===----------------------------------------------------------------------===//208// Pseudo-instructions and codegen patterns209//===----------------------------------------------------------------------===//210 211let Predicates = [HasStdExtZfa] in {212def : InstAlias<"fgtq.s $rd, $rs, $rt",213 (FLTQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;214def : InstAlias<"fgeq.s $rd, $rs, $rt",215 (FLEQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;216}217 218let Predicates = [HasStdExtZfa, HasStdExtD] in {219def : InstAlias<"fgtq.d $rd, $rs, $rt",220 (FLTQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;221def : InstAlias<"fgeq.d $rd, $rs, $rt",222 (FLEQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;223}224 225let Predicates = [HasStdExtZfa, HasStdExtZfh] in {226def : InstAlias<"fgtq.h $rd, $rs, $rt",227 (FLTQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;228def : InstAlias<"fgeq.h $rd, $rs, $rt",229 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;230}231 232let Predicates = [HasStdExtZfa, HasStdExtQ] in {233def : InstAlias<"fgtq.q $rd, $rs, $rt",234 (FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;235def : InstAlias<"fgeq.q $rd, $rs, $rt",236 (FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;237}238 239//===----------------------------------------------------------------------===//240// Codegen patterns241//===----------------------------------------------------------------------===//242 243let Predicates = [HasStdExtZfa] in {244def: Pat<(f32 (riscv_fli timm:$imm)), (FLI_S timm:$imm)>;245 246def: PatFprFpr<fminimum, FMINM_S, FPR32, f32>;247def: PatFprFpr<fmaximum, FMAXM_S, FPR32, f32>;248 249// frint rounds according to the current rounding mode and detects250// inexact conditions.251def: Pat<(any_frint FPR32:$rs1), (FROUNDNX_S FPR32:$rs1, FRM_DYN)>;252 253// fnearbyint is like frint but does not detect inexact conditions.254def: Pat<(any_fnearbyint FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_DYN)>;255 256def: Pat<(any_fround FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RMM)>;257def: Pat<(any_froundeven FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RNE)>;258def: Pat<(any_ffloor FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RDN)>;259def: Pat<(any_fceil FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RUP)>;260def: Pat<(any_ftrunc FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RTZ)>;261 262def: PatSetCC<FPR32, strict_fsetcc, SETLT, FLTQ_S, f32>;263def: PatSetCC<FPR32, strict_fsetcc, SETOLT, FLTQ_S, f32>;264def: PatSetCC<FPR32, strict_fsetcc, SETLE, FLEQ_S, f32>;265def: PatSetCC<FPR32, strict_fsetcc, SETOLE, FLEQ_S, f32>;266} // Predicates = [HasStdExtZfa]267 268let Predicates = [HasStdExtZfa, HasStdExtD] in {269def: Pat<(f64 (riscv_fli timm:$imm)), (FLI_D timm:$imm)>;270 271def: PatFprFpr<fminimum, FMINM_D, FPR64, f64>;272def: PatFprFpr<fmaximum, FMAXM_D, FPR64, f64>;273 274// frint rounds according to the current rounding mode and detects275// inexact conditions.276def: Pat<(any_frint FPR64:$rs1), (FROUNDNX_D FPR64:$rs1, FRM_DYN)>;277 278// fnearbyint is like frint but does not detect inexact conditions.279def: Pat<(any_fnearbyint FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_DYN)>;280 281def: Pat<(any_fround FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RMM)>;282def: Pat<(any_froundeven FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RNE)>;283def: Pat<(any_ffloor FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RDN)>;284def: Pat<(any_fceil FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RUP)>;285def: Pat<(any_ftrunc FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RTZ)>;286 287def: PatSetCC<FPR64, strict_fsetcc, SETLT, FLTQ_D, f64>;288def: PatSetCC<FPR64, strict_fsetcc, SETOLT, FLTQ_D, f64>;289def: PatSetCC<FPR64, strict_fsetcc, SETLE, FLEQ_D, f64>;290def: PatSetCC<FPR64, strict_fsetcc, SETOLE, FLEQ_D, f64>;291} // Predicates = [HasStdExtZfa, HasStdExtD]292 293let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {294def : Pat<(RISCVBuildPairF64 GPR:$rs1, GPR:$rs2),295 (FMVP_D_X GPR:$rs1, GPR:$rs2)>;296}297 298let Predicates = [HasStdExtZfa, HasStdExtZfh] in {299def: Pat<(f16 (riscv_fli timm:$imm)), (FLI_H timm:$imm)>;300 301def: PatFprFpr<fminimum, FMINM_H, FPR16, f16>;302def: PatFprFpr<fmaximum, FMAXM_H, FPR16, f16>;303 304// frint rounds according to the current rounding mode and detects305// inexact conditions.306def: Pat<(f16 (any_frint FPR16:$rs1)), (FROUNDNX_H FPR16:$rs1, FRM_DYN)>;307 308// fnearbyint is like frint but does not detect inexact conditions.309def: Pat<(f16 (any_fnearbyint FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_DYN)>;310 311def: Pat<(f16 (any_fround FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RMM)>;312def: Pat<(f16 (any_froundeven FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RNE)>;313def: Pat<(f16 (any_ffloor FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RDN)>;314def: Pat<(f16 (any_fceil FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RUP)>;315def: Pat<(f16 (any_ftrunc FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RTZ)>;316 317def: PatSetCC<FPR16, strict_fsetcc, SETLT, FLTQ_H, f16>;318def: PatSetCC<FPR16, strict_fsetcc, SETOLT, FLTQ_H, f16>;319def: PatSetCC<FPR16, strict_fsetcc, SETLE, FLEQ_H, f16>;320def: PatSetCC<FPR16, strict_fsetcc, SETOLE, FLEQ_H, f16>;321} // Predicates = [HasStdExtZfa, HasStdExtZfh]322