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1//===-- RISCVInstrInfoZfh.td - RISC-V 'Zfh' instructions ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Zfh'10// half-precision floating-point extension, version 1.0.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// RISC-V specific DAG Nodes.16//===----------------------------------------------------------------------===//17 18def SDT_RISCVFMV_H_X19 : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, XLenVT>]>;20def SDT_RISCVFMV_X_EXTH21 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>;22 23// FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as24// XLEN is the only legal integer width.25//26// FMV_H_X matches the semantics of the FMV.H.X.27// FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.28// FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.29//30// This is a more convenient semantic for producing dagcombines that remove31// unnecessary GPR->FPR->GPR moves.32def riscv_fmv_h_x33 : RVSDNode<"FMV_H_X", SDT_RISCVFMV_H_X>;34def riscv_fmv_x_anyexth35 : RVSDNode<"FMV_X_ANYEXTH", SDT_RISCVFMV_X_EXTH>;36def riscv_fmv_x_signexth37 : RVSDNode<"FMV_X_SIGNEXTH", SDT_RISCVFMV_X_EXTH>;38 39//===----------------------------------------------------------------------===//40// Operand and SDNode transformation definitions.41//===----------------------------------------------------------------------===//42 43// Zhinxmin and Zhinx44 45def GPRAsFPR16 : AsmOperandClass {46 let Name = "GPRAsFPR16";47 let ParserMethod = "parseGPRAsFPR";48 let RenderMethod = "addRegOperands";49}50 51def FPR16INX : RegisterOperand<GPRF16> {52 let ParserMatchClass = GPRAsFPR16;53}54 55def ZfhExt : ExtInfo<"", "", [HasStdExtZfh],56 f16, FPR16, FPR32, ?, FPR16>;57def ZfhminExt : ExtInfo<"", "", [HasStdExtZfhmin],58 f16, FPR16, FPR32, ?, FPR16>;59def ZfhDExt : ExtInfo<"", "", [HasStdExtZfh, HasStdExtD],60 ?, ?, FPR32, FPR64, FPR16>;61def ZfhminDExt : ExtInfo<"", "", [HasStdExtZfhmin, HasStdExtD],62 ?, ?, FPR32, FPR64, FPR16>;63 64def ZhinxExt : ExtInfo<"_INX", "Zfinx",65 [HasStdExtZhinx],66 f16, FPR16INX, FPR32INX, ?, FPR16INX>;67def ZhinxminExt : ExtInfo<"_INX", "Zfinx",68 [HasStdExtZhinxmin],69 f16, FPR16INX, FPR32INX, ?, FPR16INX>;70def ZhinxZdinxExt : ExtInfo<"_INX", "Zfinx",71 [HasStdExtZhinx, HasStdExtZdinx, IsRV64],72 ?, ?, FPR32INX, FPR64INX, FPR16INX, i64>;73def ZhinxminZdinxExt : ExtInfo<"_INX", "Zfinx",74 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64],75 ?, ?, FPR32INX, FPR64INX, FPR16INX, i64>;76def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32",77 [HasStdExtZhinx, HasStdExtZdinx, IsRV32],78 ?, ?, FPR32INX, FPR64IN32X, FPR16INX, i32>;79def ZhinxminZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32",80 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32],81 ?, ?, FPR32INX, FPR64IN32X, FPR16INX, i32>;82 83defvar ZfhExts = [ZfhExt, ZhinxExt];84defvar ZfhminExts = [ZfhminExt, ZhinxminExt];85defvar ZfhDExts = [ZfhDExt, ZhinxZdinxExt, ZhinxZdinx32Ext];86defvar ZfhminDExts = [ZfhminDExt, ZhinxminZdinxExt, ZhinxminZdinx32Ext];87 88//===----------------------------------------------------------------------===//89// Instructions90//===----------------------------------------------------------------------===//91 92let Predicates = [HasHalfFPLoadStoreMove] in {93let canFoldAsLoad = 1, isReMaterializable = 1 in94def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>;95 96// Operands for stores are in the order srcreg, base, offset rather than97// reflecting the order these fields are specified in the instruction98// encoding.99def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>;100} // Predicates = [HasHalfFPLoadStoreMove]101 102let Predicates = [HasStdExtZhinxmin], isCodeGenOnly = 1 in {103def LH_INX : Load_ri<0b001, "lh", GPRF16>, Sched<[WriteLDH, ReadMemBase]>;104def SH_INX : Store_rri<0b001, "sh", GPRF16>,105 Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;106 107// ADDI with GPRF16 register class to use for copy. This should not be used as108// general ADDI, so the immediate should always be zero.109let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveReg = 1,110 hasSideEffects = 0, mayLoad = 0, mayStore = 0 in111def PseudoMV_FPR16INX : Pseudo<(outs GPRF16:$rd), (ins GPRF16:$rs), []>,112 Sched<[WriteIALU, ReadIALU]>;113}114 115foreach Ext = ZfhExts in {116 let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16Addend] in {117 defm FMADD_H : FPFMA_rrr_frm_m<OPC_MADD, 0b10, "fmadd.h", Ext>;118 defm FMSUB_H : FPFMA_rrr_frm_m<OPC_MSUB, 0b10, "fmsub.h", Ext>;119 defm FNMSUB_H : FPFMA_rrr_frm_m<OPC_NMSUB, 0b10, "fnmsub.h", Ext>;120 defm FNMADD_H : FPFMA_rrr_frm_m<OPC_NMADD, 0b10, "fnmadd.h", Ext>;121 }122 123 let SchedRW = [WriteFAdd16, ReadFAdd16, ReadFAdd16] in {124 defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", Ext, Commutable=1>;125 defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", Ext>;126 }127 let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in128 defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", Ext, Commutable=1>;129 130 let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in131 defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", Ext>;132 133 defm FSQRT_H : FPUnaryOp_r_frm_m<0b0101110, 0b00000, Ext, Ext.PrimaryTy,134 Ext.PrimaryTy, "fsqrt.h">,135 Sched<[WriteFSqrt16, ReadFSqrt16]>;136 137 let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16],138 mayRaiseFPException = 0 in {139 defm FSGNJ_H : FPALU_rr_m<0b0010010, 0b000, "fsgnj.h", Ext>;140 defm FSGNJN_H : FPALU_rr_m<0b0010010, 0b001, "fsgnjn.h", Ext>;141 defm FSGNJX_H : FPALU_rr_m<0b0010010, 0b010, "fsgnjx.h", Ext>;142 }143 144 let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {145 defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", Ext, Commutable=1>;146 defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", Ext, Commutable=1>;147 }148 149 let IsSignExtendingOpW = 1 in150 defm FCVT_W_H : FPUnaryOp_r_frm_m<0b1100010, 0b00000, Ext, GPR, Ext.PrimaryTy,151 "fcvt.w.h">,152 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>;153 154 let IsSignExtendingOpW = 1 in155 defm FCVT_WU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00001, Ext, GPR, Ext.PrimaryTy,156 "fcvt.wu.h">,157 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>;158 159 defm FCVT_H_W : FPUnaryOp_r_frm_m<0b1101010, 0b00000, Ext, Ext.PrimaryTy, GPR,160 "fcvt.h.w">,161 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>;162 163 defm FCVT_H_WU : FPUnaryOp_r_frm_m<0b1101010, 0b00001, Ext, Ext.PrimaryTy, GPR,164 "fcvt.h.wu">,165 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>;166} // foreach Ext = ZfhExts167 168foreach Ext = ZfhminExts in {169 defm FCVT_H_S : FPUnaryOp_r_frm_m<0b0100010, 0b00000, Ext, Ext.PrimaryTy,170 Ext.F32Ty, "fcvt.h.s">,171 Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;172 173 defm FCVT_S_H : FPUnaryOp_r_frmlegacy_m<0b0100000, 0b00010,Ext, Ext.F32Ty,174 Ext.PrimaryTy, "fcvt.s.h">,175 Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;176} // foreach Ext = ZfhminExts177 178let Predicates = [HasHalfFPLoadStoreMove] in {179let mayRaiseFPException = 0, IsSignExtendingOpW = 1 in180def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">,181 Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>;182 183let mayRaiseFPException = 0 in184def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">,185 Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>;186} // Predicates = [HasHalfFPLoadStoreMove]187 188foreach Ext = ZfhExts in {189 let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in {190 defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", Ext, Commutable=1>;191 defm FLT_H : FPCmp_rr_m<0b1010010, 0b001, "flt.h", Ext>;192 defm FLE_H : FPCmp_rr_m<0b1010010, 0b000, "fle.h", Ext>;193 }194 195 let mayRaiseFPException = 0 in196 defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy,197 "fclass.h">,198 Sched<[WriteFClass16, ReadFClass16]>;199 200 defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, Ext, GPR, Ext.PrimaryTy,201 "fcvt.l.h", [IsRV64]>,202 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;203 204 defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, Ext, GPR, Ext.PrimaryTy,205 "fcvt.lu.h", [IsRV64]>,206 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;207 208 defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, Ext, Ext.PrimaryTy, GPR,209 "fcvt.h.l", [IsRV64]>,210 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>;211 212 defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, Ext, Ext.PrimaryTy, GPR,213 "fcvt.h.lu", [IsRV64]>,214 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>;215} // foreach Ext = ZfhExts216 217foreach Ext = ZfhminDExts in {218 defm FCVT_H_D : FPUnaryOp_r_frm_m<0b0100010, 0b00001, Ext, Ext.F16Ty,219 Ext.F64Ty, "fcvt.h.d">,220 Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>;221 222 defm FCVT_D_H : FPUnaryOp_r_frmlegacy_m<0b0100001, 0b00010, Ext, Ext.F64Ty,223 Ext.F16Ty, "fcvt.d.h">,224 Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]>;225} // foreach Ext = ZfhminDExts226 227//===----------------------------------------------------------------------===//228// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)229//===----------------------------------------------------------------------===//230 231let Predicates = [HasHalfFPLoadStoreMove] in {232def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>;233def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;234} // Predicates = [HasStdExtZfhmin]235 236let Predicates = [HasStdExtZfh] in {237def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;238def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;239def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;240 241// fgt.h/fge.h are recognised by the GNU assembler but the canonical242// flt.h/fle.h forms will always be printed. Therefore, set a zero weight.243def : InstAlias<"fgt.h $rd, $rs, $rt",244 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;245def : InstAlias<"fge.h $rd, $rs, $rt",246 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;247 248let usesCustomInserter = 1 in {249def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>;250def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;251}252} // Predicates = [HasStdExtZfh]253 254let Predicates = [HasHalfFPLoadStoreMove] in {255def PseudoFLH : PseudoFloatLoad<"flh", FPR16>;256def PseudoFSH : PseudoStore<"fsh", FPR16>;257} // Predicates = [HasStdExtZfhmin]258 259let Predicates = [HasStdExtZhinx] in {260def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;261def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;262def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;263 264def : InstAlias<"fgt.h $rd, $rs, $rt",265 (FLT_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>;266def : InstAlias<"fge.h $rd, $rs, $rt",267 (FLE_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>;268 269let usesCustomInserter = 1 in {270def PseudoQuietFLE_H_INX : PseudoQuietFCMP<FPR16INX>;271def PseudoQuietFLT_H_INX : PseudoQuietFCMP<FPR16INX>;272}273} // Predicates = [HasStdExtZhinxmin]274 275//===----------------------------------------------------------------------===//276// Pseudo-instructions and codegen patterns277//===----------------------------------------------------------------------===//278 279 280/// Float conversion operations281 282// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so283// are defined later.284 285/// Float arithmetic operations286 287foreach Ext = ZfhExts in {288 defm : PatFprFprDynFrm_m<any_fadd, FADD_H, Ext>;289 defm : PatFprFprDynFrm_m<any_fsub, FSUB_H, Ext>;290 defm : PatFprFprDynFrm_m<any_fmul, FMUL_H, Ext>;291 defm : PatFprFprDynFrm_m<any_fdiv, FDIV_H, Ext>;292}293 294let Predicates = [HasStdExtZfh] in {295def : Pat<(f16 (any_fsqrt FPR16:$rs1)), (FSQRT_H FPR16:$rs1, FRM_DYN)>;296 297def : Pat<(f16 (fneg FPR16:$rs1)), (FSGNJN_H $rs1, $rs1)>;298def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>;299 300def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>;301 302def : PatFprFpr<fcopysign, FSGNJ_H, FPR16, f16>;303def : PatFprFpr<riscv_fsgnjx, FSGNJX_H, FPR16, f16>;304def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))),305 (FSGNJN_H FPR16:$rs1, FPR16:$rs2)>;306def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),307 (FSGNJ_H $rs1, (f16 (FCVT_H_S $rs2, FRM_DYN)))>;308 309// fmadd: rs1 * rs2 + rs3310def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),311 (FMADD_H $rs1, $rs2, $rs3, FRM_DYN)>;312 313// fmsub: rs1 * rs2 - rs3314def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3))),315 (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>;316 317// fnmsub: -rs1 * rs2 + rs3318def : Pat<(f16 (any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3)),319 (FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>;320 321// fnmadd: -rs1 * rs2 - rs3322def : Pat<(f16 (any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3))),323 (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>;324 325// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)326def : Pat<(f16 (fneg (any_fma_nsz FPR16:$rs1, FPR16:$rs2, FPR16:$rs3))),327 (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>;328} // Predicates = [HasStdExtZfh]329 330let Predicates = [HasStdExtZhinx] in {331 332/// Float conversion operations333 334// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so335// are defined later.336 337/// Float arithmetic operations338 339def : Pat<(any_fsqrt FPR16INX:$rs1), (FSQRT_H_INX FPR16INX:$rs1, FRM_DYN)>;340 341def : Pat<(fneg FPR16INX:$rs1), (FSGNJN_H_INX $rs1, $rs1)>;342def : Pat<(fabs FPR16INX:$rs1), (FSGNJX_H_INX $rs1, $rs1)>;343 344def : Pat<(riscv_fclass FPR16INX:$rs1), (FCLASS_H_INX $rs1)>;345 346def : PatFprFpr<fcopysign, FSGNJ_H_INX, FPR16INX, f16>;347def : PatFprFpr<riscv_fsgnjx, FSGNJX_H_INX, FPR16INX, f16>;348def : Pat<(fcopysign FPR16INX:$rs1, (fneg FPR16INX:$rs2)),349 (FSGNJN_H_INX FPR16INX:$rs1, FPR16INX:$rs2)>;350def : Pat<(fcopysign FPR16INX:$rs1, FPR32INX:$rs2),351 (FSGNJ_H_INX $rs1, (FCVT_H_S_INX $rs2, FRM_DYN))>;352 353// fmadd: rs1 * rs2 + rs3354def : Pat<(any_fma FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3),355 (FMADD_H_INX $rs1, $rs2, $rs3, FRM_DYN)>;356 357// fmsub: rs1 * rs2 - rs3358def : Pat<(any_fma FPR16INX:$rs1, FPR16INX:$rs2, (fneg FPR16INX:$rs3)),359 (FMSUB_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;360 361// fnmsub: -rs1 * rs2 + rs3362def : Pat<(any_fma (fneg FPR16INX:$rs1), FPR16INX:$rs2, FPR16INX:$rs3),363 (FNMSUB_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;364 365// fnmadd: -rs1 * rs2 - rs3366def : Pat<(any_fma (fneg FPR16INX:$rs1), FPR16INX:$rs2, (fneg FPR16INX:$rs3)),367 (FNMADD_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;368 369// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)370def : Pat<(fneg (any_fma_nsz FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3)),371 (FNMADD_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;372} // Predicates = [HasStdExtZhinx]373 374// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches375// LLVM's fminnum and fmaxnum376// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.377foreach Ext = ZfhExts in {378 defm : PatFprFpr_m<fminnum, FMIN_H, Ext>;379 defm : PatFprFpr_m<fmaxnum, FMAX_H, Ext>;380 defm : PatFprFpr_m<fminimumnum, FMIN_H, Ext>;381 defm : PatFprFpr_m<fmaximumnum, FMAX_H, Ext>;382 defm : PatFprFpr_m<riscv_fmin, FMIN_H, Ext>;383 defm : PatFprFpr_m<riscv_fmax, FMAX_H, Ext>;384 let Predicates = Ext.Predicates in385 def : Pat<(f16 (fcanonicalize FPR16:$rs1)), (FMIN_H $rs1, $rs1)>;386}387 388/// Setcc389// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for390// strict versions of those.391 392// Match non-signaling FEQ_D393foreach Ext = ZfhExts in {394 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_H, Ext>;395 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_H, Ext>;396 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_H, Ext>;397 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_H, Ext>;398 defm : PatSetCC_m<strict_fsetcc, SETLE, PseudoQuietFLE_H, Ext>;399 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_H, Ext>;400}401 402let Predicates = [HasStdExtZfh] in {403// Match signaling FEQ_H404def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETEQ)),405 (AND (XLenVT (FLE_H $rs1, $rs2)),406 (XLenVT (FLE_H $rs2, $rs1)))>;407def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETOEQ)),408 (AND (XLenVT (FLE_H $rs1, $rs2)),409 (XLenVT (FLE_H $rs2, $rs1)))>;410// If both operands are the same, use a single FLE.411def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETEQ)),412 (FLE_H $rs1, $rs1)>;413def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETOEQ)),414 (FLE_H $rs1, $rs1)>;415} // Predicates = [HasStdExtZfh]416 417let Predicates = [HasStdExtZhinx] in {418// Match signaling FEQ_H419def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETEQ)),420 (AND (XLenVT (FLE_H_INX $rs1, $rs2)),421 (XLenVT (FLE_H_INX $rs2, $rs1)))>;422def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETOEQ)),423 (AND (XLenVT (FLE_H_INX $rs1, $rs2)),424 (XLenVT (FLE_H_INX $rs2, $rs1)))>;425// If both operands are the same, use a single FLE.426def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETEQ)),427 (FLE_H_INX $rs1, $rs1)>;428def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETOEQ)),429 (FLE_H_INX $rs1, $rs1)>;430} // Predicates = [HasStdExtZhinx]431 432foreach Ext = ZfhExts in {433 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_H, Ext>;434 defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_H, Ext>;435 defm : PatSetCC_m<any_fsetccs, SETLE, FLE_H, Ext>;436 defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_H, Ext>;437}438 439let Predicates = [HasStdExtZfh] in {440def PseudoFROUND_H : PseudoFROUND<FPR16, f16>;441} // Predicates = [HasStdExtZfh]442 443let Predicates = [HasStdExtZhinx] in {444def PseudoFROUND_H_INX : PseudoFROUND<FPR16INX, f16>;445} // Predicates = [HasStdExtZhinx]446 447let Predicates = [HasStdExtZfhmin] in {448defm Select_FPR16 : SelectCC_GPR_rrirr<FPR16, f16>;449 450/// Loads451def : LdPat<load, FLH, f16>;452 453/// Stores454def : StPat<store, FSH, FPR16, f16>;455} // Predicates = [HasStdExtZfhmin]456 457let Predicates = [HasStdExtZhinxmin] in {458defm Select_FPR16INX : SelectCC_GPR_rrirr<FPR16INX, f16>;459 460/// Loads461def : LdPat<load, LH_INX, f16>;462 463/// Stores464def : StPat<store, SH_INX, GPRF16, f16>;465} // Predicates = [HasStdExtZhinxmin]466 467let Predicates = [HasStdExtZfhmin] in {468/// Float conversion operations469 470// f32 -> f16, f16 -> f32471def : Pat<(f16 (any_fpround FPR32:$rs1)), (FCVT_H_S FPR32:$rs1, FRM_DYN)>;472def : Pat<(any_fpextend (f16 FPR16:$rs1)), (FCVT_S_H FPR16:$rs1, FRM_RNE)>;473 474// Moves (no conversion)475def : Pat<(f16 (riscv_fmv_h_x GPR:$src)), (FMV_H_X GPR:$src)>;476def : Pat<(riscv_fmv_x_anyexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>;477def : Pat<(riscv_fmv_x_signexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>;478 479def : Pat<(fcopysign FPR32:$rs1, (f16 FPR16:$rs2)), (FSGNJ_S $rs1, (FCVT_S_H $rs2, FRM_RNE))>;480} // Predicates = [HasStdExtZfhmin]481 482let Predicates = [HasStdExtZhinxmin] in {483/// Float conversion operations484 485// f32 -> f16, f16 -> f32486def : Pat<(any_fpround FPR32INX:$rs1), (FCVT_H_S_INX FPR32INX:$rs1, FRM_DYN)>;487def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_S_H_INX FPR16INX:$rs1, FRM_RNE)>;488 489// Moves (no conversion)490def : Pat<(f16 (riscv_fmv_h_x GPR:$src)), (EXTRACT_SUBREG GPR:$src, sub_16)>;491def : Pat<(riscv_fmv_x_anyexth FPR16INX:$src), (INSERT_SUBREG (XLenVT (IMPLICIT_DEF)), FPR16INX:$src, sub_16)>;492 493def : Pat<(fcopysign FPR32INX:$rs1, FPR16INX:$rs2), (FSGNJ_S_INX $rs1, (FCVT_S_H_INX $rs2, FRM_RNE))>;494} // Predicates = [HasStdExtZhinxmin]495 496let Predicates = [HasStdExtZfh, IsRV32] in {497// half->[u]int. Round-to-zero must be used.498def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_H $rs1, 0b001)>;499def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_H $rs1, 0b001)>;500 501// Saturating half->[u]int32.502def : Pat<(i32 (riscv_fcvt_x (f16 FPR16:$rs1), timm:$frm)), (FCVT_W_H $rs1, timm:$frm)>;503def : Pat<(i32 (riscv_fcvt_xu (f16 FPR16:$rs1), timm:$frm)), (FCVT_WU_H $rs1, timm:$frm)>;504 505// half->int32 with current rounding mode.506def : Pat<(i32 (any_lrint (f16 FPR16:$rs1))), (FCVT_W_H $rs1, FRM_DYN)>;507 508// half->int32 rounded to nearest with ties rounded away from zero.509def : Pat<(i32 (any_lround (f16 FPR16:$rs1))), (FCVT_W_H $rs1, FRM_RMM)>;510 511// [u]int->half. Match GCC and default to using dynamic rounding mode.512def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_W $rs1, FRM_DYN)>;513def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_WU $rs1, FRM_DYN)>;514} // Predicates = [HasStdExtZfh]515 516let Predicates = [HasStdExtZhinx, IsRV32] in {517// half->[u]int. Round-to-zero must be used.518def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, 0b001)>;519def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_H_INX $rs1, 0b001)>;520 521// Saturating float->[u]int32.522def : Pat<(i32 (riscv_fcvt_x FPR16INX:$rs1, timm:$frm)), (FCVT_W_H_INX $rs1, timm:$frm)>;523def : Pat<(i32 (riscv_fcvt_xu FPR16INX:$rs1, timm:$frm)), (FCVT_WU_H_INX $rs1, timm:$frm)>;524 525// half->int32 with current rounding mode.526def : Pat<(i32 (any_lrint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_DYN)>;527 528// half->int32 rounded to nearest with ties rounded away from zero.529def : Pat<(i32 (any_lround FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_RMM)>;530 531// [u]int->half. Match GCC and default to using dynamic rounding mode.532def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W_INX $rs1, FRM_DYN)>;533def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU_INX $rs1, FRM_DYN)>;534} // Predicates = [HasStdExtZhinx, IsRV32]535 536let Predicates = [HasStdExtZfh, IsRV64] in {537// Use target specific isd nodes to help us remember the result is sign538// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be539// duplicated if it has another user that didn't need the sign_extend.540def : Pat<(riscv_any_fcvt_w_rv64 (f16 FPR16:$rs1), timm:$frm), (FCVT_W_H $rs1, timm:$frm)>;541def : Pat<(riscv_any_fcvt_wu_rv64 (f16 FPR16:$rs1), timm:$frm), (FCVT_WU_H $rs1, timm:$frm)>;542 543// half->[u]int64. Round-to-zero must be used.544def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_H $rs1, 0b001)>;545def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_H $rs1, 0b001)>;546 547// Saturating half->[u]int64.548def : Pat<(i64 (riscv_fcvt_x (f16 FPR16:$rs1), timm:$frm)), (FCVT_L_H $rs1, timm:$frm)>;549def : Pat<(i64 (riscv_fcvt_xu (f16 FPR16:$rs1), timm:$frm)), (FCVT_LU_H $rs1, timm:$frm)>;550 551// half->int64 with current rounding mode.552def : Pat<(i64 (any_lrint (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_DYN)>;553def : Pat<(i64 (any_llrint (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_DYN)>;554 555// half->int64 rounded to nearest with ties rounded away from zero.556def : Pat<(i64 (any_lround (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_RMM)>;557def : Pat<(i64 (any_llround (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_RMM)>;558 559// [u]int->fp. Match GCC and default to using dynamic rounding mode.560def : Pat<(f16 (any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1))))), (FCVT_H_W $rs1, FRM_DYN)>;561def : Pat<(f16 (any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1))))), (FCVT_H_WU $rs1, FRM_DYN)>;562def : Pat<(f16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_H_L $rs1, FRM_DYN)>;563def : Pat<(f16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_H_LU $rs1, FRM_DYN)>;564} // Predicates = [HasStdExtZfh, IsRV64]565 566let Predicates = [HasStdExtZhinx, IsRV64] in {567// Use target specific isd nodes to help us remember the result is sign568// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be569// duplicated if it has another user that didn't need the sign_extend.570def : Pat<(riscv_any_fcvt_w_rv64 FPR16INX:$rs1, timm:$frm), (FCVT_W_H_INX $rs1, timm:$frm)>;571def : Pat<(riscv_any_fcvt_wu_rv64 FPR16INX:$rs1, timm:$frm), (FCVT_WU_H_INX $rs1, timm:$frm)>;572 573// half->[u]int64. Round-to-zero must be used.574def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, 0b001)>;575def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_H_INX $rs1, 0b001)>;576 577// Saturating float->[u]int64.578def : Pat<(i64 (riscv_fcvt_x FPR16INX:$rs1, timm:$frm)), (FCVT_L_H_INX $rs1, timm:$frm)>;579def : Pat<(i64 (riscv_fcvt_xu FPR16INX:$rs1, timm:$frm)), (FCVT_LU_H_INX $rs1, timm:$frm)>;580 581// half->int64 with current rounding mode.582def : Pat<(i64 (any_lrint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_DYN)>;583def : Pat<(i64 (any_llrint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_DYN)>;584 585// half->int64 rounded to nearest with ties rounded away from zero.586def : Pat<(i64 (any_lround FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_RMM)>;587def : Pat<(i64 (any_llround FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_RMM)>;588 589// [u]int->fp. Match GCC and default to using dynamic rounding mode.590def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W_INX $rs1, FRM_DYN)>;591def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU_INX $rs1, FRM_DYN)>;592def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L_INX $rs1, FRM_DYN)>;593def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU_INX $rs1, FRM_DYN)>;594} // Predicates = [HasStdExtZhinx, IsRV64]595 596let Predicates = [HasStdExtZfhmin, HasStdExtD] in {597/// Float conversion operations598// f64 -> f16, f16 -> f64599def : Pat<(f16 (any_fpround FPR64:$rs1)), (FCVT_H_D FPR64:$rs1, FRM_DYN)>;600def : Pat<(any_fpextend (f16 FPR16:$rs1)), (FCVT_D_H FPR16:$rs1, FRM_RNE)>;601 602/// Float arithmetic operations603def : Pat<(f16 (fcopysign FPR16:$rs1, FPR64:$rs2)),604 (FSGNJ_H $rs1, (f16 (FCVT_H_D $rs2, FRM_DYN)))>;605def : Pat<(fcopysign FPR64:$rs1, (f16 FPR16:$rs2)), (FSGNJ_D $rs1, (FCVT_D_H $rs2, FRM_RNE))>;606} // Predicates = [HasStdExtZfhmin, HasStdExtD]607 608let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] in {609/// Float conversion operations610// f64 -> f16, f16 -> f64611def : Pat<(any_fpround FPR64IN32X:$rs1),612 (FCVT_H_D_IN32X FPR64IN32X:$rs1, (i32 FRM_DYN))>;613def : Pat<(any_fpextend FPR16INX:$rs1),614 (FCVT_D_H_IN32X FPR16INX:$rs1, (i32 FRM_RNE))>;615 616/// Float arithmetic operations617def : Pat<(fcopysign FPR16INX:$rs1, FPR64IN32X:$rs2),618 (FSGNJ_H_INX $rs1, (FCVT_H_D_IN32X $rs2, (i32 FRM_DYN)))>;619def : Pat<(fcopysign FPR64IN32X:$rs1, FPR16INX:$rs2),620 (FSGNJ_D_IN32X $rs1, (FCVT_D_H_IN32X $rs2, (i32 FRM_RNE)))>;621} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32]622 623let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64] in {624/// Float conversion operations625// f64 -> f16, f16 -> f64626def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_H_D_INX FPR64INX:$rs1, FRM_DYN)>;627def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_INX FPR16INX:$rs1, FRM_RNE)>;628 629/// Float arithmetic operations630def : Pat<(fcopysign FPR16INX:$rs1, FPR64INX:$rs2),631 (FSGNJ_H_INX $rs1, (FCVT_H_D_INX $rs2, 0b111))>;632def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (f64 (FCVT_D_H_INX $rs2, FRM_RNE)))>;633} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64]634