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1//===-- RISCVInstrInfoZicbo.td - RISC-V CMO instructions ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard Base Cache10// Management Operation ISA Extensions document (Zicbom, Zicboz, and Zicbop).11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Operand definitions.16//===----------------------------------------------------------------------===//17 18// A 12-bit signed immediate where the least significant five bits are zero.19def simm12_lsb00000 : RISCVOp,20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {21 let ParserMatchClass = SImmAsmOperand<12, "Lsb00000">;22 let EncoderMethod = "getImmOpValue";23 let DecoderMethod = "decodeSImmOperand<12>";24 let OperandType = "OPERAND_SIMM12_LSB00000";25}26 27//===----------------------------------------------------------------------===//28// Instruction Class Templates29//===----------------------------------------------------------------------===//30let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in31class CBO_r<bits<12> optype, string opcodestr>32 : RVInstI<0b010, OPC_MISC_MEM, (outs), (ins GPRMemZeroOffset:$rs1),33 opcodestr, "$rs1"> {34 let imm12 = optype;35 let rd = 0b00000;36}37 38let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in39class Prefetch_ri<bits<5> optype, string opcodestr>40 : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPRMem:$rs1, simm12_lsb00000:$imm12),41 opcodestr, "${imm12}(${rs1})"> {42 let Inst{11-7} = 0b00000;43 let rs2 = optype;44 let Format = InstFormatOther; // this does not follow the normal S format.45}46 47//===----------------------------------------------------------------------===//48// Instructions49//===----------------------------------------------------------------------===//50 51let Predicates = [HasStdExtZicbom] in {52def CBO_CLEAN : CBO_r<0b000000000001, "cbo.clean">, Sched<[]>;53def CBO_FLUSH : CBO_r<0b000000000010, "cbo.flush">, Sched<[]>;54def CBO_INVAL : CBO_r<0b000000000000, "cbo.inval">, Sched<[]>;55} // Predicates = [HasStdExtZicbom]56 57let Predicates = [HasStdExtZicboz] in {58def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;59} // Predicates = [HasStdExtZicboz]60 61let Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] in {62def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;63def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;64def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;65} // Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP]66 67//===----------------------------------------------------------------------===//68// Patterns69//===----------------------------------------------------------------------===//70 71def AddrRegImmLsb00000 : ComplexPattern<iPTR, 2, "SelectAddrRegImmLsb00000">;72 73let Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] in {74 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),75 timm, timm, (i32 0)),76 (PREFETCH_I GPR:$rs1, simm12_lsb00000:$imm12)>;77 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),78 (i32 0), timm, (i32 1)),79 (PREFETCH_R GPR:$rs1, simm12_lsb00000:$imm12)>;80 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),81 (i32 1), timm, (i32 1)),82 (PREFETCH_W GPR:$rs1, simm12_lsb00000:$imm12)>;83} // Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP]84