88 lines · plain
1//===------ RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen -*------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Instruction class templates11//===----------------------------------------------------------------------===//12 13class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> :14 RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> {15 bits<0> rs1;16 let Inst{15-13} = 0b011;17 let Inst{12} = 0;18 let Inst{11-7} = rs1val;19 let Inst{6-2} = 0b00000;20 let Inst{1-0} = 0b01;21}22 23//===----------------------------------------------------------------------===//24// Instructions25//===----------------------------------------------------------------------===//26 27let Predicates = [HasStdExtZicfiss] in {28let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in29def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk",30 "$rs1"> {31 let rd = 0;32 let imm12 = 0b110011011100;33} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 034 35let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {36def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"> {37 let imm12 = 0b110011011100;38 let rs1 = 0b00000;39}40} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 041 42let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in43def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),44 "sspush", "$rs2"> {45 let rd = 0b00000;46 let rs1 = 0b00000;47}48} // Predicates = [HasStdExtZicfiss]49 50let Predicates = [HasStdExtZicfiss, HasStdExtZcmop],51 DecoderNamespace = "Zicfiss" in {52let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in53def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">;54 55let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in56def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;57} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]58 59let Predicates = [HasStdExtZicfiss] in60defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;61 62let Predicates = [HasStdExtZicfiss, IsRV64] in63defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;64 65let Predicates = [HasStdExtZimop] in {66let hasSideEffects = 1, mayLoad = 0, mayStore = 1 in67def PseudoMOP_SSPUSH : Pseudo<(outs), (ins GPRX1X5:$rs2), []>,68 PseudoInstExpansion<(MOP_RR_7 X0, X0, GPR:$rs2)>;69let hasSideEffects = 1, mayLoad = 1, mayStore = 0 in70def PseudoMOP_SSPOPCHK : Pseudo<(outs), (ins GPRX1X5:$rs1), []>,71 PseudoInstExpansion<(MOP_R_28 X0, GPR:$rs1)>;72} // Predicates = [HasStdExtZimop]73 74let Predicates = [HasStdExtZcmop] in {75let Uses = [X1], hasSideEffects = 1, mayLoad = 0, mayStore = 1 in76def PseudoMOP_C_SSPUSH : Pseudo<(outs), (ins), []>,77 PseudoInstExpansion<(C_MOP_1)>;78} // Predicates = [HasStdExtZcmop]79 80//===----------------------------------------------------------------------===/81// Compress Instruction tablegen backend.82//===----------------------------------------------------------------------===//83 84let Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in {85def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>;86def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>;87} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop]88