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1//===-- RISCVInstrInfoZilsd.td -----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Zilsd',10// Load/Store pair instructions extension.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// RISC-V specific DAG Nodes.16//===----------------------------------------------------------------------===//17 18def SDT_RISCV_LD_RV3219 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<2>]>;20def SDT_RISCV_SD_RV3221 : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<2>]>;22 23def riscv_ld_rv32 : RVSDNode<"LD_RV32", SDT_RISCV_LD_RV32,24 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;25def riscv_st_rv32 : RVSDNode<"SD_RV32", SDT_RISCV_SD_RV32,26 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;27 28//===----------------------------------------------------------------------===//29// Instruction Class Templates30//===----------------------------------------------------------------------===//31 32//===----------------------------------------------------------------------===//33// Instructions34//===----------------------------------------------------------------------===//35 36let Predicates = [HasStdExtZilsd, IsRV32], DecoderNamespace = "RV32Only" in {37def LD_RV32 : Load_ri<0b011, "ld", GPRPairRV32>, Sched<[WriteLDD, ReadMemBase]>;38def SD_RV32 : Store_rri<0b011, "sd", GPRPairRV32>,39 Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;40} // Predicates = [HasStdExtZilsd, IsRV32], DecoderNamespace = "RV32Only"41 42//===----------------------------------------------------------------------===//43// Assembler Pseudo Instructions44//===----------------------------------------------------------------------===//45 46let Predicates = [HasStdExtZilsd, IsRV32] in {47def PseudoLD_RV32 : PseudoLoad<"ld", GPRPairRV32>;48def PseudoSD_RV32 : PseudoStore<"sd", GPRPairRV32>;49 50// Pseudo instructions for load/store optimization with 2 separate registers51def PseudoLD_RV32_OPT :52 Pseudo<(outs GPR:$rd1, GPR:$rd2),53 (ins GPR:$rs1, simm12_lo:$imm12), [], "", ""> {54 let hasSideEffects = 0;55 let mayLoad = 1;56 let mayStore = 0;57}58 59def PseudoSD_RV32_OPT :60 Pseudo<(outs),61 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3, simm12_lo:$imm12), [], "", ""> {62 let hasSideEffects = 0;63 let mayLoad = 0;64 let mayStore = 1;65}66 67def : InstAlias<"ld $rd, (${rs1})", (LD_RV32 GPRPairRV32:$rd, GPR:$rs1, 0), 0>;68def : InstAlias<"sd $rs2, (${rs1})", (SD_RV32 GPRPairRV32:$rs2, GPR:$rs1, 0), 0>;69}70