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1//===-- RISCVInstrInfoZimop.td -----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard10// May-Be-Operations Extension (Zimop).11//12//===----------------------------------------------------------------------===//13 14class RVInstIMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3, RISCVOpcode opcode,15                   dag outs, dag ins, string opcodestr, string argstr>16    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {17  let Inst{31} = imm7{6};18  let Inst{30} = imm5{4};19  let Inst{29-28} = imm7{5-4};20  let Inst{27-26} = imm5{3-2};21  let Inst{25-22} = imm7{3-0};22  let Inst{21-20} = imm5{1-0};23}24 25class RVInstRMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, RISCVOpcode opcode,26                   dag outs, dag ins, string opcodestr, string argstr>27    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {28  let Inst{31} = imm4{3};29  let Inst{30} = imm3{2};30  let Inst{29-28} = imm4{2-1};31  let Inst{27-26} = imm3{1-0};32  let Inst{25} = imm4{0};33}34 35// May-Be-Operations36def riscv_mop_r  : RVSDNode<"MOP_R",37                            SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,38                                                 SDTCisSameAs<0, 2>]>>;39def riscv_mop_rr : RVSDNode<"MOP_RR",40                            SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,41                                                 SDTCisSameAs<0, 2>,42                                                 SDTCisSameAs<0, 3>]>>;43 44let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in45class RVMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3,46             RISCVOpcode opcode, string opcodestr>47    : RVInstIMopr<imm7, imm5, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),48                   opcodestr, "$rd, $rs1">;49 50let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in51class RVMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3,52             RISCVOpcode opcode, string opcodestr>53    : RVInstRMoprr<imm4, imm3, funct3, opcode, (outs GPR:$rd),54                   (ins GPR:$rs1, GPR:$rs2),55                   opcodestr, "$rd, $rs1, $rs2">;56 57foreach i = 0...31 in {58  let Predicates = [HasStdExtZimop] in59  def MOP_R_#i : RVMopr<0b1000111, i, 0b100, OPC_SYSTEM, "mop.r."#i>,60                 Sched<[]>;61}62 63foreach i = 0...7 in {64  let Predicates = [HasStdExtZimop] in65  def MOP_RR_#i : RVMoprr<0b1001, i, 0b100, OPC_SYSTEM, "mop.rr."#i>,66                Sched<[]>;67}68 69let Predicates = [HasStdExtZimop] in {70// Zimop instructions71foreach i = 0...31 in {72  def : Pat<(XLenVT (riscv_mop_r GPR:$rs1, (XLenVT i))),73            (!cast<Instruction>("MOP_R_"#i) GPR:$rs1)>;74}75 76foreach i = 0...7 in {77  def : Pat<(XLenVT (riscv_mop_rr GPR:$rs1, GPR:$rs2, (XLenVT i))),78            (!cast<Instruction>("MOP_RR_"#i) GPR:$rs1, GPR:$rs2)>;79}80 81} // Predicates = [HasStdExtZimop]82