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1//===-- RISCVInstrInfoZvfbf.td - 'Zvfbf*' instructions -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Zvfbfmin'10// extension, providing vector conversion instructions for BFloat16.11// This version is still experimental as the 'Zvfbfmin' extension hasn't been12// ratified yet.13//14//===----------------------------------------------------------------------===//15 16//===----------------------------------------------------------------------===//17// Instructions18//===----------------------------------------------------------------------===//19 20let Predicates = [HasStdExtZvfbfminOrZvfofp8min],21 Constraints = "@earlyclobber $vd",22 mayRaiseFPException = true in {23let RVVConstraint = WidenCvt, DestEEW = EEWSEWx2 in24defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>;25let Uses = [FRM, VL, VTYPE] in26defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>;27}28 29let Predicates = [HasStdExtZvfbfwma],30 Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb",31 RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFPException = true,32 DestEEW = EEWSEWx2 in {33defm VFWMACCBF16_V : VWMAC_FV_V_F<"vfwmaccbf16", 0b111011>;34}35 36//===----------------------------------------------------------------------===//37// Pseudo instructions38//===----------------------------------------------------------------------===//39let Predicates = [HasStdExtZvfbfmin] in {40 defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V;41 defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;42}43 44let mayRaiseFPException = true, Predicates = [HasStdExtZvfbfwma] in45 defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;46 47defset list<VTypeInfoToWide> AllWidenableIntToBF16Vectors = {48 def : VTypeInfoToWide<VI8MF8, VBF16MF4>;49 def : VTypeInfoToWide<VI8MF4, VBF16MF2>;50 def : VTypeInfoToWide<VI8MF2, VBF16M1>;51 def : VTypeInfoToWide<VI8M1, VBF16M2>;52 def : VTypeInfoToWide<VI8M2, VBF16M4>;53 def : VTypeInfoToWide<VI8M4, VBF16M8>;54}55 56multiclass VPseudoVALU_VV_VF_RM_BF16 {57 foreach m = MxListF in {58 defm "" : VPseudoBinaryFV_VV_RM<m, 16/*sew*/>,59 SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX,60 16/*sew*/, forcePassthruRead=true>;61 }62 63 defvar f = SCALAR_F16;64 foreach m = f.MxList in {65 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,66 SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,67 f.SEW, forcePassthruRead=true>;68 }69}70 71multiclass VPseudoVALU_VF_RM_BF16 {72 defvar f = SCALAR_F16;73 foreach m = f.MxList in {74 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,75 SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,76 f.SEW, forcePassthruRead=true>;77 }78}79 80multiclass VPseudoVFWALU_VV_VF_RM_BF16 {81 foreach m = MxListFW in {82 defm "" : VPseudoBinaryW_VV_RM<m, sew=16>,83 SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,84 16/*sew*/, forcePassthruRead=true>;85 }86 87 defvar f = SCALAR_F16;88 foreach m = f.MxListFW in {89 defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,90 SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,91 f.SEW, forcePassthruRead=true>;92 }93}94 95multiclass VPseudoVFWALU_WV_WF_RM_BF16 {96 foreach m = MxListFW in {97 defm "" : VPseudoBinaryW_WV_RM<m, sew=16>,98 SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,99 16/*sew*/, forcePassthruRead=true>;100 }101 defvar f = SCALAR_F16;102 foreach m = f.MxListFW in {103 defm "" : VPseudoBinaryW_WF_RM<m, f, sew=f.SEW>,104 SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,105 f.SEW, forcePassthruRead=true>;106 }107}108 109multiclass VPseudoVFMUL_VV_VF_RM_BF16 {110 foreach m = MxListF in {111 defm "" : VPseudoBinaryFV_VV_RM<m, 16/*sew*/>,112 SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX,113 16/*sew*/, forcePassthruRead=true>;114 }115 116 defvar f = SCALAR_F16;117 foreach m = f.MxList in {118 defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,119 SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX,120 f.SEW, forcePassthruRead=true>;121 }122}123 124multiclass VPseudoVWMUL_VV_VF_RM_BF16 {125 foreach m = MxListFW in {126 defm "" : VPseudoBinaryW_VV_RM<m, sew=16>,127 SchedBinary<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV", m.MX,128 16/*sew*/, forcePassthruRead=true>;129 }130 131 defvar f = SCALAR_F16;132 foreach m = f.MxListFW in {133 defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,134 SchedBinary<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF", m.MX,135 f.SEW, forcePassthruRead=true>;136 }137}138 139multiclass VPseudoVMAC_VV_VF_AAXA_RM_BF16 {140 foreach m = MxListF in {141 defm "" : VPseudoTernaryV_VV_AAXA_RM<m, 16/*sew*/>,142 SchedTernary<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV", 143 "ReadVFMulAddV", m.MX, 16/*sew*/>;144 }145 146 defvar f = SCALAR_F16;147 foreach m = f.MxList in {148 defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, f.SEW>,149 SchedTernary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF", 150 "ReadVFMulAddV", m.MX, f.SEW>;151 }152}153 154multiclass VPseudoVWMAC_VV_VF_RM_BF16 {155 foreach m = MxListFW in {156 defm "" : VPseudoTernaryW_VV_RM<m, sew=16>,157 SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",158 "ReadVFWMulAddV", "ReadVFWMulAddV", m.MX, 16/*sew*/>;159 }160 161 defvar f = SCALAR_F16;162 foreach m = f.MxListFW in {163 defm "" : VPseudoTernaryW_VF_RM<m, f, sew=f.SEW>,164 SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV",165 "ReadVFWMulAddF", "ReadVFWMulAddV", m.MX, f.SEW>;166 }167}168 169multiclass VPseudoVRCP_V_BF16 {170 foreach m = MxListF in {171 defvar mx = m.MX;172 let VLMul = m.value in {173 def "_V_" # mx # "_E16"174 : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,175 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,176 forcePassthruRead=true>;177 def "_V_" # mx # "_E16_MASK"178 : VPseudoUnaryMask<m.vrclass, m.vrclass>,179 RISCVMaskedPseudo<MaskIdx = 2>,180 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,181 forcePassthruRead=true>;182 }183 }184}185 186multiclass VPseudoVRCP_V_RM_BF16 {187 foreach m = MxListF in {188 defvar mx = m.MX;189 let VLMul = m.value in {190 def "_V_" # mx # "_E16"191 : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,192 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,193 forcePassthruRead=true>;194 def "_V_" # mx # "_E16_MASK"195 : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,196 RISCVMaskedPseudo<MaskIdx = 2>,197 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,198 forcePassthruRead=true>;199 }200 }201}202 203multiclass VPseudoVMAX_VV_VF_BF16 {204 foreach m = MxListF in {205 defm "" : VPseudoBinaryV_VV<m, sew=16>,206 SchedBinary<"WriteVFMinMaxV", "ReadVFMinMaxV", "ReadVFMinMaxV", 207 m.MX, 16/*sew*/, forcePassthruRead=true>;208 }209 210 defvar f = SCALAR_F16;211 foreach m = f.MxList in {212 defm "" : VPseudoBinaryV_VF<m, f, f.SEW>,213 SchedBinary<"WriteVFMinMaxF", "ReadVFMinMaxV", "ReadVFMinMaxF", 214 m.MX, f.SEW, forcePassthruRead=true>;215 }216}217 218multiclass VPseudoVSGNJ_VV_VF_BF16 {219 foreach m = MxListF in {220 defm "" : VPseudoBinaryV_VV<m, sew=16>,221 SchedBinary<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV", m.MX,222 16/*sew*/, forcePassthruRead=true>;223 }224 225 defvar f = SCALAR_F16;226 foreach m = f.MxList in {227 defm "" : VPseudoBinaryV_VF<m, f, f.SEW>,228 SchedBinary<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF", m.MX,229 f.SEW, forcePassthruRead=true>;230 }231}232 233multiclass VPseudoVWCVTF_V_BF16 {234 defvar constraint = "@earlyclobber $rd";235 foreach m = MxListW in236 defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=8,237 TargetConstraintType=3>,238 SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX, 8/*sew*/,239 forcePassthruRead=true>;240}241 242multiclass VPseudoVWCVTD_V_BF16 {243 defvar constraint = "@earlyclobber $rd";244 foreach m = MxListFW in245 defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=16,246 TargetConstraintType=3>,247 SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX, 16/*sew*/,248 forcePassthruRead=true>;249}250 251multiclass VPseudoVNCVTD_W_BF16 {252 defvar constraint = "@earlyclobber $rd";253 foreach m = MxListFW in254 defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, sew=16,255 TargetConstraintType=2>,256 SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16/*sew*/,257 forcePassthruRead=true>;258}259 260multiclass VPseudoVNCVTD_W_RM_BF16 {261 defvar constraint = "@earlyclobber $rd";262 foreach m = MxListFW in263 defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,264 constraint, sew=16,265 TargetConstraintType=2>,266 SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16/*sew*/,267 forcePassthruRead=true>;268}269 270let Predicates = [HasStdExtZvfbfa], AltFmtType = IS_ALTFMT in {271let mayRaiseFPException = true in {272defm PseudoVFADD_ALT : VPseudoVALU_VV_VF_RM_BF16;273defm PseudoVFSUB_ALT : VPseudoVALU_VV_VF_RM_BF16;274defm PseudoVFRSUB_ALT : VPseudoVALU_VF_RM_BF16;275}276 277let mayRaiseFPException = true in {278defm PseudoVFWADD_ALT : VPseudoVFWALU_VV_VF_RM_BF16;279defm PseudoVFWSUB_ALT : VPseudoVFWALU_VV_VF_RM_BF16;280defm PseudoVFWADD_ALT : VPseudoVFWALU_WV_WF_RM_BF16;281defm PseudoVFWSUB_ALT : VPseudoVFWALU_WV_WF_RM_BF16;282}283 284let mayRaiseFPException = true in285defm PseudoVFMUL_ALT : VPseudoVFMUL_VV_VF_RM_BF16;286 287let mayRaiseFPException = true in288defm PseudoVFWMUL_ALT : VPseudoVWMUL_VV_VF_RM_BF16;289 290let mayRaiseFPException = true in {291defm PseudoVFMACC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;292defm PseudoVFNMACC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;293defm PseudoVFMSAC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;294defm PseudoVFNMSAC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;295defm PseudoVFMADD_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;296defm PseudoVFNMADD_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;297defm PseudoVFMSUB_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;298defm PseudoVFNMSUB_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;299}300 301let mayRaiseFPException = true in {302defm PseudoVFWMACC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;303defm PseudoVFWNMACC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;304defm PseudoVFWMSAC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;305defm PseudoVFWNMSAC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;306}307 308let mayRaiseFPException = true in309defm PseudoVFRSQRT7_ALT : VPseudoVRCP_V_BF16;310 311let mayRaiseFPException = true in312defm PseudoVFREC7_ALT : VPseudoVRCP_V_RM_BF16;313 314let mayRaiseFPException = true in {315defm PseudoVFMIN_ALT : VPseudoVMAX_VV_VF_BF16;316defm PseudoVFMAX_ALT : VPseudoVMAX_VV_VF_BF16;317}318 319defm PseudoVFSGNJ_ALT : VPseudoVSGNJ_VV_VF_BF16;320defm PseudoVFSGNJN_ALT : VPseudoVSGNJ_VV_VF_BF16;321defm PseudoVFSGNJX_ALT : VPseudoVSGNJ_VV_VF_BF16;322 323let mayRaiseFPException = true in {324defm PseudoVMFEQ_ALT : VPseudoVCMPM_VV_VF;325defm PseudoVMFNE_ALT : VPseudoVCMPM_VV_VF;326defm PseudoVMFLT_ALT : VPseudoVCMPM_VV_VF;327defm PseudoVMFLE_ALT : VPseudoVCMPM_VV_VF;328defm PseudoVMFGT_ALT : VPseudoVCMPM_VF;329defm PseudoVMFGE_ALT : VPseudoVCMPM_VF;330}331 332defm PseudoVFCLASS_ALT : VPseudoVCLS_V;333 334defm PseudoVFMERGE_ALT : VPseudoVMRG_FM;335 336defm PseudoVFMV_V_ALT : VPseudoVMV_F;337 338let mayRaiseFPException = true in {339defm PseudoVFWCVT_F_XU_ALT : VPseudoVWCVTF_V_BF16;340defm PseudoVFWCVT_F_X_ALT : VPseudoVWCVTF_V_BF16;341 342defm PseudoVFWCVT_F_F_ALT : VPseudoVWCVTD_V_BF16;343} // mayRaiseFPException = true344 345let mayRaiseFPException = true in {346let hasSideEffects = 0, hasPostISelHook = 1 in {347defm PseudoVFNCVT_XU_F_ALT : VPseudoVNCVTI_W_RM;348defm PseudoVFNCVT_X_F_ALT : VPseudoVNCVTI_W_RM;349}350 351defm PseudoVFNCVT_RTZ_XU_F_ALT : VPseudoVNCVTI_W;352defm PseudoVFNCVT_RTZ_X_F_ALT : VPseudoVNCVTI_W;353 354defm PseudoVFNCVT_F_F_ALT : VPseudoVNCVTD_W_RM_BF16;355 356defm PseudoVFNCVT_ROD_F_F_ALT : VPseudoVNCVTD_W_BF16;357} // mayRaiseFPException = true358 359let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {360 defvar f = SCALAR_F16;361 let HasSEWOp = 1, BaseInstr = VFMV_F_S in362 def "PseudoVFMV_" # f.FX # "_S_ALT" :363 RISCVVPseudo<(outs f.fprclass:$rd), (ins VR:$rs2, sew:$sew)>,364 Sched<[WriteVMovFS, ReadVMovFS]>;365 let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,366 Constraints = "$rd = $passthru" in367 def "PseudoVFMV_S_" # f.FX # "_ALT" :368 RISCVVPseudo<(outs VR:$rd),369 (ins VR:$passthru, f.fprclass:$rs1, AVL:$vl, sew:$sew)>,370 Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;371}372 373defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF<"@earlyclobber $rd">;374defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF;375} // Predicates = [HasStdExtZvfbfa], AltFmtType = IS_ALTFMT376 377//===----------------------------------------------------------------------===//378// Patterns379//===----------------------------------------------------------------------===//380multiclass VPatConversionWF_VF_BF<string intrinsic, string instruction,381 bit isSEWAware = 0> {382 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in383 {384 defvar fvti = fvtiToFWti.Vti;385 defvar fwti = fvtiToFWti.Wti;386 defm : VPatConversion<intrinsic, instruction, "V",387 fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,388 fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;389 }390}391 392multiclass VPatConversionVF_WF_BF_RM<string intrinsic, string instruction,393 bit isSEWAware = 0> {394 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {395 defvar fvti = fvtiToFWti.Vti;396 defvar fwti = fvtiToFWti.Wti;397 defm : VPatConversionRoundingMode<intrinsic, instruction, "W",398 fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,399 fvti.LMul, fvti.RegClass, fwti.RegClass,400 isSEWAware>;401 }402}403 404let Predicates = [HasStdExtZvfbfmin] in {405 defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",406 "PseudoVFWCVTBF16_F_F", isSEWAware=1>;407 defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",408 "PseudoVFNCVTBF16_F_F", isSEWAware=1>;409 410 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {411 defvar fvti = fvtiToFWti.Vti;412 defvar fwti = fvtiToFWti.Wti;413 def : Pat<(fwti.Vector (any_riscv_fpextend_vl414 (fvti.Vector fvti.RegClass:$rs1),415 (fvti.Mask VMV0:$vm),416 VLOpFrag)),417 (!cast<Instruction>("PseudoVFWCVTBF16_F_F_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")418 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,419 (fvti.Mask VMV0:$vm),420 GPR:$vl, fvti.Log2SEW, TA_MA)>;421 422 def : Pat<(fvti.Vector (any_riscv_fpround_vl423 (fwti.Vector fwti.RegClass:$rs1),424 (fwti.Mask VMV0:$vm), VLOpFrag)),425 (!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")426 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,427 (fwti.Mask VMV0:$vm),428 // Value to indicate no rounding mode change in429 // RISCVInsertReadWriteCSR430 FRM_DYN,431 GPR:$vl, fvti.Log2SEW, TA_MA)>;432 def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),433 (!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW)434 (fvti.Vector (IMPLICIT_DEF)),435 fwti.RegClass:$rs1,436 // Value to indicate no rounding mode change in437 // RISCVInsertReadWriteCSR438 FRM_DYN,439 fvti.AVL, fvti.Log2SEW, TA_MA)>;440 }441}442 443let Predicates = [HasStdExtZvfbfwma] in {444 defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16",445 AllWidenableBF16ToFloatVectors, isSEWAware=1>;446 defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmadd_vl, "PseudoVFWMACCBF16",447 AllWidenableBF16ToFloatVectors>;448 defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16",449 AllWidenableBF16ToFloatVectors>;450}451 452multiclass VPatConversionVI_VF_BF16<string intrinsic, string instruction> {453 foreach fvti = AllBF16Vectors in {454 defvar ivti = GetIntVTypeInfo<fvti>.Vti;455 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,456 GetVTypePredicates<ivti>.Predicates) in457 defm : VPatConversion<intrinsic, instruction, "V",458 ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,459 fvti.LMul, ivti.RegClass, fvti.RegClass>;460 }461}462 463multiclass VPatConversionWF_VI_BF16<string intrinsic, string instruction,464 bit isSEWAware = 0> {465 foreach vtiToWti = AllWidenableIntToBF16Vectors in {466 defvar vti = vtiToWti.Vti;467 defvar fwti = vtiToWti.Wti;468 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,469 GetVTypePredicates<fwti>.Predicates) in470 defm : VPatConversion<intrinsic, instruction, "V",471 fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,472 vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;473 }474}475 476multiclass VPatConversionWF_VF_BF16<string intrinsic, string instruction,477 bit isSEWAware = 0> {478 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {479 defvar fvti = fvtiToFWti.Vti;480 defvar fwti = fvtiToFWti.Wti;481 let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,482 GetVTypeMinimalPredicates<fwti>.Predicates) in483 defm : VPatConversion<intrinsic, instruction, "V",484 fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,485 fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;486 }487}488 489multiclass VPatConversionVI_WF_BF16<string intrinsic, string instruction> {490 foreach vtiToWti = AllWidenableIntToBF16Vectors in {491 defvar vti = vtiToWti.Vti;492 defvar fwti = vtiToWti.Wti;493 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,494 GetVTypePredicates<fwti>.Predicates) in495 defm : VPatConversion<intrinsic, instruction, "W",496 vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,497 vti.LMul, vti.RegClass, fwti.RegClass>;498 }499}500 501multiclass VPatConversionVI_WF_RM_BF16<string intrinsic, string instruction> {502 foreach vtiToWti = AllWidenableIntToBF16Vectors in {503 defvar vti = vtiToWti.Vti;504 defvar fwti = vtiToWti.Wti;505 let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,506 GetVTypePredicates<fwti>.Predicates) in507 defm : VPatConversionRoundingMode<intrinsic, instruction, "W",508 vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,509 vti.LMul, vti.RegClass, fwti.RegClass>;510 }511}512 513multiclass VPatConversionVF_WF_BF16<string intrinsic, string instruction,514 bit isSEWAware = 0> {515 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {516 defvar fvti = fvtiToFWti.Vti;517 defvar fwti = fvtiToFWti.Wti;518 let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,519 GetVTypePredicates<fwti>.Predicates) in520 defm : VPatConversion<intrinsic, instruction, "W",521 fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,522 fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;523 }524}525 526let Predicates = [HasStdExtZvfbfa] in {527defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfadd", "PseudoVFADD_ALT",528 AllBF16Vectors, isSEWAware = 1>;529defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfsub", "PseudoVFSUB_ALT",530 AllBF16Vectors, isSEWAware = 1>;531defm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB_ALT",532 AllBF16Vectors, isSEWAware = 1>;533defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwadd", "PseudoVFWADD_ALT",534 AllWidenableBF16ToFloatVectors, isSEWAware=1>;535defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwsub", "PseudoVFWSUB_ALT",536 AllWidenableBF16ToFloatVectors, isSEWAware=1>;537defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwadd_w", "PseudoVFWADD_ALT",538 AllWidenableBF16ToFloatVectors, isSEWAware=1>;539defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB_ALT",540 AllWidenableBF16ToFloatVectors, isSEWAware=1>;541defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL_ALT",542 AllBF16Vectors, isSEWAware=1>;543defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwmul", "PseudoVFWMUL_ALT",544 AllWidenableBF16ToFloatVectors, isSEWAware=1>;545defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmacc", "PseudoVFMACC_ALT",546 AllBF16Vectors, isSEWAware=1>;547defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmacc", "PseudoVFNMACC_ALT",548 AllBF16Vectors, isSEWAware=1>;549defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsac", "PseudoVFMSAC_ALT",550 AllBF16Vectors, isSEWAware=1>;551defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsac", "PseudoVFNMSAC_ALT",552 AllBF16Vectors, isSEWAware=1>;553defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmadd", "PseudoVFMADD_ALT",554 AllBF16Vectors, isSEWAware=1>;555defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmadd", "PseudoVFNMADD_ALT",556 AllBF16Vectors, isSEWAware=1>;557defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsub", "PseudoVFMSUB_ALT",558 AllBF16Vectors, isSEWAware=1>;559defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsub", "PseudoVFNMSUB_ALT",560 AllBF16Vectors, isSEWAware=1>;561defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmacc", "PseudoVFWMACC_ALT",562 AllWidenableBF16ToFloatVectors, isSEWAware=1>;563defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmacc", "PseudoVFWNMACC_ALT",564 AllWidenableBF16ToFloatVectors, isSEWAware=1>;565defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC_ALT",566 AllWidenableBF16ToFloatVectors, isSEWAware=1>;567defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC_ALT",568 AllWidenableBF16ToFloatVectors, isSEWAware=1>;569defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7_ALT",570 AllBF16Vectors, isSEWAware=1>;571defm : VPatUnaryV_V_RM<"int_riscv_vfrec7", "PseudoVFREC7_ALT",572 AllBF16Vectors, isSEWAware=1>;573defm : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN_ALT",574 AllBF16Vectors, isSEWAware=1>;575defm : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX_ALT",576 AllBF16Vectors, isSEWAware=1>;577defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnj", "PseudoVFSGNJ_ALT",578 AllBF16Vectors, isSEWAware=1>;579defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjn", "PseudoVFSGNJN_ALT",580 AllBF16Vectors, isSEWAware=1>;581defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjx", "PseudoVFSGNJX_ALT",582 AllBF16Vectors, isSEWAware=1>;583defm : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ_ALT", AllBF16Vectors>;584defm : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE_ALT", AllBF16Vectors>;585defm : VPatBinaryM_VV_VX<"int_riscv_vmflt", "PseudoVMFLT_ALT", AllBF16Vectors>;586defm : VPatBinaryM_VV_VX<"int_riscv_vmfne", "PseudoVMFNE_ALT", AllBF16Vectors>;587defm : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT_ALT", AllBF16Vectors>;588defm : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE_ALT", AllBF16Vectors>;589defm : VPatBinarySwappedM_VV<"int_riscv_vmfgt", "PseudoVMFLT_ALT", AllBF16Vectors>;590defm : VPatBinarySwappedM_VV<"int_riscv_vmfge", "PseudoVMFLE_ALT", AllBF16Vectors>;591defm : VPatConversionVI_VF_BF16<"int_riscv_vfclass", "PseudoVFCLASS_ALT">;592foreach vti = AllBF16Vectors in {593 let Predicates = GetVTypePredicates<vti>.Predicates in594 defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVFMERGE_ALT",595 "V"#vti.ScalarSuffix#"M",596 vti.Vector,597 vti.Vector, vti.Scalar, vti.Mask,598 vti.Log2SEW, vti.LMul, vti.RegClass,599 vti.RegClass, vti.ScalarRegClass>;600}601defm : VPatConversionWF_VI_BF16<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU_ALT",602 isSEWAware=1>;603defm : VPatConversionWF_VI_BF16<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X_ALT",604 isSEWAware=1>;605defm : VPatConversionWF_VF_BF16<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F_ALT",606 isSEWAware=1>;607defm : VPatConversionVI_WF_RM_BF16<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F_ALT">;608defm : VPatConversionVI_WF_RM_BF16<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F_ALT">;609defm : VPatConversionVI_WF_BF16<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F_ALT">;610defm : VPatConversionVI_WF_BF16<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F_ALT">;611defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F_ALT",612 AllWidenableBF16ToFloatVectors, isSEWAware=1>;613defm : VPatConversionVF_WF_BF16<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F_ALT",614 isSEWAware=1>;615defm : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP_ALT", AllBF16Vectors>;616defm : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN_ALT", AllBF16Vectors>;617 618foreach fvti = AllBF16Vectors in {619 defvar ivti = GetIntVTypeInfo<fvti>.Vti;620 let Predicates = GetVTypePredicates<ivti>.Predicates in {621 // 13.16. Vector Floating-Point Move Instruction622 // If we're splatting fpimm0, use vmv.v.x vd, x0.623 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl624 fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)),625 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)626 $passthru, 0, GPR:$vl, fvti.Log2SEW, TU_MU)>;627 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl628 fvti.Vector:$passthru, (fvti.Scalar (SelectScalarFPAsInt (XLenVT GPR:$imm))), VLOpFrag)),629 (!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX)630 $passthru, GPR:$imm, GPR:$vl, fvti.Log2SEW, TU_MU)>;631 }632 633 let Predicates = GetVTypePredicates<fvti>.Predicates in {634 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl635 fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),636 (!cast<Instruction>("PseudoVFMV_V_ALT_" # fvti.ScalarSuffix # "_" #637 fvti.LMul.MX)638 $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2),639 GPR:$vl, fvti.Log2SEW, TU_MU)>;640 }641}642 643foreach vti = NoGroupBF16Vectors in {644 let Predicates = GetVTypePredicates<vti>.Predicates in {645 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$passthru),646 (vti.Scalar (fpimm0)),647 VLOpFrag)),648 (PseudoVMV_S_X $passthru, (XLenVT X0), GPR:$vl, vti.Log2SEW)>;649 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$passthru),650 (vti.Scalar (SelectScalarFPAsInt (XLenVT GPR:$imm))),651 VLOpFrag)),652 (PseudoVMV_S_X $passthru, GPR:$imm, GPR:$vl, vti.Log2SEW)>;653 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$passthru),654 vti.ScalarRegClass:$rs1,655 VLOpFrag)),656 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_ALT")657 vti.RegClass:$passthru,658 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;659 }660 661 defvar vfmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",662 vti.ScalarSuffix,663 "_S_ALT"));664 // Only pattern-match extract-element operations where the index is 0. Any665 // other index will have been custom-lowered to slide the vector correctly666 // into place.667 let Predicates = GetVTypePredicates<vti>.Predicates in668 def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)),669 (vfmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>;670}671 672let Predicates = [HasStdExtZvfbfa] in {673 foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {674 defvar fvti = fvtiToFWti.Vti;675 defvar fwti = fvtiToFWti.Wti;676 def : Pat<(fwti.Vector (any_riscv_fpextend_vl677 (fvti.Vector fvti.RegClass:$rs1),678 (fvti.Mask VMV0:$vm),679 VLOpFrag)),680 (!cast<Instruction>("PseudoVFWCVT_F_F_ALT_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")681 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,682 (fvti.Mask VMV0:$vm),683 GPR:$vl, fvti.Log2SEW, TA_MA)>;684 685 def : Pat<(fvti.Vector (any_riscv_fpround_vl686 (fwti.Vector fwti.RegClass:$rs1),687 (fwti.Mask VMV0:$vm), VLOpFrag)),688 (!cast<Instruction>("PseudoVFNCVT_F_F_ALT_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")689 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,690 (fwti.Mask VMV0:$vm),691 // Value to indicate no rounding mode change in692 // RISCVInsertReadWriteCSR693 FRM_DYN,694 GPR:$vl, fvti.Log2SEW, TA_MA)>;695 def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),696 (!cast<Instruction>("PseudoVFNCVT_F_F_ALT_W_"#fvti.LMul.MX#"_E"#fvti.SEW)697 (fvti.Vector (IMPLICIT_DEF)),698 fwti.RegClass:$rs1,699 // Value to indicate no rounding mode change in700 // RISCVInsertReadWriteCSR701 FRM_DYN,702 fvti.AVL, fvti.Log2SEW, TA_MA)>;703 }704 705 foreach vti = AllBF16Vectors in {706 // 13.12. Vector Floating-Point Sign-Injection Instructions707 def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),708 (!cast<Instruction>("PseudoVFSGNJX_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)709 (vti.Vector (IMPLICIT_DEF)),710 vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;711 // Handle fneg with VFSGNJN using the same input for both operands.712 def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),713 (!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)714 (vti.Vector (IMPLICIT_DEF)),715 vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;716 717 def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),718 (vti.Vector vti.RegClass:$rs2))),719 (!cast<Instruction>("PseudoVFSGNJ_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)720 (vti.Vector (IMPLICIT_DEF)),721 vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;722 def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),723 (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))),724 (!cast<Instruction>("PseudoVFSGNJ_ALT_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)725 (vti.Vector (IMPLICIT_DEF)),726 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;727 728 def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),729 (vti.Vector (fneg vti.RegClass:$rs2)))),730 (!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)731 (vti.Vector (IMPLICIT_DEF)),732 vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;733 def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),734 (vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))),735 (!cast<Instruction>("PseudoVFSGNJN_ALT_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)736 (vti.Vector (IMPLICIT_DEF)),737 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;738 739 // 13.12. Vector Floating-Point Sign-Injection Instructions740 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),741 VLOpFrag),742 (!cast<Instruction>("PseudoVFSGNJX_ALT_VV_"# vti.LMul.MX #"_E"#vti.SEW#"_MASK")743 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,744 vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,745 TA_MA)>;746 // Handle fneg with VFSGNJN using the same input for both operands.747 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),748 VLOpFrag),749 (!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW #"_MASK")750 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,751 vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,752 TA_MA)>;753 754 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),755 (vti.Vector vti.RegClass:$rs2),756 vti.RegClass:$passthru,757 (vti.Mask VMV0:$vm),758 VLOpFrag),759 (!cast<Instruction>("PseudoVFSGNJ_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")760 vti.RegClass:$passthru, vti.RegClass:$rs1,761 vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,762 TAIL_AGNOSTIC)>;763 764 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),765 (riscv_fneg_vl vti.RegClass:$rs2,766 (vti.Mask true_mask),767 VLOpFrag),768 srcvalue,769 (vti.Mask true_mask),770 VLOpFrag),771 (!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)772 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,773 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;774 775 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),776 (SplatFPOp vti.ScalarRegClass:$rs2),777 vti.RegClass:$passthru,778 (vti.Mask VMV0:$vm),779 VLOpFrag),780 (!cast<Instruction>("PseudoVFSGNJ_ALT_V"#vti.ScalarSuffix#"_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")781 vti.RegClass:$passthru, vti.RegClass:$rs1,782 vti.ScalarRegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,783 TAIL_AGNOSTIC)>;784 }785 }786} // Predicates = [HasStdExtZvfbfa]787