1148 lines · plain
1//===-- RISCVInstrInfoZvk.td - RISC-V 'Zvk' instructions ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Zvk',10// Vector Cryptography Instructions extension, version Release 1.0.0.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Operand and SDNode transformation definitions.16//===----------------------------------------------------------------------===//17 18def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;19 20//===----------------------------------------------------------------------===//21// Instruction class templates22//===----------------------------------------------------------------------===//23 24let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {25multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {26 def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,27 SchedBinaryMC<"WriteVCLMULV", "ReadVCLMULV", "ReadVCLMULV">;28 def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,29 SchedBinaryMC<"WriteVCLMULX", "ReadVCLMULV", "ReadVCLMULX">;30}31 32class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,33 string argstr>34 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {35 bits<5> vs2;36 bits<6> imm;37 bits<5> vd;38 bit vm;39 40 let Inst{31-27} = funct6{5-1};41 let Inst{26} = imm{5};42 let Inst{25} = vm;43 let Inst{24-20} = vs2;44 let Inst{19-15} = imm{4-0};45 let Inst{14-12} = OPIVI.Value;46 let Inst{11-7} = vd;47 let Inst{6-0} = OPC_OP_V.Value;48 49 let Uses = [VL, VTYPE];50 let RVVConstraint = VMConstraint;51}52 53multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>54 : VALU_IV_V_X<opcodestr, funct6> {55 def I : RVInstIVI_VROR<funct6, (outs VR:$vd),56 (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),57 opcodestr # ".vi", "$vd, $vs2, $imm$vm">,58 SchedUnaryMC<"WriteVRotI", "ReadVRotV">;59}60 61// op vd, vs2, vs162class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>63 : VALUVVNoVm<funct6, opv, opcodestr> {64 let Inst{6-0} = OPC_OP_VE.Value;65}66 67// op vd, vs2, vs168class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>69 : RVInstVV<funct6, opv, (outs VR:$vd_wb),70 (ins VR:$vd, VR:$vs2, VR:$vs1),71 opcodestr, "$vd, $vs2, $vs1"> {72 let Constraints = "$vd = $vd_wb";73 let vm = 1;74 let Inst{6-0} = OPC_OP_VE.Value;75}76 77// op vd, vs2, imm78class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>79 : VALUVINoVm<funct6, opcodestr, optype> {80 let Inst{6-0} = OPC_OP_VE.Value;81 let Inst{14-12} = OPMVV.Value;82}83 84// op vd, vs2, imm where vd is also a source regardless of tail policy85class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>86 : RVInstIVI<funct6, (outs VR:$vd_wb),87 (ins VR:$vd, VR:$vs2, optype:$imm),88 opcodestr, "$vd, $vs2, $imm"> {89 let Constraints = "$vd = $vd_wb";90 let vm = 1;91 let Inst{6-0} = OPC_OP_VE.Value;92 let Inst{14-12} = OPMVV.Value;93}94 95// op vd, vs2 (use vs1 as instruction encoding) where vd is also a source96// regardless of tail policy97class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,98 string opcodestr>99 : RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),100 opcodestr, "$vd, $vs2"> {101 let Constraints = "$vd = $vd_wb";102 let vm = 1;103 let Inst{6-0} = OPC_OP_VE.Value;104}105 106multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,107 RISCVVFormat opv, string opcodestr> {108 let RVVConstraint = NoConstraint in109 def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,110 SchedBinaryMC<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV">;111 let RVVConstraint = VS2Constraint in112 def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,113 SchedBinaryMC<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV">;114}115} // hasSideEffects = 0, mayLoad = 0, mayStore = 0116 117//===----------------------------------------------------------------------===//118// Instructions119//===----------------------------------------------------------------------===//120 121let Predicates = [HasStdExtZvbb] in {122 def VBREV_V : VALUVs2<0b010010, 0b01010, OPMVV, "vbrev.v">;123 def VCLZ_V : VALUVs2<0b010010, 0b01100, OPMVV, "vclz.v">;124 def VCPOP_V : VALUVs2<0b010010, 0b01110, OPMVV, "vcpop.v">;125 def VCTZ_V : VALUVs2<0b010010, 0b01101, OPMVV, "vctz.v">;126 let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV,127 DestEEW = EEWSEWx2 in128 defm VWSLL_V : VSHT_IV_V_X_I<"vwsll", 0b110101>;129} // Predicates = [HasStdExtZvbb]130 131let Predicates = [HasStdExtZvbcOrZvbc32e] in {132 defm VCLMUL_V : VCLMUL_MV_V_X<"vclmul", 0b001100>;133 defm VCLMULH_V : VCLMUL_MV_V_X<"vclmulh", 0b001101>;134} // Predicates = [HasStdExtZvbcOrZvbc32e]135 136let Predicates = [HasStdExtZvkb] in {137 defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>;138 def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;139 def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;140 defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;141 defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;142} // Predicates = [HasStdExtZvkb]143 144let ElementsDependOn = EltDepsVLMask in {145 146let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {147 def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,148 SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",149 "ReadVGHSHV">;150 def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">,151 SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;152} // Predicates = [HasStdExtZvkg]153 154let Predicates = [HasStdExtZvkgs], RVVConstraint = VS2Constraint in {155 def VGHSH_VS : PALUVVNoVmTernary<0b100011, OPMVV, "vghsh.vs">,156 SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",157 "ReadVGHSHV">;158 def VGMUL_VS : PALUVs2NoVmBinary<0b101001, 0b10001, OPMVV, "vgmul.vs">,159 SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;160} // Predicates = [HasStdExtZvkgs]161 162let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in {163 def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,164 SchedTernaryMC<"WriteVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV",165 "ReadVSHA2CHV">;166 def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,167 SchedTernaryMC<"WriteVSHA2CLV", "ReadVSHA2CLV", "ReadVSHA2CLV",168 "ReadVSHA2CLV">;169 def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,170 SchedTernaryMC<"WriteVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV",171 "ReadVSHA2MSV">;172} // Predicates = [HasStdExtZvknhaOrZvknhb]173 174let Predicates = [HasStdExtZvkned] in {175 defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">;176 defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;177 defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;178 defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;179 def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,180 SchedUnaryMC<"WriteVAESKF1V", "ReadVAESKF1V">;181 def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,182 SchedBinaryMC<"WriteVAESKF2V", "ReadVAESKF2V", "ReadVAESKF2V">;183 let RVVConstraint = VS2Constraint in184 def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,185 SchedBinaryMC<"WriteVAESZV", "ReadVAESZV", "ReadVAESZV">;186} // Predicates = [HasStdExtZvkned]187 188let Predicates = [HasStdExtZvksed] in {189 let RVVConstraint = NoConstraint in190 def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,191 SchedUnaryMC<"WriteVSM4KV", "ReadVSM4KV">;192 defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;193} // Predicates = [HasStdExtZvksed]194 195let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {196 def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,197 SchedBinaryMC<"WriteVSM3CV", "ReadVSM3CV", "ReadVSM3CV">;198 def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,199 SchedUnaryMC<"WriteVSM3MEV", "ReadVSM3MEV">;200} // Predicates = [HasStdExtZvksh]201 202} // ElementsDependOn = EltDepsVLMask203 204//===----------------------------------------------------------------------===//205// Pseudo instructions206//===----------------------------------------------------------------------===//207 208defvar I32IntegerVectors = !filter(vti, AllIntegerVectors, !eq(vti.SEW, 32));209 210class ZvkI32IntegerVectors<string vd_lmul> {211 list<VTypeInfo> vs2_types = !cond(!eq(vd_lmul, "M8") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 32)),212 !eq(vd_lmul, "M4") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 32)),213 !eq(vd_lmul, "M2") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 16)),214 !eq(vd_lmul, "M1") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 8)),215 !eq(vd_lmul, "MF2") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 4)),216 !eq(vd_lmul, "MF4") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 2)),217 !eq(vd_lmul, "MF8") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 1)));218}219 220class ZvkMxSet<string vd_lmul> {221 list<LMULInfo> vs2_lmuls = !cond(!eq(vd_lmul, "M8") : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4],222 !eq(vd_lmul, "M4") : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4],223 !eq(vd_lmul, "M2") : [V_MF8, V_MF4, V_MF2, V_M1, V_M2],224 !eq(vd_lmul, "M1") : [V_MF8, V_MF4, V_MF2, V_M1],225 !eq(vd_lmul, "MF2") : [V_MF8, V_MF4, V_MF2],226 !eq(vd_lmul, "MF4") : [V_MF8, V_MF4],227 !eq(vd_lmul, "MF8") : [V_MF8]);228}229 230class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :231 RISCVVPseudo<(outs RetClass:$rd_wb),232 (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []> {233 let mayLoad = 0;234 let mayStore = 0;235 let hasSideEffects = 0;236 let Constraints = "$rd_wb = $rd";237 let HasVLOp = 1;238 let HasSEWOp = 1;239 let HasVecPolicyOp = 1;240 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);241}242 243class VPseudoTernaryNoMask_Zvk<VReg RetClass,244 VReg Op1Class,245 DAGOperand Op2Class> :246 RISCVVPseudo<(outs RetClass:$rd_wb),247 (ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,248 AVL:$vl, sew:$sew, vec_policy:$policy), []> {249 let mayLoad = 0;250 let mayStore = 0;251 let hasSideEffects = 0;252 let Constraints = "$rd_wb = $rd";253 let HasVLOp = 1;254 let HasSEWOp = 1;255 let HasVecPolicyOp = 1;256 let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);257}258 259multiclass VPseudoBinaryNoMaskPolicy_Zvk<VReg RetClass,260 VReg Op1Class,261 DAGOperand Op2Class,262 LMULInfo MInfo,263 string Constraint = ""> {264 let VLMul = MInfo.value in {265 def "_" # MInfo.MX : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,266 Constraint>;267 }268}269 270multiclass VPseudoTernaryNoMask_Zvk<VReg RetClass,271 VReg Op1Class,272 DAGOperand Op2Class,273 LMULInfo MInfo, int sew = 0> {274 let VLMul = MInfo.value, SEW = sew in {275 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);276 def suffix : VPseudoTernaryNoMask_Zvk<RetClass, Op1Class, Op2Class>;277 }278}279 280multiclass VPseudoBinaryV_V_NoMask_Zvk<LMULInfo m> {281 let VLMul = m.value in {282 def "_VV_" # m.MX : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass>;283 }284}285 286multiclass VPseudoBinaryV_S_NoMask_Zvk<LMULInfo m> {287 let VLMul = m.value in288 foreach vs2_lmul = ZvkMxSet<m.MX>.vs2_lmuls in289 def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoBinaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass>;290}291 292multiclass VPseudoVGMUL {293 foreach m = MxListVF4 in {294 defvar mx = m.MX;295 defm "" : VPseudoBinaryV_V_NoMask_Zvk<m>,296 SchedBinary<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV", mx>;297 }298}299 300multiclass VPseudoVAESMV {301 foreach m = MxListVF4 in {302 defvar mx = m.MX;303 defm "" : VPseudoBinaryV_V_NoMask_Zvk<m>,304 SchedBinary<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV", mx>;305 defm "" : VPseudoBinaryV_S_NoMask_Zvk<m>,306 SchedBinary<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV", mx>;307 308 }309}310 311multiclass VPseudoVSM4R {312 foreach m = MxListVF4 in {313 defvar mx = m.MX;314 defm "" : VPseudoBinaryV_V_NoMask_Zvk<m>,315 SchedBinary<"WriteVSM4RV", "ReadVSM4RV", "ReadVSM4RV", mx>;316 defm "" : VPseudoBinaryV_S_NoMask_Zvk<m>,317 SchedBinary<"WriteVSM4RV", "ReadVSM4RV", "ReadVSM4RV", mx>;318 319 }320}321 322multiclass VPseudoVGHSH {323 foreach m = MxListVF4 in {324 defvar mx = m.MX;325 defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,326 SchedTernary<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",327 "ReadVGHSHV", mx>;328 }329}330 331multiclass VPseudoVSHA2CH {332 foreach m = MxListVF4 in {333 defvar mx = m.MX;334 defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,335 SchedTernary<"WriteVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV",336 "ReadVSHA2CHV", mx>;337 }338}339 340multiclass VPseudoVSHA2CL {341 foreach m = MxListVF4 in {342 defvar mx = m.MX;343 defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,344 SchedTernary<"WriteVSHA2CLV", "ReadVSHA2CLV", "ReadVSHA2CLV",345 "ReadVSHA2CLV", mx>;346 }347}348 349multiclass VPseudoVSHA2MS<int sew = 0> {350 foreach m = !if(!eq(sew, 64), MxListVF8, MxListVF4) in {351 defvar mx = m.MX;352 defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m, sew = sew>,353 SchedTernary<"WriteVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV",354 "ReadVSHA2MSV", mx, sew>;355 }356}357 358multiclass VPseudoVAESKF1 {359 foreach m = MxListVF4 in {360 defvar mx = m.MX;361 defm _VI : VPseudoBinaryNoMaskPolicy_Zvk<m.vrclass, m.vrclass, uimm5, m>,362 SchedBinary<"WriteVAESKF1V", "ReadVAESKF1V", "ReadVAESKF1V", mx,363 forcePassthruRead=true>;364 }365}366 367multiclass VPseudoVAESKF2 {368 foreach m = MxListVF4 in {369 defvar mx = m.MX;370 defm _VI : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, uimm5, m>,371 SchedTernary<"WriteVAESKF2V", "ReadVAESKF2V", "ReadVAESKF2V",372 "ReadVAESKF2V", mx>;373 }374}375 376multiclass VPseudoVAESZ {377 foreach m = MxListVF4 in {378 defvar mx = m.MX;379 defm "" : VPseudoBinaryV_S_NoMask_Zvk<m>,380 SchedBinary<"WriteVAESZV", "ReadVAESZV", "ReadVAESZV", mx>;381 }382}383 384multiclass VPseudoVSM3C {385 foreach m = MxListVF4 in {386 defvar mx = m.MX;387 defm _VI : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, uimm5, m>,388 SchedTernary<"WriteVSM3CV", "ReadVSM3CV", "ReadVSM3CV",389 "ReadVSM3CV", mx>;390 }391}392 393multiclass VPseudoVSM4K {394 foreach m = MxListVF4 in {395 defvar mx = m.MX;396 defm _VI : VPseudoBinaryNoMaskPolicy_Zvk<m.vrclass, m.vrclass, uimm5, m>,397 SchedBinary<"WriteVSM4KV", "ReadVSM4KV", "ReadVSM4KV", mx,398 forcePassthruRead=true>;399 }400}401 402multiclass VPseudoVSM3ME {403 foreach m = MxListVF4 in {404 defvar mx = m.MX;405 defm _VV : VPseudoBinaryNoMaskPolicy_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,406 SchedBinary<"WriteVSM3MEV", "ReadVSM3MEV", "ReadVSM3MEV", mx,407 forcePassthruRead=true>;408 }409}410 411multiclass VPseudoVCLMUL_VV_VX {412 foreach m = MxList in {413 defvar mx = m.MX;414 defm "" : VPseudoBinaryV_VV<m>,415 SchedBinary<"WriteVCLMULV", "ReadVCLMULV", "ReadVCLMULV", mx,416 forcePassthruRead=true>;417 defm "" : VPseudoBinaryV_VX<m>,418 SchedBinary<"WriteVCLMULX", "ReadVCLMULV", "ReadVCLMULX", mx,419 forcePassthruRead=true>;420 }421}422 423multiclass VPseudoUnaryV_V<LMULInfo m> {424 let VLMul = m.value in {425 defvar suffix = "_V_" # m.MX;426 def suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>;427 def suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,428 RISCVMaskedPseudo<MaskIdx=2>;429 }430}431 432multiclass VPseudoVBREV {433 foreach m = MxList in {434 defvar mx = m.MX;435 defm "" : VPseudoUnaryV_V<m>,436 SchedUnary<"WriteVBREVV", "ReadVBREVV", mx, forcePassthruRead=true>;437 }438}439 440multiclass VPseudoVCLZ {441 foreach m = MxList in {442 defvar mx = m.MX;443 defm "" : VPseudoUnaryV_V<m>,444 SchedUnary<"WriteVCLZV", "ReadVCLZV", mx, forcePassthruRead=true>;445 }446}447 448multiclass VPseudoVCTZ {449 foreach m = MxList in {450 defvar mx = m.MX;451 defm "" : VPseudoUnaryV_V<m>,452 SchedUnary<"WriteVCTZV", "ReadVCTZV", mx, forcePassthruRead=true>;453 }454}455 456multiclass VPseudoVCPOP {457 foreach m = MxList in {458 defvar mx = m.MX;459 defm "" : VPseudoUnaryV_V<m>,460 SchedUnary<"WriteVCPOPV", "ReadVCPOPV", mx, forcePassthruRead=true>;461 }462}463 464multiclass VPseudoVWSLL {465 foreach m = MxListW in {466 defvar mx = m.MX;467 defm "" : VPseudoBinaryW_VV<m>,468 SchedBinary<"WriteVWSLLV", "ReadVWSLLV", "ReadVWSLLV", mx,469 forcePassthruRead=true>;470 defm "" : VPseudoBinaryW_VX<m>,471 SchedBinary<"WriteVWSLLX", "ReadVWSLLV", "ReadVWSLLX", mx,472 forcePassthruRead=true>;473 defm "" : VPseudoBinaryW_VI<uimm5, m>,474 SchedUnary<"WriteVWSLLI", "ReadVWSLLV", mx,475 forcePassthruRead=true>;476 }477}478 479multiclass VPseudoVANDN {480 foreach m = MxList in {481 defm "" : VPseudoBinaryV_VV<m>,482 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,483 forcePassthruRead=true>;484 defm "" : VPseudoBinaryV_VX<m>,485 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX,486 forcePassthruRead=true>;487 }488}489 490multiclass VPseudoVBREV8 {491 foreach m = MxList in {492 defvar mx = m.MX;493 defm "" : VPseudoUnaryV_V<m>,494 SchedUnary<"WriteVBREV8V", "ReadVBREV8V", mx, forcePassthruRead=true>;495 }496}497 498multiclass VPseudoVREV8 {499 foreach m = MxList in {500 defvar mx = m.MX;501 defm "" : VPseudoUnaryV_V<m>,502 SchedUnary<"WriteVREV8V", "ReadVREV8V", mx, forcePassthruRead=true>;503 }504}505 506multiclass VPseudoVROT_VV_VX {507 foreach m = MxList in {508 defm "" : VPseudoBinaryV_VV<m>,509 SchedBinary<"WriteVRotV", "ReadVRotV", "ReadVRotV", m.MX,510 forcePassthruRead=true>;511 defm "" : VPseudoBinaryV_VX<m>,512 SchedBinary<"WriteVRotX", "ReadVRotV", "ReadVRotX", m.MX,513 forcePassthruRead=true>;514 }515}516 517multiclass VPseudoVROT_VV_VX_VI518 : VPseudoVROT_VV_VX {519 foreach m = MxList in {520 defm "" : VPseudoBinaryV_VI<uimm6, m>,521 SchedUnary<"WriteVRotI", "ReadVRotV", m.MX,522 forcePassthruRead=true>;523 }524}525 526let Predicates = [HasStdExtZvbb] in {527 defm PseudoVBREV : VPseudoVBREV;528 defm PseudoVCLZ : VPseudoVCLZ;529 defm PseudoVCTZ : VPseudoVCTZ;530 defm PseudoVCPOP : VPseudoVCPOP;531 defm PseudoVWSLL : VPseudoVWSLL;532} // Predicates = [HasStdExtZvbb]533 534let Predicates = [HasStdExtZvbc] in {535 defm PseudoVCLMUL : VPseudoVCLMUL_VV_VX;536 defm PseudoVCLMULH : VPseudoVCLMUL_VV_VX;537} // Predicates = [HasStdExtZvbc]538 539let Predicates = [HasStdExtZvkb] in {540 defm PseudoVANDN : VPseudoVANDN;541 defm PseudoVBREV8 : VPseudoVBREV8;542 defm PseudoVREV8 : VPseudoVREV8;543 defm PseudoVROL : VPseudoVROT_VV_VX;544 defm PseudoVROR : VPseudoVROT_VV_VX_VI;545} // Predicates = [HasStdExtZvkb]546 547let Predicates = [HasStdExtZvkg] in {548 defm PseudoVGHSH : VPseudoVGHSH;549 defm PseudoVGMUL : VPseudoVGMUL;550} // Predicates = [HasStdExtZvkg]551 552let Predicates = [HasStdExtZvkned] in {553 defm PseudoVAESDF : VPseudoVAESMV;554 defm PseudoVAESDM : VPseudoVAESMV;555 defm PseudoVAESEF : VPseudoVAESMV;556 defm PseudoVAESEM : VPseudoVAESMV;557 defm PseudoVAESKF1 : VPseudoVAESKF1;558 defm PseudoVAESKF2 : VPseudoVAESKF2;559 defm PseudoVAESZ : VPseudoVAESZ;560} // Predicates = [HasStdExtZvkned]561 562let Predicates = [HasStdExtZvknhaOrZvknhb] in {563 defm PseudoVSHA2CH : VPseudoVSHA2CH;564 defm PseudoVSHA2CL : VPseudoVSHA2CL;565 defm PseudoVSHA2MS : VPseudoVSHA2MS<sew=32>;566 let Predicates = [HasStdExtZvknhb] in567 defm PseudoVSHA2MS : VPseudoVSHA2MS<sew=64>;568} // Predicates = [HasStdExtZvknhaOrZvknhb]569 570let Predicates = [HasStdExtZvksed] in {571 defm PseudoVSM4K : VPseudoVSM4K;572 defm PseudoVSM4R : VPseudoVSM4R;573} // Predicates = [HasStdExtZvksed]574 575let Predicates = [HasStdExtZvksh] in {576 defm PseudoVSM3C : VPseudoVSM3C;577 defm PseudoVSM3ME : VPseudoVSM3ME;578} // Predicates = [HasStdExtZvksh]579 580//===----------------------------------------------------------------------===//581// SDNode patterns582//===----------------------------------------------------------------------===//583 584multiclass VPatUnarySDNode_V<SDPatternOperator op, string instruction_name,585 Predicate predicate = HasStdExtZvbb> {586 foreach vti = AllIntegerVectors in {587 let Predicates = !listconcat([predicate],588 GetVTypePredicates<vti>.Predicates) in {589 def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1))),590 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX)591 (vti.Vector (IMPLICIT_DEF)),592 vti.RegClass:$rs1,593 vti.AVL, vti.Log2SEW, TA_MA)>;594 }595 }596}597 598// Helpers for detecting splats since we preprocess splat_vector to vmv.v.x599// This should match the logic in RISCVDAGToDAGISel::selectVSplat600def riscv_splat_vector : PatFrag<(ops node:$rs1),601 (riscv_vmv_v_x_vl undef, node:$rs1, srcvalue)>;602def allonessew8 : ImmLeaf<XLenVT, "return SignExtend64<8>(Imm) == -1LL;">;603def allonessew16 : ImmLeaf<XLenVT, "return SignExtend64<16>(Imm) == -1LL;">;604def allonessew32 : ImmLeaf<XLenVT, "return SignExtend64<32>(Imm) == -1LL;">;605def allonessew64 : ImmLeaf<XLenVT, "return Imm == -1LL;">;606 607foreach vti = AllIntegerVectors in {608 let Predicates = !listconcat([HasStdExtZvkb],609 GetVTypePredicates<vti>.Predicates) in {610 def : Pat<(vti.Vector (and (xor vti.RegClass:$rs1,611 (riscv_splat_vector !cast<ImmLeaf>("allonessew"#vti.SEW))),612 vti.RegClass:$rs2)),613 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)614 (vti.Vector (IMPLICIT_DEF)),615 vti.RegClass:$rs2,616 vti.RegClass:$rs1,617 vti.AVL, vti.Log2SEW, TA_MA)>;618 def : Pat<(vti.Vector (and (riscv_splat_vector619 (not vti.ScalarRegClass:$rs1)),620 vti.RegClass:$rs2)),621 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)622 (vti.Vector (IMPLICIT_DEF)),623 vti.RegClass:$rs2,624 vti.ScalarRegClass:$rs1,625 vti.AVL, vti.Log2SEW, TA_MA)>;626 def : Pat<(vti.Vector (and (riscv_splat_vector invLogicImm:$rs1),627 vti.RegClass:$rs2)),628 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)629 (vti.Vector (IMPLICIT_DEF)),630 vti.RegClass:$rs2,631 invLogicImm:$rs1,632 vti.AVL, vti.Log2SEW, TA_MA)>;633 }634}635 636defm : VPatUnarySDNode_V<bitreverse, "PseudoVBREV">;637defm : VPatUnarySDNode_V<bswap, "PseudoVREV8", HasStdExtZvkb>;638defm : VPatUnarySDNode_V<ctlz, "PseudoVCLZ">;639defm : VPatUnarySDNode_V<cttz, "PseudoVCTZ">;640defm : VPatUnarySDNode_V<ctpop, "PseudoVCPOP">;641 642defm : VPatBinarySDNode_VV_VX<rotl, "PseudoVROL">;643 644// Invert the immediate and mask it to SEW for readability.645def InvRot8Imm : SDNodeXForm<imm, [{646 return CurDAG->getTargetConstant(0x7 & (64 - N->getZExtValue()), SDLoc(N),647 N->getValueType(0));648}]>;649def InvRot16Imm : SDNodeXForm<imm, [{650 return CurDAG->getTargetConstant(0xf & (64 - N->getZExtValue()), SDLoc(N),651 N->getValueType(0));652}]>;653def InvRot32Imm : SDNodeXForm<imm, [{654 return CurDAG->getTargetConstant(0x1f & (64 - N->getZExtValue()), SDLoc(N),655 N->getValueType(0));656}]>;657def InvRot64Imm : SDNodeXForm<imm, [{658 return CurDAG->getTargetConstant(0x3f & (64 - N->getZExtValue()), SDLoc(N),659 N->getValueType(0));660}]>;661 662// Although there is no vrol.vi, an immediate rotate left can be achieved by663// negating the immediate in vror.vi664foreach vti = AllIntegerVectors in {665 let Predicates = !listconcat([HasStdExtZvkb],666 GetVTypePredicates<vti>.Predicates) in {667 def : Pat<(vti.Vector (rotl vti.RegClass:$rs2,668 (vti.Vector (SplatPat_uimm6 uimm6:$rs1)))),669 (!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX)670 (vti.Vector (IMPLICIT_DEF)),671 vti.RegClass:$rs2,672 (!cast<SDNodeXForm>("InvRot" # vti.SEW # "Imm") uimm6:$rs1),673 vti.AVL, vti.Log2SEW, TA_MA)>;674 }675}676defm : VPatBinarySDNode_VV_VX_VI<rotr, "PseudoVROR", uimm6>;677 678foreach vtiToWti = AllWidenableIntVectors in {679 defvar vti = vtiToWti.Vti;680 defvar wti = vtiToWti.Wti;681 let Predicates = !listconcat([HasStdExtZvbb],682 GetVTypePredicates<vti>.Predicates,683 GetVTypePredicates<wti>.Predicates) in {684 def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs2))),685 (wti.Vector (ext_oneuse (vti.Vector vti.RegClass:$rs1)))),686 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX)687 (wti.Vector (IMPLICIT_DEF)),688 vti.RegClass:$rs2, vti.RegClass:$rs1,689 vti.AVL, vti.Log2SEW, TA_MA)>;690 691 def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs2))),692 (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1)))),693 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX)694 (wti.Vector (IMPLICIT_DEF)),695 vti.RegClass:$rs2, GPR:$rs1,696 vti.AVL, vti.Log2SEW, TA_MA)>;697 698 def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs2))),699 (wti.Vector (SplatPat_uimm5 uimm5:$rs1))),700 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX)701 (wti.Vector (IMPLICIT_DEF)),702 vti.RegClass:$rs2, uimm5:$rs1,703 vti.AVL, vti.Log2SEW, TA_MA)>;704 }705}706 707//===----------------------------------------------------------------------===//708// VL patterns709//===----------------------------------------------------------------------===//710 711multiclass VPatUnaryVL_V<SDPatternOperator op, string instruction_name,712 Predicate predicate = HasStdExtZvbb> {713 foreach vti = AllIntegerVectors in {714 let Predicates = !listconcat([predicate],715 GetVTypePredicates<vti>.Predicates) in {716 def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1),717 (vti.Vector vti.RegClass:$passthru),718 (vti.Mask VMV0:$vm),719 VLOpFrag)),720 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX#"_MASK")721 vti.RegClass:$passthru,722 vti.RegClass:$rs1,723 (vti.Mask VMV0:$vm),724 GPR:$vl,725 vti.Log2SEW,726 TAIL_AGNOSTIC)>;727 }728 }729}730 731foreach vti = AllIntegerVectors in {732 let Predicates = !listconcat([HasStdExtZvkb],733 GetVTypePredicates<vti>.Predicates) in {734 def : Pat<(vti.Vector (riscv_and_vl (riscv_xor_vl735 (vti.Vector vti.RegClass:$rs1),736 (riscv_splat_vector !cast<ImmLeaf>("allonessew"#vti.SEW)),737 (vti.Vector vti.RegClass:$passthru),738 (vti.Mask VMV0:$vm),739 VLOpFrag),740 (vti.Vector vti.RegClass:$rs2),741 (vti.Vector vti.RegClass:$passthru),742 (vti.Mask VMV0:$vm),743 VLOpFrag)),744 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX#"_MASK")745 vti.RegClass:$passthru,746 vti.RegClass:$rs2,747 vti.RegClass:$rs1,748 (vti.Mask VMV0:$vm),749 GPR:$vl,750 vti.Log2SEW,751 TAIL_AGNOSTIC)>;752 753 def : Pat<(vti.Vector (riscv_and_vl (riscv_splat_vector754 (not vti.ScalarRegClass:$rs1)),755 (vti.Vector vti.RegClass:$rs2),756 (vti.Vector vti.RegClass:$passthru),757 (vti.Mask VMV0:$vm),758 VLOpFrag)),759 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX#"_MASK")760 vti.RegClass:$passthru,761 vti.RegClass:$rs2,762 vti.ScalarRegClass:$rs1,763 (vti.Mask VMV0:$vm),764 GPR:$vl,765 vti.Log2SEW,766 TAIL_AGNOSTIC)>;767 768 def : Pat<(vti.Vector (riscv_and_vl (riscv_splat_vector invLogicImm:$rs1),769 (vti.Vector vti.RegClass:$rs2),770 (vti.Vector vti.RegClass:$passthru),771 (vti.Mask VMV0:$vm),772 VLOpFrag)),773 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX#"_MASK")774 vti.RegClass:$passthru,775 vti.RegClass:$rs2,776 invLogicImm:$rs1,777 (vti.Mask VMV0:$vm),778 GPR:$vl,779 vti.Log2SEW,780 TAIL_AGNOSTIC)>;781 }782}783 784defm : VPatUnaryVL_V<riscv_bitreverse_vl, "PseudoVBREV">;785defm : VPatUnaryVL_V<riscv_bswap_vl, "PseudoVREV8", HasStdExtZvkb>;786defm : VPatUnaryVL_V<riscv_ctlz_vl, "PseudoVCLZ">;787defm : VPatUnaryVL_V<riscv_cttz_vl, "PseudoVCTZ">;788defm : VPatUnaryVL_V<riscv_ctpop_vl, "PseudoVCPOP">;789 790defm : VPatBinaryVL_VV_VX<riscv_rotl_vl, "PseudoVROL">;791// Although there is no vrol.vi, an immediate rotate left can be achieved by792// negating the immediate in vror.vi793foreach vti = AllIntegerVectors in {794 let Predicates = !listconcat([HasStdExtZvkb],795 GetVTypePredicates<vti>.Predicates) in {796 def : Pat<(riscv_rotl_vl vti.RegClass:$rs2,797 (vti.Vector (SplatPat_uimm6 uimm6:$rs1)),798 (vti.Vector vti.RegClass:$passthru),799 (vti.Mask VMV0:$vm), VLOpFrag),800 (!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX#"_MASK")801 vti.RegClass:$passthru,802 vti.RegClass:$rs2,803 (!cast<SDNodeXForm>("InvRot" # vti.SEW # "Imm") uimm6:$rs1),804 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;805 }806}807defm : VPatBinaryVL_VV_VX_VI<riscv_rotr_vl, "PseudoVROR", uimm6>;808 809foreach vtiToWti = AllWidenableIntVectors in {810 defvar vti = vtiToWti.Vti;811 defvar wti = vtiToWti.Wti;812 let Predicates = !listconcat([HasStdExtZvbb],813 GetVTypePredicates<vti>.Predicates,814 GetVTypePredicates<wti>.Predicates) in {815 def : Pat<(riscv_shl_vl816 (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs2))),817 (wti.Vector (ext_oneuse (vti.Vector vti.RegClass:$rs1))),818 (wti.Vector wti.RegClass:$passthru),819 (vti.Mask VMV0:$vm), VLOpFrag),820 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")821 wti.RegClass:$passthru, vti.RegClass:$rs2, vti.RegClass:$rs1,822 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;823 824 def : Pat<(riscv_shl_vl825 (wti.Vector (riscv_zext_vl_oneuse826 (vti.Vector vti.RegClass:$rs2),827 (vti.Mask VMV0:$vm), VLOpFrag)),828 (wti.Vector (riscv_ext_vl_oneuse829 (vti.Vector vti.RegClass:$rs1),830 (vti.Mask VMV0:$vm), VLOpFrag)),831 (wti.Vector wti.RegClass:$passthru),832 (vti.Mask VMV0:$vm), VLOpFrag),833 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")834 wti.RegClass:$passthru, vti.RegClass:$rs2, vti.RegClass:$rs1,835 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;836 837 def : Pat<(riscv_shl_vl838 (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs2))),839 (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1))),840 (wti.Vector wti.RegClass:$passthru),841 (vti.Mask VMV0:$vm), VLOpFrag),842 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")843 wti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$rs1,844 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;845 846 def : Pat<(riscv_shl_vl847 (wti.Vector (riscv_zext_vl_oneuse848 (vti.Vector vti.RegClass:$rs2),849 (vti.Mask VMV0:$vm), VLOpFrag)),850 (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1))),851 (wti.Vector wti.RegClass:$passthru),852 (vti.Mask VMV0:$vm), VLOpFrag),853 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")854 wti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$rs1,855 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;856 857 def : Pat<(riscv_shl_vl858 (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs2))),859 (wti.Vector (SplatPat_uimm5 uimm5:$rs1)),860 (wti.Vector wti.RegClass:$passthru),861 (vti.Mask VMV0:$vm), VLOpFrag),862 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")863 wti.RegClass:$passthru, vti.RegClass:$rs2, uimm5:$rs1,864 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;865 866 def : Pat<(riscv_shl_vl867 (wti.Vector (riscv_zext_vl_oneuse868 (vti.Vector vti.RegClass:$rs2),869 (vti.Mask VMV0:$vm), VLOpFrag)),870 (wti.Vector (SplatPat_uimm5 uimm5:$rs1)),871 (wti.Vector wti.RegClass:$passthru),872 (vti.Mask VMV0:$vm), VLOpFrag),873 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")874 wti.RegClass:$passthru, vti.RegClass:$rs2, uimm5:$rs1,875 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;876 877 def : Pat<(riscv_vwsll_vl878 (vti.Vector vti.RegClass:$rs2),879 (vti.Vector vti.RegClass:$rs1),880 (wti.Vector wti.RegClass:$passthru),881 (vti.Mask VMV0:$vm), VLOpFrag),882 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")883 wti.RegClass:$passthru, vti.RegClass:$rs2, vti.RegClass:$rs1,884 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;885 886 def : Pat<(riscv_vwsll_vl887 (vti.Vector vti.RegClass:$rs2),888 (vti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1))),889 (wti.Vector wti.RegClass:$passthru),890 (vti.Mask VMV0:$vm), VLOpFrag),891 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")892 wti.RegClass:$passthru, vti.RegClass:$rs2, GPR:$rs1,893 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;894 895 def : Pat<(riscv_vwsll_vl896 (vti.Vector vti.RegClass:$rs2),897 (vti.Vector (SplatPat_uimm5 uimm5:$rs1)),898 (wti.Vector wti.RegClass:$passthru),899 (vti.Mask VMV0:$vm), VLOpFrag),900 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")901 wti.RegClass:$passthru, vti.RegClass:$rs2, uimm5:$rs1,902 (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;903 }904}905 906//===----------------------------------------------------------------------===//907// Codegen patterns908//===----------------------------------------------------------------------===//909 910class VPatUnaryNoMask_Zvk<string intrinsic_name,911 string inst,912 string kind,913 ValueType result_type,914 ValueType op2_type,915 int sew,916 LMULInfo vlmul,917 VReg result_reg_class,918 VReg op2_reg_class> :919 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)920 (result_type result_reg_class:$rd),921 (op2_type op2_reg_class:$rs2),922 VLOpFrag, (XLenVT timm:$policy))),923 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)924 (result_type result_reg_class:$rd),925 (op2_type op2_reg_class:$rs2),926 GPR:$vl, sew, (XLenVT timm:$policy))>;927 928class VPatUnaryNoMask_VS_Zvk<string intrinsic_name,929 string inst,930 string kind,931 ValueType result_type,932 ValueType op2_type,933 int sew,934 LMULInfo vlmul,935 LMULInfo vs2_lmul,936 VReg result_reg_class,937 VReg op2_reg_class> :938 Pat<(result_type (!cast<Intrinsic>(intrinsic_name)939 (result_type result_reg_class:$rd),940 (op2_type op2_reg_class:$rs2),941 VLOpFrag, (XLenVT timm:$policy))),942 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_"#vs2_lmul.MX)943 (result_type result_reg_class:$rd),944 (op2_type op2_reg_class:$rs2),945 GPR:$vl, sew, (XLenVT timm:$policy))>;946 947multiclass VPatUnaryV_V_NoMask_Zvk<string intrinsic, string instruction,948 list<VTypeInfo> vtilist> {949 foreach vti = vtilist in950 def : VPatUnaryNoMask_Zvk<intrinsic # "_vv", instruction, "VV",951 vti.Vector, vti.Vector, vti.Log2SEW,952 vti.LMul, vti.RegClass, vti.RegClass>;953}954 955multiclass VPatUnaryV_S_NoMaskVectorCrypto<string intrinsic, string instruction,956 list<VTypeInfo> vtilist> {957 foreach vti = vtilist in958 foreach vti_vs2 = ZvkI32IntegerVectors<vti.LMul.MX>.vs2_types in959 def : VPatUnaryNoMask_VS_Zvk<intrinsic # "_vs", instruction, "VS",960 vti.Vector, vti_vs2.Vector, vti.Log2SEW,961 vti.LMul, vti_vs2.LMul, vti.RegClass, vti_vs2.RegClass>;962}963 964multiclass VPatUnaryV_V_S_NoMask_Zvk<string intrinsic, string instruction,965 list<VTypeInfo> vtilist> {966 defm : VPatUnaryV_V_NoMask_Zvk<intrinsic, instruction, vtilist>;967 defm : VPatUnaryV_S_NoMaskVectorCrypto<intrinsic, instruction, vtilist>;968}969 970multiclass VPatBinaryV_VV_NoMask<string intrinsic, string instruction,971 list<VTypeInfo> vtilist,972 bit isSEWAware = false> {973 foreach vti = vtilist in974 def : VPatTernaryNoMaskWithPolicy<intrinsic, instruction, "VV",975 vti.Vector, vti.Vector, vti.Vector,976 vti.Log2SEW, vti.LMul, vti.RegClass,977 vti.RegClass, vti.RegClass,978 isSEWAware = isSEWAware>;979}980 981multiclass VPatBinaryV_VI_NoMask<string intrinsic, string instruction,982 list<VTypeInfo> vtilist,983 Operand imm_type = tuimm5> {984 foreach vti = vtilist in985 def : VPatTernaryNoMaskWithPolicy<intrinsic, instruction, "VI",986 vti.Vector, vti.Vector, XLenVT,987 vti.Log2SEW, vti.LMul, vti.RegClass,988 vti.RegClass, imm_type>;989}990 991multiclass VPatBinaryV_VI_NoMaskTU<string intrinsic, string instruction,992 list<VTypeInfo> vtilist,993 Operand imm_type = tuimm5> {994 foreach vti = vtilist in995 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VI_" # vti.LMul.MX,996 vti.Vector, vti.Vector, XLenVT, vti.Log2SEW,997 vti.RegClass, vti.RegClass, imm_type>;998}999 1000multiclass VPatBinaryV_VV_NoMaskTU<string intrinsic, string instruction,1001 list<VTypeInfo> vtilist> {1002 foreach vti = vtilist in1003 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VV_" # vti.LMul.MX,1004 vti.Vector, vti.Vector, vti.Vector, vti.Log2SEW,1005 vti.RegClass, vti.RegClass, vti.RegClass>;1006}1007 1008multiclass VPatBinaryV_VX_VROTATE<string intrinsic, string instruction,1009 list<VTypeInfo> vtilist, bit isSEWAware = 0> {1010 foreach vti = vtilist in {1011 defvar kind = "V"#vti.ScalarSuffix;1012 let Predicates = GetVTypePredicates<vti>.Predicates in1013 defm : VPatBinary<intrinsic,1014 !if(isSEWAware,1015 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,1016 instruction#"_"#kind#"_"#vti.LMul.MX),1017 vti.Vector, vti.Vector, XLenVT, vti.Mask,1018 vti.Log2SEW, vti.RegClass,1019 vti.RegClass, vti.ScalarRegClass>;1020 }1021}1022 1023multiclass VPatBinaryV_VI_VROL<string intrinsic, string instruction,1024 list<VTypeInfo> vtilist, bit isSEWAware = 0> {1025 foreach vti = vtilist in {1026 defvar Intr = !cast<Intrinsic>(intrinsic);1027 defvar Pseudo = !cast<Instruction>(1028 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW,1029 instruction#"_VI_"#vti.LMul.MX));1030 let Predicates = GetVTypePredicates<vti>.Predicates in1031 def : Pat<(vti.Vector (Intr (vti.Vector vti.RegClass:$passthru),1032 (vti.Vector vti.RegClass:$rs2),1033 (XLenVT uimm6:$rs1),1034 VLOpFrag)),1035 (Pseudo (vti.Vector vti.RegClass:$passthru),1036 (vti.Vector vti.RegClass:$rs2),1037 (InvRot64Imm uimm6:$rs1),1038 GPR:$vl, vti.Log2SEW, TU_MU)>;1039 1040 defvar IntrMask = !cast<Intrinsic>(intrinsic#"_mask");1041 defvar PseudoMask = !cast<Instruction>(1042 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK",1043 instruction#"_VI_"#vti.LMul.MX#"_MASK"));1044 let Predicates = GetVTypePredicates<vti>.Predicates in1045 def : Pat<(vti.Vector (IntrMask (vti.Vector vti.RegClass:$passthru),1046 (vti.Vector vti.RegClass:$rs2),1047 (XLenVT uimm6:$rs1),1048 (vti.Mask VMV0:$vm),1049 VLOpFrag, (XLenVT timm:$policy))),1050 (PseudoMask (vti.Vector vti.RegClass:$passthru),1051 (vti.Vector vti.RegClass:$rs2),1052 (InvRot64Imm uimm6:$rs1),1053 (vti.Mask VMV0:$vm),1054 GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;1055 }1056}1057 1058multiclass VPatBinaryV_VV_VX_VROL<string intrinsic, string instruction,1059 string instruction2, list<VTypeInfo> vtilist>1060 : VPatBinaryV_VV<intrinsic, instruction, vtilist>,1061 VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,1062 VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist>;1063 1064multiclass VPatBinaryV_VV_VX_VI_VROR<string intrinsic, string instruction,1065 list<VTypeInfo> vtilist>1066 : VPatBinaryV_VV<intrinsic, instruction, vtilist>,1067 VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,1068 VPatBinaryV_VI<intrinsic, instruction, vtilist, uimm6>;1069 1070multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,1071 list<VTypeInfoToWide> vtilist>1072 : VPatBinaryW_VV<intrinsic, instruction, vtilist> {1073 foreach VtiToWti = vtilist in {1074 defvar Vti = VtiToWti.Vti;1075 defvar Wti = VtiToWti.Wti;1076 defvar kind = "V"#Vti.ScalarSuffix;1077 let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,1078 GetVTypePredicates<Wti>.Predicates) in {1079 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,1080 Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,1081 Vti.Log2SEW, Wti.RegClass,1082 Vti.RegClass, Vti.ScalarRegClass>;1083 defm : VPatBinary<intrinsic, instruction # "_VI_" # Vti.LMul.MX,1084 Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,1085 Vti.Log2SEW, Wti.RegClass,1086 Vti.RegClass, uimm5>;1087 }1088 }1089}1090 1091let Predicates = [HasStdExtZvbb] in {1092 defm : VPatUnaryV_V<"int_riscv_vbrev", "PseudoVBREV", AllIntegerVectors>;1093 defm : VPatUnaryV_V<"int_riscv_vclz", "PseudoVCLZ", AllIntegerVectors>;1094 defm : VPatUnaryV_V<"int_riscv_vctz", "PseudoVCTZ", AllIntegerVectors>;1095 defm : VPatUnaryV_V<"int_riscv_vcpopv", "PseudoVCPOP", AllIntegerVectors>;1096 defm : VPatBinaryW_VV_VX_VI_VWSLL<"int_riscv_vwsll", "PseudoVWSLL", AllWidenableIntVectors>;1097} // Predicates = [HasStdExtZvbb]1098 1099let Predicates = [HasStdExtZvbc] in {1100 defm : VPatBinaryV_VV_VX<"int_riscv_vclmul", "PseudoVCLMUL", I64IntegerVectors>;1101 defm : VPatBinaryV_VV_VX<"int_riscv_vclmulh", "PseudoVCLMULH", I64IntegerVectors>;1102} // Predicates = [HasStdExtZvbc]1103 1104let Predicates = [HasStdExtZvkb] in {1105 defm : VPatBinaryV_VV_VX<"int_riscv_vandn", "PseudoVANDN", AllIntegerVectors>;1106 defm : VPatUnaryV_V<"int_riscv_vbrev8", "PseudoVBREV8", AllIntegerVectors>;1107 defm : VPatUnaryV_V<"int_riscv_vrev8", "PseudoVREV8", AllIntegerVectors>;1108 defm : VPatBinaryV_VV_VX_VROL<"int_riscv_vrol", "PseudoVROL", "PseudoVROR", AllIntegerVectors>;1109 defm : VPatBinaryV_VV_VX_VI_VROR<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;1110} // Predicates = [HasStdExtZvkb]1111 1112let Predicates = [HasStdExtZvkg] in {1113 defm : VPatBinaryV_VV_NoMask<"int_riscv_vghsh", "PseudoVGHSH", I32IntegerVectors>;1114 defm : VPatUnaryV_V_NoMask_Zvk<"int_riscv_vgmul", "PseudoVGMUL", I32IntegerVectors>;1115} // Predicates = [HasStdExtZvkg]1116 1117let Predicates = [HasStdExtZvkned] in {1118 defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesdf", "PseudoVAESDF", I32IntegerVectors>;1119 defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesdm", "PseudoVAESDM", I32IntegerVectors>;1120 defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesef", "PseudoVAESEF", I32IntegerVectors>;1121 defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vaesem", "PseudoVAESEM", I32IntegerVectors>;1122 defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vaeskf1", "PseudoVAESKF1", I32IntegerVectors>;1123 defm : VPatBinaryV_VI_NoMask<"int_riscv_vaeskf2", "PseudoVAESKF2", I32IntegerVectors>;1124 defm : VPatUnaryV_S_NoMaskVectorCrypto<"int_riscv_vaesz", "PseudoVAESZ", I32IntegerVectors>;1125} // Predicates = [HasStdExtZvkned]1126 1127let Predicates = [HasStdExtZvknhaOrZvknhb] in {1128 defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32IntegerVectors>;1129 defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I32IntegerVectors>;1130 defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors, isSEWAware=true>;1131} // Predicates = [HasStdExtZvknha]1132 1133let Predicates = [HasStdExtZvknhb] in {1134 defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I64IntegerVectors>;1135 defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I64IntegerVectors>;1136 defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I64IntegerVectors, isSEWAware=true>;1137} // Predicates = [HasStdExtZvknhb]1138 1139let Predicates = [HasStdExtZvksed] in {1140 defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vsm4k", "PseudoVSM4K", I32IntegerVectors>;1141 defm : VPatUnaryV_V_S_NoMask_Zvk<"int_riscv_vsm4r", "PseudoVSM4R", I32IntegerVectors>;1142} // Predicates = [HasStdExtZvksed]1143 1144let Predicates = [HasStdExtZvksh] in {1145 defm : VPatBinaryV_VI_NoMask<"int_riscv_vsm3c", "PseudoVSM3C", I32IntegerVectors>;1146 defm : VPatBinaryV_VV_NoMaskTU<"int_riscv_vsm3me", "PseudoVSM3ME", I32IntegerVectors>;1147} // Predicates = [HasStdExtZvksh]1148