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1//===-- RISCVInstrInfoZvqdot.td - 'Zvqdotq' instructions ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instructions from the standard 'Zvqdotq'10// extension.11// This version is still experimental as the 'Zvqdotq' extension hasn't been12// ratified yet.13//14//===----------------------------------------------------------------------===//15 16//===----------------------------------------------------------------------===//17// Instructions18//===----------------------------------------------------------------------===//19 20class VQDOTVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>21 : RVInstVV<funct6, opv, (outs VR:$vd_wb),22 (ins VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm),23 opcodestr, "$vd, $vs2, $vs1$vm"> {24 let mayLoad = 0;25 let mayStore = 0;26 let hasSideEffects = 0;27 let Constraints = "$vd = $vd_wb";28}29 30class VQDOTVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>31 : RVInstVX<funct6, opv, (outs VR:$vd_wb),32 (ins VR:$vd, VR:$vs2, GPR:$rs1, VMaskOp:$vm),33 opcodestr, "$vd, $vs2, $rs1$vm"> {34 let mayLoad = 0;35 let mayStore = 0;36 let hasSideEffects = 0;37 let Constraints = "$vd = $vd_wb";38}39 40let Predicates = [HasStdExtZvqdotq] in {41 def VQDOT_VV : VQDOTVV<0b101100, OPMVV, "vqdot.vv">;42 def VQDOT_VX : VQDOTVX<0b101100, OPMVX, "vqdot.vx">;43 def VQDOTU_VV : VQDOTVV<0b101000, OPMVV, "vqdotu.vv">;44 def VQDOTU_VX : VQDOTVX<0b101000, OPMVX, "vqdotu.vx">;45 def VQDOTSU_VV : VQDOTVV<0b101010, OPMVV, "vqdotsu.vv">;46 def VQDOTSU_VX : VQDOTVX<0b101010, OPMVX, "vqdotsu.vx">;47 def VQDOTUS_VX : VQDOTVX<0b101110, OPMVX, "vqdotus.vx">;48} // Predicates = [HasStdExtZvqdotq]49 50//===----------------------------------------------------------------------===//51// Helpers to define the VL patterns.52//===----------------------------------------------------------------------===//53 54let HasPassthruOp = true, HasMaskOp = true in {55 def riscv_vqdot_vl : RVSDNode<"VQDOT_VL", SDT_RISCVIntBinOp_VL>;56 def riscv_vqdotu_vl : RVSDNode<"VQDOTU_VL", SDT_RISCVIntBinOp_VL>;57 def riscv_vqdotsu_vl : RVSDNode<"VQDOTSU_VL", SDT_RISCVIntBinOp_VL>;58} // let HasPassthruOp = true, HasMaskOp = true59 60//===----------------------------------------------------------------------===//61// Pseudo Instructions for CodeGen62//===----------------------------------------------------------------------===//63 64multiclass VPseudoVQDOT_VV_VX {65 foreach m = MxSet<32>.m in {66 defm "" : VPseudoBinaryV_VV<m>,67 SchedBinary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", m.MX,68 forcePassthruRead=true>;69 defm "" : VPseudoBinaryV_VX<m>,70 SchedBinary<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX", m.MX,71 forcePassthruRead=true>;72 }73}74 75// TODO: Add pseudo and patterns for vqdotus.vx76// TODO: Add isCommutable for VQDOT and VQDOTU77let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0,78 hasSideEffects = 0 in {79 defm PseudoVQDOT : VPseudoVQDOT_VV_VX;80 defm PseudoVQDOTU : VPseudoVQDOT_VV_VX;81 defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX;82 // VQDOTUS does not have a VV variant83 foreach m = MxListVF4 in {84 defm "PseudoVQDOTUS_VX" : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m>;85 }86}87 88//===----------------------------------------------------------------------===//89// Patterns.90//===----------------------------------------------------------------------===//91 92defvar AllE32Vectors = [VI32MF2, VI32M1, VI32M2, VI32M4, VI32M8];93defm : VPatBinaryVL_VV_VX<riscv_vqdot_vl, "PseudoVQDOT", AllE32Vectors>;94defm : VPatBinaryVL_VV_VX<riscv_vqdotu_vl, "PseudoVQDOTU", AllE32Vectors>;95defm : VPatBinaryVL_VV_VX<riscv_vqdotsu_vl, "PseudoVQDOTSU", AllE32Vectors>;96 97// These VPat definitions are for vqdot because they have a different operand98// order with other ternary instructions (i.e. vop.vx vd, vs2, rs1)99multiclass VPatTernaryV_VX_AABX<string intrinsic, string instruction,100 list<VTypeInfoToWide> info_pairs> {101 foreach pair = info_pairs in {102 defvar VdInfo = pair.Wti;103 defvar Vs2Info = pair.Vti;104 let Predicates = GetVTypePredicates<VdInfo>.Predicates in105 defm : VPatTernaryWithPolicy<intrinsic, instruction,106 "V"#VdInfo.ScalarSuffix,107 VdInfo.Vector, Vs2Info.Vector, Vs2Info.Scalar,108 VdInfo.Mask, VdInfo.Log2SEW, VdInfo.LMul,109 VdInfo.RegClass, Vs2Info.RegClass,110 Vs2Info.ScalarRegClass>;111 }112}113 114multiclass VPatTernaryV_VV_AABX<string intrinsic, string instruction,115 list<VTypeInfoToWide> info_pairs> {116 foreach pair = info_pairs in {117 defvar VdInfo = pair.Wti;118 defvar Vs2Info = pair.Vti;119 let Predicates = GetVTypePredicates<VdInfo>.Predicates in120 defm : VPatTernaryWithPolicy<intrinsic, instruction,121 "VV",122 VdInfo.Vector, Vs2Info.Vector, Vs2Info.Vector,123 VdInfo.Mask, VdInfo.Log2SEW, VdInfo.LMul,124 VdInfo.RegClass, Vs2Info.RegClass,125 Vs2Info.RegClass>;126 }127}128 129multiclass VPatTernaryV_VV_VX_AABX<string intrinsic, string instruction,130 list<VTypeInfoToWide> info_pairs>131 : VPatTernaryV_VV_AABX<intrinsic, instruction, info_pairs>,132 VPatTernaryV_VX_AABX<intrinsic, instruction, info_pairs>;133 134defset list<VTypeInfoToWide> VQDOTInfoPairs = {135 def : VTypeInfoToWide<VI8MF2, VI32MF2>;136 def : VTypeInfoToWide<VI8M1, VI32M1>;137 def : VTypeInfoToWide<VI8M2, VI32M2>;138 def : VTypeInfoToWide<VI8M4, VI32M4>;139 def : VTypeInfoToWide<VI8M8, VI32M8>;140}141 142let Predicates = [HasStdExtZvqdotq] in {143 defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vqdot", "PseudoVQDOT", VQDOTInfoPairs>;144 defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vqdotu", "PseudoVQDOTU", VQDOTInfoPairs>;145 defm : VPatTernaryV_VV_VX_AABX<"int_riscv_vqdotsu", "PseudoVQDOTSU", VQDOTInfoPairs>;146 defm : VPatTernaryV_VX_AABX<"int_riscv_vqdotus", "PseudoVQDOTUS", VQDOTInfoPairs>;147}148