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1//===-- RISCVInstrPredicates.td - Instruction Predicates ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the RISC-V instruction predicates.10//11//===----------------------------------------------------------------------===//12 13// This predicate is true when the rs2 operand of vlse or vsse is x0, false14// otherwise.15def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;16 17// This scheduling predicate is true when subtarget feature TuneHasSingleElementVecFP6418// is enabled.19def SingleElementVecFP64SchedPred : FeatureSchedPredicate<TuneHasSingleElementVecFP64>;20 21// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.22def isSEXT_W23 : TIIPredicate<"isSEXT_W",24 MCReturnStatement<CheckAll<[25 CheckOpcode<[ADDIW]>,26 CheckIsRegOperand<1>,27 CheckIsImmOperand<2>,28 CheckImmOperand<2, 0>29 ]>>>;30 31// Returns true if this is the zext.w pattern, adduw rd, rs1, x0.32def isZEXT_W33 : TIIPredicate<"isZEXT_W",34 MCReturnStatement<CheckAll<[35 CheckOpcode<[ADD_UW]>,36 CheckIsRegOperand<1>,37 CheckIsRegOperand<2>,38 CheckRegOperand<2, X0>39 ]>>>;40 41// Returns true if this is the zext.b pattern, andi rd, rs1, 255.42def isZEXT_B43 : TIIPredicate<"isZEXT_B",44 MCReturnStatement<CheckAll<[45 CheckOpcode<[ANDI]>,46 CheckIsRegOperand<1>,47 CheckIsImmOperand<2>,48 CheckImmOperand<2, 255>49 ]>>>;50 51def isSelectPseudo52 : TIIPredicate<"isSelectPseudo",53 MCReturnStatement<54 CheckOpcode<[55 Select_GPR_Using_CC_GPR,56 Select_GPR_Using_CC_Imm5_Zibi,57 Select_GPR_Using_CC_SImm5_CV,58 Select_GPRNoX0_Using_CC_SImm5NonZero_QC,59 Select_GPRNoX0_Using_CC_UImm5NonZero_QC,60 Select_GPRNoX0_Using_CC_SImm16NonZero_QC,61 Select_GPRNoX0_Using_CC_UImm16NonZero_QC,62 Select_GPR_Using_CC_UImmLog2XLen_NDS,63 Select_GPR_Using_CC_UImm7_NDS,64 Select_FPR16_Using_CC_GPR,65 Select_FPR16INX_Using_CC_GPR,66 Select_FPR32_Using_CC_GPR,67 Select_FPR32INX_Using_CC_GPR,68 Select_FPR64_Using_CC_GPR,69 Select_FPR64INX_Using_CC_GPR,70 Select_FPR64IN32X_Using_CC_GPR71 ]>>>;72 73// Returns true if this is a vector configuration instruction.74def isVectorConfigInstr75 : TIIPredicate<"isVectorConfigInstr",76 MCReturnStatement<77 CheckOpcode<[78 PseudoVSETVLI,79 PseudoVSETVLIX0,80 PseudoVSETVLIX0X0,81 PseudoVSETIVLI,82 PseudoSF_VSETTNT,83 PseudoSF_VSETTNTX0,84 PseudoSF_VSETTNTX0X085 ]>>>;86 87// Returns true if this is a PseudoSF_VSETTNT* instructions.88def isXSfmmVectorConfigTNInstr89 : TIIPredicate<"isXSfmmVectorConfigTNInstr",90 MCReturnStatement<91 CheckOpcode<[92 PseudoSF_VSETTNT,93 PseudoSF_VSETTNTX0,94 PseudoSF_VSETTNTX0X095 ]>>>;96 97// Returns true if this is PseudoSF_VSETTM or PseudoSF_VSETTK.98def isXSfmmVectorConfigTMTKInstr99 : TIIPredicate<"isXSfmmVectorConfigTMTKInstr",100 MCReturnStatement<101 CheckOpcode<[102 PseudoSF_VSETTM,103 PseudoSF_VSETTK104 ]>>>;105 106// Returns true if this is a XSfmm vector configuration instruction.107def isXSfmmVectorConfigInstr108 : TIIPredicate<"isXSfmmVectorConfigInstr",109 MCReturnStatement<110 CheckOpcode<[111 PseudoSF_VSETTNT,112 PseudoSF_VSETTNTX0,113 PseudoSF_VSETTNTX0X0,114 PseudoSF_VSETTM,115 PseudoSF_VSETTK116 ]>>>;117 118// Return true if this is 'vsetvli x0, x0, vtype' which preserves119// VL and only sets VTYPE.120def isVLPreservingConfig121 : TIIPredicate<"isVLPreservingConfig",122 MCReturnStatement<CheckOpcode<[PseudoVSETVLIX0X0]>>>;123 124def isFloatScalarMoveOrScalarSplatInstr125 : TIIPredicate<"isFloatScalarMoveOrScalarSplatInstr",126 MCReturnStatement<127 CheckOpcode<!listflatten([128 !instances<Pseudo>("^PseudoVFMV_S_F.*"),129 !instances<Pseudo>("^PseudoVFMV_V_F.*")130 ])>>>;131 132def isScalarExtractInstr133 : TIIPredicate<"isScalarExtractInstr",134 MCReturnStatement<135 CheckOpcode<!listflatten([136 !instances<Pseudo>("^PseudoVMV_X_S.*"),137 !instances<Pseudo>("^PseudoVFMV_F.*_S.*")138 ])>>>;139 140def isVExtractInstr141 : TIIPredicate<"isVExtractInstr",142 MCReturnStatement<143 CheckOpcode<144 !instances<Instruction>("^PseudoRI_VEXTRACT.*")>>>;145 146def isScalarInsertInstr147 : TIIPredicate<"isScalarInsertInstr",148 MCReturnStatement<149 CheckOpcode<!listflatten([150 !instances<Pseudo>("^PseudoVMV_S_X.*"),151 !instances<Pseudo>("^PseudoVFMV_S_F.*")152 ])>>>;153 154def isScalarSplatInstr155 : TIIPredicate<"isScalarSplatInstr",156 MCReturnStatement<157 CheckOpcode<!listflatten([158 !instances<Pseudo>("^PseudoVMV_V_I.*"),159 !instances<Pseudo>("^PseudoVMV_V_X.*"),160 !instances<Pseudo>("^PseudoVFMV_V_F.*")161 ])>>>;162 163def isVSlideInstr164 : TIIPredicate<"isVSlideInstr",165 MCReturnStatement<166 CheckOpcode<!listflatten([167 !instances<Pseudo>("^PseudoVSLIDEDOWN_VX.*"),168 !instances<Pseudo>("^PseudoVSLIDEDOWN_VI.*"),169 !instances<Pseudo>("^PseudoVSLIDEUP_VX.*"),170 !instances<Pseudo>("^PseudoVSLIDEUP_VI.*")171 ])>>>;172 173def isFaultOnlyFirstLoad174 : TIIPredicate<"isFaultOnlyFirstLoad",175 MCReturnStatement<176 CheckOpcode<177 !instances<Pseudo>(178 "^PseudoVL(SEG[2-8])?E(8|16|32|64)FF_V.*")>>>;179 180def isNonZeroLoadImmediate181 : TIIPredicate<"isNonZeroLoadImmediate",182 MCReturnStatement<CheckAll<[183 CheckOpcode<[ADDI]>,184 CheckIsRegOperand<1>,185 CheckRegOperand<1, X0>,186 CheckIsImmOperand<2>,187 CheckNot<CheckImmOperand<2, 0>>188 ]>>>;189 190def isLPAD191 : TIIPredicate<"isLPAD",192 MCReturnStatement<CheckAll<[193 CheckOpcode<[AUIPC]>,194 CheckIsRegOperand<0>,195 CheckRegOperand<0, X0>,196 ]>>>;197 198def ignoresVXRM199 : TIIPredicate<"ignoresVXRM",200 MCOpcodeSwitchStatement<201 [MCOpcodeSwitchCase<202 !listflatten([203 !instances<Pseudo>("^PseudoVNCLIP_WI.*"),204 !instances<Pseudo>("^PseudoVNCLIPU_WI.*")205 ]),206 MCReturnStatement<CheckImmOperand<3, 0>>>],207 MCReturnStatement<FalsePred>>>;208