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1//==----- RISCVMacroFusion.td - Macro Fusion Definitions -----*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9// ===---------------------------------------------------------------------===//10// The following definitions describe the macro fusion predicators.11 12// Fuse LUI followed by ADDI or ADDIW:13// rd = imm[31:0] which decomposes to14// lui rd, imm[31:12]15// addi(w) rd, rd, imm[11:0]16def TuneLUIADDIFusion17 : SimpleFusion<"lui-addi-fusion", "HasLUIADDIFusion",18 "Enable LUI+ADDI macro fusion",19 CheckOpcode<[LUI]>,20 CheckOpcode<[ADDI, ADDIW]>>;21 22// Fuse AUIPC followed by ADDI:23// auipc rd, imm2024// addi rd, rd, imm1225def TuneAUIPCADDIFusion26 : SimpleFusion<"auipc-addi-fusion", "HasAUIPCADDIFusion",27 "Enable AUIPC+ADDI macrofusion",28 CheckOpcode<[AUIPC]>,29 CheckOpcode<[ADDI]>>;30 31// Fuse zero extension of halfword:32// slli rd, rs1, 4833// srli rd, rd, 4834def TuneZExtHFusion35 : SimpleFusion<"zexth-fusion", "HasZExtHFusion",36 "Enable SLLI+SRLI to be fused to zero extension of halfword",37 CheckAll<[38 CheckOpcode<[SLLI]>,39 CheckIsImmOperand<2>,40 CheckImmOperand<2, 48>41 ]>,42 CheckAll<[43 CheckOpcode<[SRLI]>,44 CheckIsImmOperand<2>,45 CheckImmOperand<2, 48>46 ]>>;47 48// Fuse zero extension of word:49// slli rd, rs1, 3250// srli rd, rd, 3251def TuneZExtWFusion52 : SimpleFusion<"zextw-fusion", "HasZExtWFusion",53 "Enable SLLI+SRLI to be fused to zero extension of word",54 CheckAll<[55 CheckOpcode<[SLLI]>,56 CheckIsImmOperand<2>,57 CheckImmOperand<2, 32>58 ]>,59 CheckAll<[60 CheckOpcode<[SRLI]>,61 CheckIsImmOperand<2>,62 CheckImmOperand<2, 32>63 ]>>;64 65// Fuse shifted zero extension of word:66// slli rd, rs1, 3267// srli rd, rd, x68// where 0 <= x < 3269def TuneShiftedZExtWFusion70 : SimpleFusion<"shifted-zextw-fusion", "HasShiftedZExtWFusion",71 "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",72 CheckAll<[73 CheckOpcode<[SLLI]>,74 CheckIsImmOperand<2>,75 CheckImmOperand<2, 32>76 ]>,77 CheckAll<[78 CheckOpcode<[SRLI]>,79 CheckIsImmOperand<2>,80 CheckImmOperandRange<2, 0, 31>81 ]>>;82 83// Fuse load with add:84// add rd, rs1, rs285// ld rd, 0(rd)86def TuneLDADDFusion87 : SimpleFusion<"ld-add-fusion", "HasLDADDFusion", "Enable LD+ADD macrofusion",88 CheckOpcode<[ADD]>,89 CheckAll<[90 CheckOpcode<[LD]>,91 CheckIsImmOperand<2>,92 CheckImmOperand<2, 0>93 ]>>;94 95defvar Load = [LB, LH, LW, LD, LBU, LHU, LWU];96 97// Fuse add(.uw) followed by a load (lb, lh, lw, ld, lbu, lhu, lwu):98// add(.uw) rd, rs1, rs299// load rd, imm12(rd)100def TuneADDLoadFusion101 : SimpleFusion<"add-load-fusion", "HasADDLoadFusion", "Enable ADD(.UW) + load macrofusion",102 CheckOpcode<[ADD, ADD_UW]>,103 CheckOpcode<Load>>;104 105// Fuse AUIPC followed by by a load (lb, lh, lw, ld, lbu, lhu, lwu)106// auipc rd, imm20107// load rd, imm12(rd)108def TuneAUIPCLoadFusion109 : SimpleFusion<"auipc-load-fusion", "HasAUIPCLoadFusion",110 "Enable AUIPC + load macrofusion",111 CheckOpcode<[AUIPC]>,112 CheckOpcode<Load>>;113 114// Fuse LUI followed by a load (lb, lh, lw, ld, lbu, lhu, lwu)115// lui rd, imm[31:12]116// load rd, imm12(rd)117def TuneLUILoadFusion118 : SimpleFusion<"lui-load-fusion", "HasLUILoadFusion",119 "Enable LUI + load macrofusion",120 CheckOpcode<[LUI]>,121 CheckOpcode<Load>>;122 123// Bitfield extract fusion: similar to TuneShiftedZExtWFusion124// but without the immediate restriction125// slli rd, rs1, imm12126// srli rd, rd, imm12127def TuneBFExtFusion128 : SimpleFusion<"bfext-fusion", "HasBFExtFusion",129 "Enable SLLI+SRLI (bitfield extract) macrofusion",130 CheckOpcode<[SLLI]>,131 CheckOpcode<[SRLI]>>;132 133// Fuse ADDI followed by a load (lb, lh, lw, ld, lbu, lhu, lwu)134// addi rd, rs1, imm12135// load rd, imm12(rd)136def TuneADDILoadFusion137 : SimpleFusion<"addi-load-fusion", "HasADDILoadFusion",138 "Enable ADDI + load macrofusion",139 CheckOpcode<[ADDI]>,140 CheckOpcode<Load>>;141 142// Fuse shXadd(.uw) followed by a load (lb, lh, lw, ld, lbu, lhu, lwu)143// shXadd(.uw) rd, rs1, rs2144// load rd, imm12(rd)145def TuneSHXADDLoadFusion146 : SimpleFusion<"shxadd-load-fusion", "HasSHXADDLoadFusion",147 "Enable SH(1|2|3)ADD(.UW) + load macrofusion",148 CheckOpcode<[SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW]>,149 CheckOpcode<Load>>;150