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1//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// RISC-V processors supported.11//===----------------------------------------------------------------------===//12 13// Predefined scheduling direction.14defvar TopDown = [{ MISched::TopDown }];15defvar BottomUp = [{ MISched::BottomUp }];16defvar Bidirectional = [{ MISched::Bidirectional }];17 18class RISCVTuneInfo {19 bits<8> PrefFunctionAlignment = 1;20 bits<8> PrefLoopAlignment = 1;21 22 // Information needed by LoopDataPrefetch.23 bits<16> CacheLineSize = 0;24 bits<16> PrefetchDistance = 0;25 bits<16> MinPrefetchStride = 1;26 bits<32> MaxPrefetchIterationsAhead = -1;27 28 bits<32> MinimumJumpTableEntries = 5;29 30 // Tail duplication threshold at -O3.31 bits<32> TailDupAggressiveThreshold = 6;32 33 bits<32> MaxStoresPerMemsetOptSize = 4;34 bits<32> MaxStoresPerMemset = 8;35 36 bits<32> MaxGluedStoresPerMemcpy = 0;37 bits<32> MaxStoresPerMemcpyOptSize = 4;38 bits<32> MaxStoresPerMemcpy = 8;39 40 bits<32> MaxStoresPerMemmoveOptSize = 4;41 bits<32> MaxStoresPerMemmove = 8;42 43 bits<32> MaxLoadsPerMemcmpOptSize = 4;44 bits<32> MaxLoadsPerMemcmp = 8;45 46 // The direction of PostRA scheduling.47 code PostRASchedDirection = TopDown;48}49 50def RISCVTuneInfoTable : GenericTable {51 let FilterClass = "RISCVTuneInfo";52 let CppTypeName = "RISCVTuneInfo";53 let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",54 "CacheLineSize", "PrefetchDistance", "MinPrefetchStride",55 "MaxPrefetchIterationsAhead", "MinimumJumpTableEntries",56 "TailDupAggressiveThreshold", "MaxStoresPerMemsetOptSize",57 "MaxStoresPerMemset", "MaxGluedStoresPerMemcpy",58 "MaxStoresPerMemcpyOptSize", "MaxStoresPerMemcpy",59 "MaxStoresPerMemmoveOptSize", "MaxStoresPerMemmove",60 "MaxLoadsPerMemcmpOptSize", "MaxLoadsPerMemcmp",61 "PostRASchedDirection"];62}63 64def getRISCVTuneInfo : SearchIndex {65 let Table = RISCVTuneInfoTable;66 let Key = ["Name"];67}68 69class GenericTuneInfo: RISCVTuneInfo;70 71class RISCVProcessorModel<string n,72 SchedMachineModel m,73 list<SubtargetFeature> f,74 list<SubtargetFeature> tunef = [],75 string default_march = "">76 : ProcessorModel<n, m, f, tunef> {77 string DefaultMarch = default_march;78 int MVendorID = 0;79 int MArchID = 0;80 int MImpID = 0;81}82 83class RISCVTuneProcessorModel<string n,84 SchedMachineModel m,85 list<SubtargetFeature> tunef = [],86 list<SubtargetFeature> f = []>87 : ProcessorModel<n, m, f,tunef>;88 89defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];90 91def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",92 NoSchedModel,93 [Feature32Bit,94 FeatureStdExtI],95 GenericTuneFeatures>,96 GenericTuneInfo;97def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",98 NoSchedModel,99 [Feature64Bit,100 FeatureStdExtI],101 GenericTuneFeatures>,102 GenericTuneInfo;103// Support generic for compatibility with other targets. The triple will be used104// to change to the appropriate rv32/rv64 version.105def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;106def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,107 GenericTuneInfo;108 109def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",110 MIPSP8700Model,111 [Feature64Bit,112 FeatureStdExtI,113 FeatureStdExtM,114 FeatureStdExtA,115 FeatureStdExtF,116 FeatureStdExtD,117 FeatureStdExtC,118 FeatureStdExtZba,119 FeatureStdExtZbb,120 FeatureStdExtZifencei,121 FeatureStdExtZicsr,122 FeatureVendorXMIPSCMov,123 FeatureVendorXMIPSLSP,124 FeatureVendorXMIPSCBOP,125 FeatureVendorXMIPSEXECTL],126 [TuneMIPSP8700]>;127 128def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",129 RocketModel,130 [Feature32Bit,131 FeatureStdExtI,132 FeatureStdExtZifencei,133 FeatureStdExtZicsr]>;134def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",135 RocketModel,136 [Feature64Bit,137 FeatureStdExtI,138 FeatureStdExtZifencei,139 FeatureStdExtZicsr]>;140def ROCKET : RISCVTuneProcessorModel<"rocket",141 RocketModel>;142 143defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll,144 TuneShortForwardBranchIALU,145 TunePostRAScheduler];146def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",147 SiFive7Model, SiFive7TuneFeatures>;148 149def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",150 RocketModel,151 [Feature32Bit,152 FeatureStdExtI,153 FeatureStdExtZicsr,154 FeatureStdExtZifencei,155 FeatureStdExtM,156 FeatureStdExtC]>;157 158def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",159 RocketModel,160 [Feature32Bit,161 FeatureStdExtI,162 FeatureStdExtZicsr,163 FeatureStdExtZifencei,164 FeatureStdExtM,165 FeatureStdExtA,166 FeatureStdExtC]>;167 168def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",169 RocketModel,170 [Feature32Bit,171 FeatureStdExtI,172 FeatureStdExtZifencei,173 FeatureStdExtM,174 FeatureStdExtA,175 FeatureStdExtF,176 FeatureStdExtC]>;177 178def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",179 RocketModel,180 [Feature32Bit,181 FeatureStdExtI,182 FeatureStdExtZifencei,183 FeatureStdExtZicsr,184 FeatureStdExtM,185 FeatureStdExtA,186 FeatureStdExtC]>;187 188def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",189 RocketModel,190 [Feature32Bit,191 FeatureStdExtI,192 FeatureStdExtZifencei,193 FeatureStdExtM,194 FeatureStdExtA,195 FeatureStdExtF,196 FeatureStdExtC]>;197 198def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",199 SiFive7Model,200 [Feature32Bit,201 FeatureStdExtI,202 FeatureStdExtZifencei,203 FeatureStdExtM,204 FeatureStdExtA,205 FeatureStdExtF,206 FeatureStdExtC],207 SiFive7TuneFeatures>;208 209def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",210 RocketModel,211 [Feature64Bit,212 FeatureStdExtI,213 FeatureStdExtZicsr,214 FeatureStdExtZifencei,215 FeatureStdExtM,216 FeatureStdExtA,217 FeatureStdExtC]>;218 219def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",220 RocketModel,221 [Feature64Bit,222 FeatureStdExtI,223 FeatureStdExtZicsr,224 FeatureStdExtZifencei,225 FeatureStdExtM,226 FeatureStdExtA,227 FeatureStdExtC]>;228 229def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",230 RocketModel,231 [Feature64Bit,232 FeatureStdExtI,233 FeatureStdExtZifencei,234 FeatureStdExtM,235 FeatureStdExtA,236 FeatureStdExtF,237 FeatureStdExtD,238 FeatureStdExtC]>;239 240def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",241 SiFive7Model,242 [Feature64Bit,243 FeatureStdExtI,244 FeatureStdExtZifencei,245 FeatureStdExtM,246 FeatureStdExtA,247 FeatureStdExtF,248 FeatureStdExtD,249 FeatureStdExtC,250 FeatureStdExtZihintpause],251 SiFive7TuneFeatures>;252 253def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",254 RocketModel,255 [Feature64Bit,256 FeatureStdExtI,257 FeatureStdExtZifencei,258 FeatureStdExtM,259 FeatureStdExtA,260 FeatureStdExtF,261 FeatureStdExtD,262 FeatureStdExtC]>;263 264def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",265 SiFive7Model,266 [Feature64Bit,267 FeatureStdExtI,268 FeatureStdExtZifencei,269 FeatureStdExtM,270 FeatureStdExtA,271 FeatureStdExtF,272 FeatureStdExtD,273 FeatureStdExtC],274 SiFive7TuneFeatures>;275 276defvar SiFiveIntelligenceTuneFeatures = !listconcat(SiFive7TuneFeatures,277 [TuneDLenFactor2,278 TuneOptimizedZeroStrideLoad,279 TuneOptimizedNF2SegmentLoadStore,280 TuneVLDependentLatency]);281def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,282 [Feature64Bit,283 FeatureStdExtI,284 FeatureStdExtZifencei,285 FeatureStdExtM,286 FeatureStdExtA,287 FeatureStdExtF,288 FeatureStdExtD,289 FeatureStdExtC,290 FeatureStdExtV,291 FeatureStdExtZvl512b,292 FeatureStdExtZfh,293 FeatureStdExtZvfh,294 FeatureStdExtZba,295 FeatureStdExtZbb],296 SiFiveIntelligenceTuneFeatures>;297 298def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390",299 SiFiveX390Model,300 [Feature64Bit,301 FeatureStdExtI,302 FeatureStdExtM,303 FeatureStdExtA,304 FeatureStdExtF,305 FeatureStdExtD,306 FeatureStdExtC,307 FeatureStdExtB,308 FeatureStdExtV,309 FeatureStdExtZic64b,310 FeatureStdExtZicbom,311 FeatureStdExtZicbop,312 FeatureStdExtZicboz,313 FeatureStdExtZiccamoa,314 FeatureStdExtZiccif,315 FeatureStdExtZiccrse,316 FeatureStdExtZicfilp,317 FeatureStdExtZicfiss,318 FeatureStdExtZicntr,319 FeatureStdExtZicond,320 FeatureStdExtZifencei,321 FeatureStdExtZihintntl,322 FeatureStdExtZihintpause,323 FeatureStdExtZihpm,324 FeatureStdExtZimop,325 FeatureStdExtZa64rs,326 FeatureStdExtZawrs,327 FeatureStdExtZfa,328 FeatureStdExtZfh,329 FeatureStdExtZcb,330 FeatureStdExtZcmop,331 FeatureStdExtZkr,332 FeatureStdExtZkt,333 FeatureStdExtZvbb,334 FeatureStdExtZvfbfmin,335 FeatureStdExtZvfbfwma,336 FeatureStdExtZvfh,337 FeatureStdExtZvkt,338 FeatureStdExtZvl1024b,339 FeatureVendorXSiFivecdiscarddlone,340 FeatureVendorXSiFivecflushdlone],341 !listconcat(SiFiveIntelligenceTuneFeatures,342 [TuneHasSingleElementVecFP64])>;343 344defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,345 TuneConditionalCompressedMoveFusion,346 TuneLUIADDIFusion,347 TuneAUIPCADDIFusion,348 TunePostRAScheduler];349 350def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,351 [Feature64Bit,352 FeatureStdExtI,353 FeatureStdExtM,354 FeatureStdExtA,355 FeatureStdExtF,356 FeatureStdExtD,357 FeatureStdExtC,358 FeatureStdExtZicsr,359 FeatureStdExtZiccif,360 FeatureStdExtZiccrse,361 FeatureStdExtZiccamoa,362 FeatureStdExtZicclsm,363 FeatureStdExtZa64rs,364 FeatureStdExtZihpm,365 FeatureStdExtZihintpause,366 FeatureStdExtB,367 FeatureStdExtZic64b,368 FeatureStdExtZicbom,369 FeatureStdExtZicbop,370 FeatureStdExtZicboz,371 FeatureStdExtZfhmin,372 FeatureStdExtZkt,373 FeatureStdExtZifencei,374 FeatureStdExtZihintntl,375 FeatureUnalignedScalarMem,376 FeatureUnalignedVectorMem],377 SiFiveP400TuneFeatures>;378 379def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,380 [Feature64Bit,381 FeatureStdExtI,382 FeatureStdExtM,383 FeatureStdExtA,384 FeatureStdExtF,385 FeatureStdExtD,386 FeatureStdExtC,387 FeatureStdExtZicsr,388 FeatureStdExtZiccif,389 FeatureStdExtZiccrse,390 FeatureStdExtZiccamoa,391 FeatureStdExtZicclsm,392 FeatureStdExtZa64rs,393 FeatureStdExtZihpm,394 FeatureStdExtZihintpause,395 FeatureStdExtB,396 FeatureStdExtZic64b,397 FeatureStdExtZicbom,398 FeatureStdExtZicbop,399 FeatureStdExtZicboz,400 FeatureStdExtZfhmin,401 FeatureStdExtZkt,402 FeatureStdExtV,403 FeatureStdExtZifencei,404 FeatureStdExtZihintntl,405 FeatureStdExtZvl128b,406 FeatureStdExtZvbb,407 FeatureStdExtZvknc,408 FeatureStdExtZvkng,409 FeatureStdExtZvksc,410 FeatureStdExtZvksg,411 FeatureVendorXSiFivecdiscarddlone,412 FeatureVendorXSiFivecflushdlone,413 FeatureUnalignedScalarMem,414 FeatureUnalignedVectorMem],415 !listconcat(SiFiveP400TuneFeatures,416 [TuneNoSinkSplatOperands,417 TuneVXRMPipelineFlush])>;418 419defvar SiFiveP500TuneFeatures = [TuneNoDefaultUnroll,420 TuneConditionalCompressedMoveFusion,421 TuneLUIADDIFusion,422 TuneAUIPCADDIFusion,423 TunePostRAScheduler];424 425def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model,426 [Feature64Bit,427 FeatureStdExtI,428 FeatureStdExtZifencei,429 FeatureStdExtM,430 FeatureStdExtA,431 FeatureStdExtF,432 FeatureStdExtD,433 FeatureStdExtC,434 FeatureStdExtZba,435 FeatureStdExtZbb],436 SiFiveP500TuneFeatures> {437 let MVendorID = 0x489;438 let MArchID = 0x8000000000000008;439 let MImpID = 0x6220425;440}441 442def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,443 [Feature64Bit,444 FeatureStdExtI,445 FeatureStdExtM,446 FeatureStdExtA,447 FeatureStdExtF,448 FeatureStdExtD,449 FeatureStdExtC,450 FeatureStdExtZicsr,451 FeatureStdExtZiccif,452 FeatureStdExtZiccrse,453 FeatureStdExtZiccamoa,454 FeatureStdExtZicclsm,455 FeatureStdExtZa64rs,456 FeatureStdExtZihpm,457 FeatureStdExtZihintpause,458 FeatureStdExtB,459 FeatureStdExtZic64b,460 FeatureStdExtZicbom,461 FeatureStdExtZicbop,462 FeatureStdExtZicboz,463 FeatureStdExtZfhmin,464 FeatureStdExtZkt,465 FeatureStdExtV,466 FeatureStdExtZifencei,467 FeatureStdExtZihintntl,468 FeatureStdExtZvl128b,469 FeatureStdExtZvbb,470 FeatureStdExtZvknc,471 FeatureStdExtZvkng,472 FeatureStdExtZvksc,473 FeatureStdExtZvksg,474 FeatureUnalignedScalarMem,475 FeatureUnalignedVectorMem],476 [TuneNoDefaultUnroll,477 TuneConditionalCompressedMoveFusion,478 TuneLUIADDIFusion,479 TuneAUIPCADDIFusion,480 TuneNoSinkSplatOperands,481 TuneVXRMPipelineFlush,482 TunePostRAScheduler]>;483 484def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", SiFiveP800Model,485 !listconcat(RVA23U64Features,486 [FeatureStdExtZama16b,487 FeatureStdExtZfh,488 FeatureStdExtZifencei,489 FeatureStdExtZkr,490 FeatureStdExtZvfbfmin,491 FeatureStdExtZvfbfwma,492 FeatureStdExtZvfh,493 FeatureStdExtZvknc,494 FeatureStdExtZvkng,495 FeatureStdExtZvksc,496 FeatureStdExtZvksg,497 FeatureStdExtZvl128b,498 FeatureUnalignedScalarMem,499 FeatureUnalignedVectorMem]),500 [TuneNoDefaultUnroll,501 TuneConditionalCompressedMoveFusion,502 TuneLUIADDIFusion,503 TuneAUIPCADDIFusion,504 TuneNoSinkSplatOperands,505 TuneVXRMPipelineFlush,506 TunePostRAScheduler]>;507 508def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",509 SyntacoreSCR1Model,510 [Feature32Bit,511 FeatureStdExtI,512 FeatureStdExtZicsr,513 FeatureStdExtZifencei,514 FeatureStdExtC],515 [TuneNoDefaultUnroll]>;516 517def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",518 SyntacoreSCR1Model,519 [Feature32Bit,520 FeatureStdExtI,521 FeatureStdExtZicsr,522 FeatureStdExtZifencei,523 FeatureStdExtM,524 FeatureStdExtC],525 [TuneNoDefaultUnroll]>;526 527def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",528 SyntacoreSCR3RV32Model,529 [Feature32Bit,530 FeatureStdExtI,531 FeatureStdExtZicsr,532 FeatureStdExtZifencei,533 FeatureStdExtM,534 FeatureStdExtC],535 [TuneNoDefaultUnroll, TunePostRAScheduler]>;536 537def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",538 SyntacoreSCR3RV64Model,539 [Feature64Bit,540 FeatureStdExtI,541 FeatureStdExtZicsr,542 FeatureStdExtZifencei,543 FeatureStdExtM,544 FeatureStdExtA,545 FeatureStdExtC],546 [TuneNoDefaultUnroll, TunePostRAScheduler]>;547 548def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",549 SyntacoreSCR4RV32Model,550 [Feature32Bit,551 FeatureStdExtI,552 FeatureStdExtZicsr,553 FeatureStdExtZifencei,554 FeatureStdExtM,555 FeatureStdExtF,556 FeatureStdExtD,557 FeatureStdExtC],558 [TuneNoDefaultUnroll, TunePostRAScheduler]>;559 560def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",561 SyntacoreSCR4RV64Model,562 [Feature64Bit,563 FeatureStdExtI,564 FeatureStdExtZicsr,565 FeatureStdExtZifencei,566 FeatureStdExtM,567 FeatureStdExtA,568 FeatureStdExtF,569 FeatureStdExtD,570 FeatureStdExtC],571 [TuneNoDefaultUnroll, TunePostRAScheduler]>;572 573def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",574 SyntacoreSCR5RV32Model,575 [Feature32Bit,576 FeatureStdExtI,577 FeatureStdExtZicsr,578 FeatureStdExtZifencei,579 FeatureStdExtM,580 FeatureStdExtA,581 FeatureStdExtF,582 FeatureStdExtD,583 FeatureStdExtC],584 [TuneNoDefaultUnroll, TunePostRAScheduler]>;585 586def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",587 SyntacoreSCR5RV64Model,588 [Feature64Bit,589 FeatureStdExtI,590 FeatureStdExtZicsr,591 FeatureStdExtZifencei,592 FeatureStdExtM,593 FeatureStdExtA,594 FeatureStdExtF,595 FeatureStdExtD,596 FeatureStdExtC],597 [TuneNoDefaultUnroll, TunePostRAScheduler]>;598 599def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",600 SyntacoreSCR7Model,601 [Feature64Bit,602 FeatureStdExtI,603 FeatureStdExtZicsr,604 FeatureStdExtZifencei,605 FeatureStdExtM,606 FeatureStdExtA,607 FeatureStdExtF,608 FeatureStdExtD,609 FeatureStdExtC,610 FeatureStdExtV,611 FeatureStdExtZba,612 FeatureStdExtZbb,613 FeatureStdExtZbc,614 FeatureStdExtZbs,615 FeatureStdExtZkn],616 [TuneNoDefaultUnroll, TunePostRAScheduler]>;617 618def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",619 TTAscalonD8Model,620 !listconcat(RVA23S64Features,621 [FeatureStdExtSmaia,622 FeatureStdExtSsaia,623 FeatureStdExtSsstrict,624 FeatureStdExtZfbfmin,625 FeatureStdExtZfh,626 FeatureStdExtZvbc,627 FeatureStdExtZvfbfmin,628 FeatureStdExtZvfbfwma,629 FeatureStdExtZvfh,630 FeatureStdExtZvkng,631 FeatureStdExtZvl256b,632 FeatureUnalignedScalarMem,633 FeatureUnalignedVectorMem]),634 [TuneNoDefaultUnroll,635 TuneNLogNVRGather,636 TuneOptimizedNF2SegmentLoadStore,637 TuneOptimizedNF3SegmentLoadStore,638 TuneOptimizedNF4SegmentLoadStore,639 TuneOptimizedNF5SegmentLoadStore,640 TuneOptimizedNF6SegmentLoadStore,641 TuneOptimizedNF7SegmentLoadStore,642 TuneOptimizedNF8SegmentLoadStore,643 TuneOptimizedZeroStrideLoad,644 TunePostRAScheduler]>;645 646def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",647 NoSchedModel,648 [Feature64Bit,649 FeatureStdExtI,650 FeatureStdExtZifencei,651 FeatureStdExtZicsr,652 FeatureStdExtZicntr,653 FeatureStdExtZihpm,654 FeatureStdExtZihintpause,655 FeatureStdExtM,656 FeatureStdExtA,657 FeatureStdExtF,658 FeatureStdExtD,659 FeatureStdExtC,660 FeatureStdExtZba,661 FeatureStdExtZbb,662 FeatureStdExtZbc,663 FeatureStdExtZbs,664 FeatureStdExtZicbom,665 FeatureStdExtZicbop,666 FeatureStdExtZicboz,667 FeatureVendorXVentanaCondOps],668 [TuneVentanaVeyron,669 TuneDisableMISchedLoadClustering,670 TuneDisablePostMISchedLoadClustering,671 TuneDisablePostMISchedStoreClustering,672 TuneLUIADDIFusion,673 TuneAUIPCADDIFusion,674 TuneZExtHFusion,675 TuneZExtWFusion,676 TuneShiftedZExtWFusion,677 TuneADDLoadFusion,678 TuneAUIPCLoadFusion,679 TuneLUILoadFusion]> {680 let MVendorID = 0x61f;681 let MArchID = 0x8000000000010000;682 let MImpID = 0x111;683}684 685def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",686 XiangShanNanHuModel,687 [Feature64Bit,688 FeatureStdExtI,689 FeatureStdExtZicsr,690 FeatureStdExtZifencei,691 FeatureStdExtM,692 FeatureStdExtA,693 FeatureStdExtF,694 FeatureStdExtD,695 FeatureStdExtC,696 FeatureStdExtZba,697 FeatureStdExtZbb,698 FeatureStdExtZbc,699 FeatureStdExtZbs,700 FeatureStdExtZkn,701 FeatureStdExtZksed,702 FeatureStdExtZksh,703 FeatureStdExtSvinval,704 FeatureStdExtZicbom,705 FeatureStdExtZicboz],706 [TuneNoDefaultUnroll,707 TuneZExtHFusion,708 TuneZExtWFusion,709 TuneShiftedZExtWFusion]>;710 711def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",712 NoSchedModel,713 !listconcat(RVA23S64Features,714 [FeatureStdExtZacas,715 FeatureStdExtZbc,716 FeatureStdExtZfh,717 FeatureStdExtZkn,718 FeatureStdExtZks,719 FeatureStdExtZvfh,720 FeatureStdExtSmaia,721 FeatureStdExtSmcsrind,722 FeatureStdExtSmdbltrp,723 FeatureStdExtSmmpm,724 FeatureStdExtSmnpm,725 FeatureStdExtSmrnmi,726 FeatureStdExtSmstateen,727 FeatureStdExtSsaia,728 FeatureStdExtSscsrind,729 FeatureStdExtSsdbltrp,730 FeatureStdExtSspm,731 FeatureStdExtSsstrict,732 FeatureStdExtZvl128b]),733 [TuneNoDefaultUnroll,734 TuneZExtHFusion,735 TuneZExtWFusion,736 TuneShiftedZExtWFusion]>;737 738def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",739 SpacemitX60Model,740 !listconcat(RVA22S64Features,741 [FeatureStdExtV,742 FeatureStdExtSscofpmf,743 FeatureStdExtSstc,744 FeatureStdExtSvnapot,745 FeatureStdExtZbc,746 FeatureStdExtZbkc,747 FeatureStdExtZfh,748 FeatureStdExtZicond,749 FeatureStdExtZvfh,750 FeatureStdExtZvkt,751 FeatureStdExtZvl256b,752 FeatureVendorXSMTVDot,753 FeatureUnalignedScalarMem]),754 [TuneDLenFactor2,755 TuneOptimizedNF2SegmentLoadStore,756 TuneOptimizedNF3SegmentLoadStore,757 TuneOptimizedNF4SegmentLoadStore,758 TuneVXRMPipelineFlush]> {759 let MVendorID = 0x710;760 let MArchID = 0x8000000058000001;761 let MImpID = 0x1000000049772200;762}763 764def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",765 NoSchedModel,766 [Feature32Bit,767 FeatureStdExtI,768 FeatureStdExtM,769 FeatureStdExtA,770 FeatureStdExtC,771 FeatureStdExtZicsr,772 FeatureStdExtZifencei,773 FeatureStdExtZba,774 FeatureStdExtZbb,775 FeatureStdExtZbs,776 FeatureStdExtZbkb,777 FeatureStdExtZcb,778 FeatureStdExtZcmp]>;779 780def ANDES_A25 : RISCVProcessorModel<"andes-a25",781 NoSchedModel,782 [Feature32Bit,783 FeatureStdExtI,784 FeatureStdExtZicsr,785 FeatureStdExtZifencei,786 FeatureStdExtM,787 FeatureStdExtA,788 FeatureStdExtF,789 FeatureStdExtD,790 FeatureStdExtC,791 FeatureVendorXAndesPerf]>;792 793def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",794 NoSchedModel,795 [Feature64Bit,796 FeatureStdExtI,797 FeatureStdExtZicsr,798 FeatureStdExtZifencei,799 FeatureStdExtM,800 FeatureStdExtA,801 FeatureStdExtF,802 FeatureStdExtD,803 FeatureStdExtC,804 FeatureVendorXAndesPerf]>;805 806defvar Andes45TuneFeatures = [TuneAndes45,807 TuneNoDefaultUnroll,808 TuneShortForwardBranchIALU,809 TunePostRAScheduler];810 811def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",812 Andes45Model, Andes45TuneFeatures>;813 814def ANDES_N45 : RISCVProcessorModel<"andes-n45",815 Andes45Model,816 [Feature32Bit,817 FeatureStdExtI,818 FeatureStdExtZicsr,819 FeatureStdExtZifencei,820 FeatureStdExtM,821 FeatureStdExtA,822 FeatureStdExtF,823 FeatureStdExtD,824 FeatureStdExtC,825 FeatureVendorXAndesPerf],826 Andes45TuneFeatures>;827 828def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",829 Andes45Model,830 [Feature64Bit,831 FeatureStdExtI,832 FeatureStdExtZicsr,833 FeatureStdExtZifencei,834 FeatureStdExtM,835 FeatureStdExtA,836 FeatureStdExtF,837 FeatureStdExtD,838 FeatureStdExtC,839 FeatureVendorXAndesPerf],840 Andes45TuneFeatures>;841 842def ANDES_A45 : RISCVProcessorModel<"andes-a45",843 Andes45Model,844 [Feature32Bit,845 FeatureStdExtI,846 FeatureStdExtZicsr,847 FeatureStdExtZifencei,848 FeatureStdExtM,849 FeatureStdExtA,850 FeatureStdExtF,851 FeatureStdExtD,852 FeatureStdExtC,853 FeatureVendorXAndesPerf],854 Andes45TuneFeatures>;855 856def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",857 Andes45Model,858 [Feature64Bit,859 FeatureStdExtI,860 FeatureStdExtZicsr,861 FeatureStdExtZifencei,862 FeatureStdExtM,863 FeatureStdExtA,864 FeatureStdExtF,865 FeatureStdExtD,866 FeatureStdExtC,867 FeatureVendorXAndesPerf],868 Andes45TuneFeatures>;869 870def ANDES_AX45MPV : RISCVProcessorModel<"andes-ax45mpv",871 Andes45Model,872 [Feature64Bit,873 FeatureStdExtI,874 FeatureStdExtZicsr,875 FeatureStdExtZifencei,876 FeatureStdExtM,877 FeatureStdExtA,878 FeatureStdExtF,879 FeatureStdExtD,880 FeatureStdExtC,881 FeatureStdExtV,882 FeatureVendorXAndesPerf],883 Andes45TuneFeatures>;884