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1//==- RISCVSchedAndes45.td - Andes45 Scheduling Definitions --*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10 11// FIXME: Implement sheduling model for V and other extensions.12def Andes45Model : SchedMachineModel {13 let MicroOpBufferSize = 0; // Andes45 is in-order processor14 let IssueWidth = 2; // 2 micro-ops dispatched per cycle15 let LoadLatency = 2;16 let MispredictPenalty = 5;17 let CompleteModel = 0;18}19 20let SchedModel = Andes45Model in {21 22//===----------------------------------------------------------------------===//23// Define each kind of processor resource and number available.24 25//===----------------------------------------------------------------------===//26// Andes 45 series CPU27// - 2 Integer Arithmetic and Logical Units (ALU)28// - Multiply / Divide Unit (MDU)29// - Load Store Unit (LSU)30// - Control and Status Register Unit (CSR)31// - Floating Point Multiply-Accumulate Unit (FMAC)32// - Floating Point Divide / SQRT Unit (FDIV)33// - Floating Point Move Unit (FMV)34// - Floating Point Misc Unit (FMISC)35//===----------------------------------------------------------------------===//36 37let BufferSize = 0 in {38def Andes45ALU : ProcResource<2>;39def Andes45MDU : ProcResource<1>;40def Andes45LSU : ProcResource<1>;41def Andes45CSR : ProcResource<1>;42 43def Andes45FMAC : ProcResource<1>;44def Andes45FDIV : ProcResource<1>;45def Andes45FMV : ProcResource<1>;46def Andes45FMISC : ProcResource<1>;47}48 49// Integer arithmetic and logic50def : WriteRes<WriteIALU, [Andes45ALU]>;51def : WriteRes<WriteIALU32, [Andes45ALU]>;52def : WriteRes<WriteShiftImm, [Andes45ALU]>;53def : WriteRes<WriteShiftImm32, [Andes45ALU]>;54def : WriteRes<WriteShiftReg, [Andes45ALU]>;55def : WriteRes<WriteShiftReg32, [Andes45ALU]>;56 57// Short forward branch58def : WriteRes<WriteSFB, [Andes45ALU]> {59 let Latency = 1;60 let NumMicroOps = 2;61}62 63// Branching64def : WriteRes<WriteJmp, [Andes45ALU]>;65def : WriteRes<WriteJal, [Andes45ALU]>;66def : WriteRes<WriteJalr, [Andes45ALU]>;67 68// Integer multiplication69let Latency = 3 in {70def : WriteRes<WriteIMul, [Andes45MDU]>;71def : WriteRes<WriteIMul32, [Andes45MDU]>;72}73 74// Integer division75let Latency = 39, ReleaseAtCycles = [39] in {76def : WriteRes<WriteIDiv, [Andes45MDU]>;77def : WriteRes<WriteIDiv32, [Andes45MDU]>;78}79 80// Integer remainder81let Latency = 39, ReleaseAtCycles = [39] in {82def : WriteRes<WriteIRem, [Andes45MDU]>;83def : WriteRes<WriteIRem32, [Andes45MDU]>;84}85 86// Memory87let Latency = 5 in {88def : WriteRes<WriteLDB, [Andes45LSU]>;89def : WriteRes<WriteLDH, [Andes45LSU]>;90def : WriteRes<WriteFLD16, [Andes45LSU]>;91}92 93let Latency = 3 in {94def : WriteRes<WriteLDW, [Andes45LSU]>;95def : WriteRes<WriteLDD, [Andes45LSU]>;96def : WriteRes<WriteFLD32, [Andes45LSU]>;97def : WriteRes<WriteFLD64, [Andes45LSU]>;98}99 100let Latency = 1 in {101def : WriteRes<WriteSTB, [Andes45LSU]>;102def : WriteRes<WriteSTH, [Andes45LSU]>;103def : WriteRes<WriteSTW, [Andes45LSU]>;104def : WriteRes<WriteSTD, [Andes45LSU]>;105def : WriteRes<WriteFST16, [Andes45LSU]>;106def : WriteRes<WriteFST32, [Andes45LSU]>;107def : WriteRes<WriteFST64, [Andes45LSU]>;108}109 110// Atomic Memory111let Latency = 9 in {112def : WriteRes<WriteAtomicW, [Andes45LSU]>;113def : WriteRes<WriteAtomicD, [Andes45LSU]>;114def : WriteRes<WriteAtomicLDW, [Andes45LSU]>;115def : WriteRes<WriteAtomicLDD, [Andes45LSU]>;116}117 118let Latency = 3 in {119def : WriteRes<WriteAtomicSTW, [Andes45LSU]>;120def : WriteRes<WriteAtomicSTD, [Andes45LSU]>;121}122 123// FMAC124let Latency = 4 in {125def : WriteRes<WriteFAdd16, [Andes45FMAC]>;126def : WriteRes<WriteFAdd32, [Andes45FMAC]>;127def : WriteRes<WriteFAdd64, [Andes45FMAC]>;128def : WriteRes<WriteFMul16, [Andes45FMAC]>;129def : WriteRes<WriteFMul32, [Andes45FMAC]>;130def : WriteRes<WriteFMul64, [Andes45FMAC]>;131def : WriteRes<WriteFMA16, [Andes45FMAC]>;132def : WriteRes<WriteFMA32, [Andes45FMAC]>;133def : WriteRes<WriteFMA64, [Andes45FMAC]>;134}135 136// FDIV137let Latency = 12, ReleaseAtCycles = [12] in138def : WriteRes<WriteFDiv16, [Andes45FDIV]>;139let Latency = 11, ReleaseAtCycles = [11] in140def : WriteRes<WriteFSqrt16, [Andes45FDIV]>;141 142let Latency = 19, ReleaseAtCycles = [19] in143def : WriteRes<WriteFDiv32, [Andes45FDIV]>;144let Latency = 18, ReleaseAtCycles = [18] in145def : WriteRes<WriteFSqrt32, [Andes45FDIV]>;146 147let Latency = 33, ReleaseAtCycles = [33] in148def : WriteRes<WriteFDiv64, [Andes45FDIV]>;149let Latency = 32, ReleaseAtCycles = [32] in150def : WriteRes<WriteFSqrt64, [Andes45FDIV]>;151 152// FMV153def : WriteRes<WriteFSGNJ16, [Andes45FMV]>;154def : WriteRes<WriteFSGNJ32, [Andes45FMV]>;155def : WriteRes<WriteFSGNJ64, [Andes45FMV]>;156def : WriteRes<WriteFMovF16ToI16, [Andes45FMV]>;157def : WriteRes<WriteFMovI16ToF16, [Andes45FMV]>;158def : WriteRes<WriteFMovF32ToI32, [Andes45FMV]>;159def : WriteRes<WriteFMovI32ToF32, [Andes45FMV]>;160def : WriteRes<WriteFMovF64ToI64, [Andes45FMV]>;161def : WriteRes<WriteFMovI64ToF64, [Andes45FMV]>;162 163// FMISC164let Latency = 2 in {165def : WriteRes<WriteFMinMax16, [Andes45FMISC]>;166def : WriteRes<WriteFMinMax32, [Andes45FMISC]>;167def : WriteRes<WriteFMinMax64, [Andes45FMISC]>;168def : WriteRes<WriteFClass16, [Andes45FMISC]>;169def : WriteRes<WriteFClass32, [Andes45FMISC]>;170def : WriteRes<WriteFClass64, [Andes45FMISC]>;171def : WriteRes<WriteFCmp16, [Andes45FMISC]>;172def : WriteRes<WriteFCmp32, [Andes45FMISC]>;173def : WriteRes<WriteFCmp64, [Andes45FMISC]>;174def : WriteRes<WriteFCvtF16ToI32, [Andes45FMISC]>;175def : WriteRes<WriteFCvtF16ToI64, [Andes45FMISC]>;176def : WriteRes<WriteFCvtF32ToI32, [Andes45FMISC]>;177def : WriteRes<WriteFCvtF32ToI64, [Andes45FMISC]>;178def : WriteRes<WriteFCvtF64ToI32, [Andes45FMISC]>;179def : WriteRes<WriteFCvtF64ToI64, [Andes45FMISC]>;180def : WriteRes<WriteFCvtI32ToF16, [Andes45FMISC]>;181def : WriteRes<WriteFCvtI32ToF32, [Andes45FMISC]>;182def : WriteRes<WriteFCvtI32ToF64, [Andes45FMISC]>;183def : WriteRes<WriteFCvtI64ToF16, [Andes45FMISC]>;184def : WriteRes<WriteFCvtI64ToF32, [Andes45FMISC]>;185def : WriteRes<WriteFCvtI64ToF64, [Andes45FMISC]>;186def : WriteRes<WriteFCvtF16ToF32, [Andes45FMISC]>;187def : WriteRes<WriteFCvtF16ToF64, [Andes45FMISC]>;188def : WriteRes<WriteFCvtF32ToF16, [Andes45FMISC]>;189def : WriteRes<WriteFCvtF32ToF64, [Andes45FMISC]>;190def : WriteRes<WriteFCvtF64ToF16, [Andes45FMISC]>;191def : WriteRes<WriteFCvtF64ToF32, [Andes45FMISC]>;192}193 194// Bitmanip195// Zba extension196def : WriteRes<WriteSHXADD, [Andes45ALU]>;197def : WriteRes<WriteSHXADD32, [Andes45ALU]>;198 199// Zbb extension200def : WriteRes<WriteRotateImm, [Andes45ALU]>;201def : WriteRes<WriteRotateImm32, [Andes45ALU]>;202def : WriteRes<WriteRotateReg, [Andes45ALU]>;203def : WriteRes<WriteRotateReg32, [Andes45ALU]>;204def : WriteRes<WriteREV8, [Andes45ALU]>;205def : WriteRes<WriteORCB, [Andes45ALU]>;206def : WriteRes<WriteIMinMax, [Andes45ALU]>;207 208let Latency = 3 in {209def : WriteRes<WriteCLZ, [Andes45ALU]>;210def : WriteRes<WriteCLZ32, [Andes45ALU]>;211def : WriteRes<WriteCTZ, [Andes45ALU]>;212def : WriteRes<WriteCTZ32, [Andes45ALU]>;213def : WriteRes<WriteCPOP, [Andes45ALU]>;214def : WriteRes<WriteCPOP32, [Andes45ALU]>;215}216 217// Zbc extension218let Latency = 3 in219def : WriteRes<WriteCLMUL, [Andes45ALU]>;220 221// Zbs extension222def : WriteRes<WriteSingleBit, [Andes45ALU]>;223def : WriteRes<WriteSingleBitImm, [Andes45ALU]>;224def : WriteRes<WriteBEXT, [Andes45ALU]>;225def : WriteRes<WriteBEXTI, [Andes45ALU]>;226 227// Others228def : WriteRes<WriteCSR, [Andes45CSR]>;229def : WriteRes<WriteNop, []>;230 231//===----------------------------------------------------------------------===//232 233// Bypass and advance234def : ReadAdvance<ReadIALU, 0>;235def : ReadAdvance<ReadIALU32, 0>;236def : ReadAdvance<ReadShiftImm, 0>;237def : ReadAdvance<ReadShiftImm32, 0>;238def : ReadAdvance<ReadShiftReg, 0>;239def : ReadAdvance<ReadShiftReg32, 0>;240def : ReadAdvance<ReadSFBJmp, 0>;241def : ReadAdvance<ReadSFBALU, 0>;242def : ReadAdvance<ReadJalr, 0>;243def : ReadAdvance<ReadJmp, 0>;244def : ReadAdvance<ReadIMul, 0>;245def : ReadAdvance<ReadIMul32, 0>;246def : ReadAdvance<ReadIDiv, 0>;247def : ReadAdvance<ReadIDiv32, 0>;248def : ReadAdvance<ReadIRem, 0>;249def : ReadAdvance<ReadIRem32, 0>;250def : ReadAdvance<ReadStoreData, 0>;251def : ReadAdvance<ReadMemBase, 0>;252def : ReadAdvance<ReadAtomicWA, 0>;253def : ReadAdvance<ReadAtomicWD, 0>;254def : ReadAdvance<ReadAtomicDA, 0>;255def : ReadAdvance<ReadAtomicDD, 0>;256def : ReadAdvance<ReadAtomicLDW, 0>;257def : ReadAdvance<ReadAtomicLDD, 0>;258def : ReadAdvance<ReadAtomicSTW, 0>;259def : ReadAdvance<ReadAtomicSTD, 0>;260def : ReadAdvance<ReadFStoreData, 0>;261def : ReadAdvance<ReadFMemBase, 0>;262def : ReadAdvance<ReadFAdd16, 0>;263def : ReadAdvance<ReadFAdd32, 0>;264def : ReadAdvance<ReadFAdd64, 0>;265def : ReadAdvance<ReadFMul16, 0>;266def : ReadAdvance<ReadFMul32, 0>;267def : ReadAdvance<ReadFMul64, 0>;268def : ReadAdvance<ReadFMA16, 0>;269def : ReadAdvance<ReadFMA32, 0>;270def : ReadAdvance<ReadFMA64, 0>;271def : ReadAdvance<ReadFMA16Addend, 0>;272def : ReadAdvance<ReadFMA32Addend, 0>;273def : ReadAdvance<ReadFMA64Addend, 0>;274def : ReadAdvance<ReadFDiv16, 0>;275def : ReadAdvance<ReadFDiv32, 0>;276def : ReadAdvance<ReadFDiv64, 0>;277def : ReadAdvance<ReadFSqrt16, 0>;278def : ReadAdvance<ReadFSqrt32, 0>;279def : ReadAdvance<ReadFSqrt64, 0>;280def : ReadAdvance<ReadFSGNJ16, 0>;281def : ReadAdvance<ReadFSGNJ32, 0>;282def : ReadAdvance<ReadFSGNJ64, 0>;283def : ReadAdvance<ReadFMovF16ToI16, 0>;284def : ReadAdvance<ReadFMovI16ToF16, 0>;285def : ReadAdvance<ReadFMovF32ToI32, 0>;286def : ReadAdvance<ReadFMovI32ToF32, 0>;287def : ReadAdvance<ReadFMovF64ToI64, 0>;288def : ReadAdvance<ReadFMovI64ToF64, 0>;289def : ReadAdvance<ReadFMinMax16, 0>;290def : ReadAdvance<ReadFMinMax32, 0>;291def : ReadAdvance<ReadFMinMax64, 0>;292def : ReadAdvance<ReadFClass16, 0>;293def : ReadAdvance<ReadFClass32, 0>;294def : ReadAdvance<ReadFClass64, 0>;295def : ReadAdvance<ReadFCmp16, 0>;296def : ReadAdvance<ReadFCmp32, 0>;297def : ReadAdvance<ReadFCmp64, 0>;298def : ReadAdvance<ReadFCvtF16ToI32, 0>;299def : ReadAdvance<ReadFCvtF16ToI64, 0>;300def : ReadAdvance<ReadFCvtF32ToI32, 0>;301def : ReadAdvance<ReadFCvtF32ToI64, 0>;302def : ReadAdvance<ReadFCvtF64ToI32, 0>;303def : ReadAdvance<ReadFCvtF64ToI64, 0>;304def : ReadAdvance<ReadFCvtI32ToF16, 0>;305def : ReadAdvance<ReadFCvtI32ToF32, 0>;306def : ReadAdvance<ReadFCvtI32ToF64, 0>;307def : ReadAdvance<ReadFCvtI64ToF16, 0>;308def : ReadAdvance<ReadFCvtI64ToF32, 0>;309def : ReadAdvance<ReadFCvtI64ToF64, 0>;310def : ReadAdvance<ReadFCvtF16ToF32, 0>;311def : ReadAdvance<ReadFCvtF16ToF64, 0>;312def : ReadAdvance<ReadFCvtF32ToF16, 0>;313def : ReadAdvance<ReadFCvtF32ToF64, 0>;314def : ReadAdvance<ReadFCvtF64ToF16, 0>;315def : ReadAdvance<ReadFCvtF64ToF32, 0>;316def : ReadAdvance<ReadSHXADD, 0>;317def : ReadAdvance<ReadSHXADD32, 0>;318def : ReadAdvance<ReadRotateImm, 1>;319def : ReadAdvance<ReadRotateImm32, 1>;320def : ReadAdvance<ReadRotateReg, 1>;321def : ReadAdvance<ReadRotateReg32, 1>;322def : ReadAdvance<ReadCLZ, 0>;323def : ReadAdvance<ReadCLZ32, 0>;324def : ReadAdvance<ReadCTZ, 0>;325def : ReadAdvance<ReadCTZ32, 0>;326def : ReadAdvance<ReadCPOP, 0>;327def : ReadAdvance<ReadCPOP32, 0>;328def : ReadAdvance<ReadREV8, 0>;329def : ReadAdvance<ReadORCB, 0>;330def : ReadAdvance<ReadIMinMax, 0>;331def : ReadAdvance<ReadCLMUL, 0>;332def : ReadAdvance<ReadSingleBit, 0>;333def : ReadAdvance<ReadSingleBitImm, 0>;334def : ReadAdvance<ReadCSR, 0>;335 336//===----------------------------------------------------------------------===//337// Unsupported extensions338defm : UnsupportedSchedQ;339defm : UnsupportedSchedV;340defm : UnsupportedSchedZabha;341defm : UnsupportedSchedZbkb;342defm : UnsupportedSchedZbkx;343defm : UnsupportedSchedZfa;344defm : UnsupportedSchedZvk;345defm : UnsupportedSchedXsf;346}347