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1//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// P8700 - a RISC-V processor by MIPS.11// Pipelines:12// - 2 Integer Arithmetic and Logical Units (ALU and AL2)13// - Multiply / Divide Unit (MDU)14// - Branch Unit (CTI)15// - Load Store Unit (LSU)16// - Short Floating Point Pipe (FPUS)17// - Long Floating Point Pipe (FPUL)18//===----------------------------------------------------------------------===//19 20def MIPSP8700Model : SchedMachineModel {21 int IssueWidth = 4;22 int MicroOpBufferSize = 96;23 int LoadLatency = 4;24 int MispredictPenalty = 8;25 let CompleteModel = 0;26}27 28let SchedModel = MIPSP8700Model in {29// Handle ALQ Pipelines.30// It contains 1 ALU Unit only.31def p8700ALQ : ProcResource<1> { let BufferSize = 16; }32 33// Handle AGQ Pipelines.34def p8700AGQ : ProcResource<3> { let BufferSize = 16; }35def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }36def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }37def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }38def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;39 40// Handle Multiply Divide Pipe.41def p8700GpDiv : ProcResource<1>;42def p8700GpMul : ProcResource<1>;43 44def : WriteRes<WriteIALU, [p8700WriteEitherALU]>;45def : WriteRes<WriteIALU32, [p8700WriteEitherALU]>;46def : WriteRes<WriteShiftImm, [p8700WriteEitherALU]>;47def : WriteRes<WriteShiftImm32, [p8700WriteEitherALU]>;48def : WriteRes<WriteShiftReg, [p8700WriteEitherALU]>;49def : WriteRes<WriteShiftReg32, [p8700WriteEitherALU]>;50 51// Handle zba.52def : WriteRes<WriteSHXADD, [p8700WriteEitherALU]>;53def : WriteRes<WriteSHXADD32, [p8700WriteEitherALU]>;54 55// Handle zbb.56let Latency = 2 in {57def : WriteRes<WriteCLZ, [p8700IssueAL2]>;58def : WriteRes<WriteCTZ, [p8700IssueAL2]>;59def : WriteRes<WriteCPOP, [p8700IssueAL2]>;60def : WriteRes<WriteCLZ32, [p8700IssueAL2]>;61def : WriteRes<WriteCTZ32, [p8700IssueAL2]>;62def : WriteRes<WriteCPOP32, [p8700IssueAL2]>;63}64def : WriteRes<WriteRotateReg, [p8700WriteEitherALU]>;65def : WriteRes<WriteRotateImm, [p8700WriteEitherALU]>;66def : WriteRes<WriteRotateReg32, [p8700WriteEitherALU]>;67def : WriteRes<WriteRotateImm32, [p8700WriteEitherALU]>;68def : WriteRes<WriteREV8, [p8700WriteEitherALU]>;69def : WriteRes<WriteORCB, [p8700WriteEitherALU]>;70def : WriteRes<WriteIMinMax, [p8700WriteEitherALU]>;71 72let Latency = 0 in73def : WriteRes<WriteNop, [p8700WriteEitherALU]>;74 75let Latency = 4 in {76def : WriteRes<WriteLDB, [p8700IssueLSU]>;77def : WriteRes<WriteLDH, [p8700IssueLSU]>;78def : WriteRes<WriteLDW, [p8700IssueLSU]>;79def : WriteRes<WriteLDD, [p8700IssueLSU]>;80 81def : WriteRes<WriteAtomicW, [p8700IssueLSU]>;82def : WriteRes<WriteAtomicD, [p8700IssueLSU]>;83def : WriteRes<WriteAtomicLDW, [p8700IssueLSU]>;84def : WriteRes<WriteAtomicLDD, [p8700IssueLSU]>;85}86 87let Latency = 8 in {88def : WriteRes<WriteFLD32, [p8700IssueLSU]>;89def : WriteRes<WriteFLD64, [p8700IssueLSU]>;90}91 92let Latency = 3 in {93def : WriteRes<WriteSTB, [p8700IssueLSU]>;94def : WriteRes<WriteSTH, [p8700IssueLSU]>;95def : WriteRes<WriteSTW, [p8700IssueLSU]>;96def : WriteRes<WriteSTD, [p8700IssueLSU]>;97 98def : WriteRes<WriteAtomicSTW, [p8700IssueLSU]>;99def : WriteRes<WriteAtomicSTD, [p8700IssueLSU]>;100}101 102def : WriteRes<WriteFST32, [p8700IssueLSU]>;103def : WriteRes<WriteFST64, [p8700IssueLSU]>;104 105let Latency = 7 in {106def : WriteRes<WriteFMovI32ToF32, [p8700IssueLSU]>;107def : WriteRes<WriteFMovF32ToI32, [p8700IssueLSU]>;108def : WriteRes<WriteFMovI64ToF64, [p8700IssueLSU]>;109def : WriteRes<WriteFMovF64ToI64, [p8700IssueLSU]>;110}111 112let Latency = 4 in {113def : WriteRes<WriteIMul, [p8700GpMul]>;114def : WriteRes<WriteIMul32, [p8700GpMul]>;115}116 117let Latency = 7, ReleaseAtCycles = [7] in {118def : WriteRes<WriteIDiv, [p8700GpDiv]>;119def : WriteRes<WriteIDiv32, [p8700GpDiv]>;120def : WriteRes<WriteIRem, [p8700GpDiv]>;121def : WriteRes<WriteIRem32, [p8700GpDiv]>;122}123 124def : WriteRes<WriteCSR, [p8700ALQ]>;125 126// Handle CTI Pipeline.127def : WriteRes<WriteJmp, [p8700IssueCTI]>;128def : WriteRes<WriteJal, [p8700IssueCTI]>;129def : WriteRes<WriteJalr, [p8700IssueCTI]>;130 131// Handle FPU Pipelines.132def p8700FPQ : ProcResource<3> { let BufferSize = 16; }133def p8700IssueFPUS : ProcResource<1> { let Super = p8700FPQ; }134def p8700IssueFPUL : ProcResource<1> { let Super = p8700FPQ; }135def p8700FpuApu : ProcResource<1>;136def p8700FpuLong : ProcResource<1>;137 138let Latency = 4 in {139def : WriteRes<WriteFCvtI32ToF32, [p8700IssueFPUL, p8700FpuApu]>;140def : WriteRes<WriteFCvtI32ToF64, [p8700IssueFPUL, p8700FpuApu]>;141def : WriteRes<WriteFCvtI64ToF32, [p8700IssueFPUL, p8700FpuApu]>;142def : WriteRes<WriteFCvtI64ToF64, [p8700IssueFPUL, p8700FpuApu]>;143def : WriteRes<WriteFCvtF32ToI32, [p8700IssueFPUL, p8700FpuApu]>;144def : WriteRes<WriteFCvtF32ToI64, [p8700IssueFPUL, p8700FpuApu]>;145def : WriteRes<WriteFCvtF32ToF64, [p8700IssueFPUL, p8700FpuApu]>;146def : WriteRes<WriteFCvtF64ToI32, [p8700IssueFPUL, p8700FpuApu]>;147def : WriteRes<WriteFCvtF64ToI64, [p8700IssueFPUL, p8700FpuApu]>;148def : WriteRes<WriteFCvtF64ToF32, [p8700IssueFPUL, p8700FpuApu]>;149 150def : WriteRes<WriteFAdd32, [p8700IssueFPUL, p8700FpuApu]>;151def : WriteRes<WriteFAdd64, [p8700IssueFPUL, p8700FpuApu]>;152}153 154let Latency = 2 in {155def : WriteRes<WriteFSGNJ32, [p8700IssueFPUS, p8700FpuApu]>;156def : WriteRes<WriteFMinMax32, [p8700IssueFPUS, p8700FpuApu]>;157def : WriteRes<WriteFSGNJ64, [p8700IssueFPUS, p8700FpuApu]>;158def : WriteRes<WriteFMinMax64, [p8700IssueFPUS, p8700FpuApu]>;159 160def : WriteRes<WriteFCmp32, [p8700IssueFPUS, p8700FpuApu]>;161def : WriteRes<WriteFCmp64, [p8700IssueFPUS, p8700FpuApu]>;162}163 164def : WriteRes<WriteFClass32, [p8700IssueFPUS, p8700FpuApu]>;165def : WriteRes<WriteFClass64, [p8700IssueFPUS, p8700FpuApu]>;166 167let Latency = 8 in {168def : WriteRes<WriteFMA32, [p8700FpuLong, p8700FpuApu]>;169def : WriteRes<WriteFMA64, [p8700FpuLong, p8700FpuApu]>;170}171 172let Latency = 5 in {173def : WriteRes<WriteFMul32, [p8700FpuLong, p8700FpuApu]>;174def : WriteRes<WriteFMul64, [p8700FpuLong, p8700FpuApu]>;175}176 177let Latency = 11, ReleaseAtCycles = [1, 11] in {178def : WriteRes<WriteFDiv32, [p8700FpuLong, p8700FpuApu]>;179def : WriteRes<WriteFSqrt32, [p8700FpuLong, p8700FpuApu]>;180}181 182let Latency = 17, ReleaseAtCycles = [1, 17] in {183def : WriteRes<WriteFDiv64, [p8700IssueFPUL, p8700FpuApu]>;184def : WriteRes<WriteFSqrt64, [p8700IssueFPUL, p8700FpuApu]>;185}186 187// Bypass and advance.188def : ReadAdvance<ReadIALU, 0>;189def : ReadAdvance<ReadIALU32, 0>;190def : ReadAdvance<ReadShiftImm, 0>;191def : ReadAdvance<ReadShiftImm32, 0>;192def : ReadAdvance<ReadShiftReg, 0>;193def : ReadAdvance<ReadShiftReg32, 0>;194def : ReadAdvance<ReadSHXADD, 0>;195def : ReadAdvance<ReadSHXADD32, 0>;196def : ReadAdvance<ReadRotateReg, 0>;197def : ReadAdvance<ReadRotateImm, 0>;198def : ReadAdvance<ReadCLZ, 0>;199def : ReadAdvance<ReadCTZ, 0>;200def : ReadAdvance<ReadCPOP, 0>;201def : ReadAdvance<ReadRotateReg32, 0>;202def : ReadAdvance<ReadRotateImm32, 0>;203def : ReadAdvance<ReadCLZ32, 0>;204def : ReadAdvance<ReadCTZ32, 0>;205def : ReadAdvance<ReadCPOP32, 0>;206def : ReadAdvance<ReadREV8, 0>;207def : ReadAdvance<ReadORCB, 0>;208def : ReadAdvance<ReadIMul, 0>;209def : ReadAdvance<ReadIMul32, 0>;210def : ReadAdvance<ReadIDiv, 0>;211def : ReadAdvance<ReadIDiv32, 0>;212def : ReadAdvance<ReadJmp, 0>;213def : ReadAdvance<ReadJalr, 0>;214def : ReadAdvance<ReadFMovI32ToF32, 0>;215def : ReadAdvance<ReadFMovF32ToI32, 0>;216def : ReadAdvance<ReadFMovI64ToF64, 0>;217def : ReadAdvance<ReadFMovF64ToI64, 0>;218def : ReadAdvance<ReadFSGNJ32, 0>;219def : ReadAdvance<ReadFMinMax32, 0>;220def : ReadAdvance<ReadFSGNJ64, 0>;221def : ReadAdvance<ReadFMinMax64, 0>;222def : ReadAdvance<ReadFCmp32, 0>;223def : ReadAdvance<ReadFCmp64, 0>;224def : ReadAdvance<ReadFCvtI32ToF32, 0>;225def : ReadAdvance<ReadFCvtI32ToF64, 0>;226def : ReadAdvance<ReadFCvtI64ToF32, 0>;227def : ReadAdvance<ReadFCvtI64ToF64, 0>;228def : ReadAdvance<ReadFCvtF32ToI32, 0>;229def : ReadAdvance<ReadFCvtF32ToI64, 0>;230def : ReadAdvance<ReadFCvtF32ToF64, 0>;231def : ReadAdvance<ReadFCvtF64ToI32, 0>;232def : ReadAdvance<ReadFCvtF64ToI64, 0>;233def : ReadAdvance<ReadFCvtF64ToF32, 0>;234def : ReadAdvance<ReadFAdd32, 0>;235def : ReadAdvance<ReadFAdd64, 0>;236def : ReadAdvance<ReadFMul32, 0>;237def : ReadAdvance<ReadFMul64, 0>;238def : ReadAdvance<ReadFMA32, 0>;239def : ReadAdvance<ReadFMA32Addend, 0>;240def : ReadAdvance<ReadFMA64, 0>;241def : ReadAdvance<ReadFMA64Addend, 0>;242def : ReadAdvance<ReadFDiv32, 0>;243def : ReadAdvance<ReadFSqrt32, 0>;244def : ReadAdvance<ReadFDiv64, 0>;245def : ReadAdvance<ReadFSqrt64, 0>;246def : ReadAdvance<ReadAtomicWA, 0>;247def : ReadAdvance<ReadAtomicWD, 0>;248def : ReadAdvance<ReadAtomicDA, 0>;249def : ReadAdvance<ReadAtomicDD, 0>;250def : ReadAdvance<ReadAtomicLDW, 0>;251def : ReadAdvance<ReadAtomicLDD, 0>;252def : ReadAdvance<ReadAtomicSTW, 0>;253def : ReadAdvance<ReadAtomicSTD, 0>;254def : ReadAdvance<ReadFStoreData, 0>;255def : ReadAdvance<ReadCSR, 0>;256def : ReadAdvance<ReadMemBase, 0>;257def : ReadAdvance<ReadStoreData, 0>;258def : ReadAdvance<ReadFMemBase, 0>;259def : ReadAdvance<ReadFClass32, 0>;260def : ReadAdvance<ReadFClass64, 0>;261def : ReadAdvance<ReadIMinMax, 0>;262def : ReadAdvance<ReadIRem, 0>;263def : ReadAdvance<ReadIRem32, 0>;264 265// Unsupported extensions.266defm : UnsupportedSchedQ;267defm : UnsupportedSchedV;268defm : UnsupportedSchedZbc;269defm : UnsupportedSchedZbs;270defm : UnsupportedSchedZbkb;271defm : UnsupportedSchedZbkx;272defm : UnsupportedSchedZfa;273defm : UnsupportedSchedZfhmin;274defm : UnsupportedSchedSFB;275defm : UnsupportedSchedZabha;276defm : UnsupportedSchedZvk;277defm : UnsupportedSchedXsf;278}279