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1//==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9// ===---------------------------------------------------------------------===//10// The following definitions describe the simpler per-operand machine model.11// This works with MachineScheduler. See MCSchedule.h for details.12 13// Rocket machine model for scheduling and other instruction cost heuristics.14def RocketModel : SchedMachineModel {15 let MicroOpBufferSize = 0; // Rocket is in-order.16 let IssueWidth = 1; // 1 micro-op is dispatched per cycle.17 let LoadLatency = 3;18 let MispredictPenalty = 3;19 let CompleteModel = false;20 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,21 HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,22 HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,23 HasStdExtZkr, HasVInstructions, HasVInstructionsI64];24}25 26//===----------------------------------------------------------------------===//27// Define each kind of processor resource and number available.28 29// Modeling each pipeline as a ProcResource using the BufferSize = 0 since30// Rocket is in-order.31 32let BufferSize = 0 in {33def RocketUnitALU : ProcResource<1>; // Int ALU34def RocketUnitIMul : ProcResource<1>; // Int Multiply35def RocketUnitMem : ProcResource<1>; // Load/Store36def RocketUnitB : ProcResource<1>; // Branch37 38def RocketUnitFPALU : ProcResource<1>; // FP ALU39}40 41let BufferSize = 1 in {42def RocketUnitIDiv : ProcResource<1>; // Int Division43def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt44}45 46//===----------------------------------------------------------------------===//47 48let SchedModel = RocketModel in {49 50// Branching51def : WriteRes<WriteJmp, [RocketUnitB]>;52def : WriteRes<WriteJal, [RocketUnitB]>;53def : WriteRes<WriteJalr, [RocketUnitB]>;54 55// Integer arithmetic and logic56def : WriteRes<WriteIALU32, [RocketUnitALU]>;57def : WriteRes<WriteIALU, [RocketUnitALU]>;58def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;59def : WriteRes<WriteShiftImm, [RocketUnitALU]>;60def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;61def : WriteRes<WriteShiftReg, [RocketUnitALU]>;62 63// Integer multiplication64let Latency = 4 in {65def : WriteRes<WriteIMul, [RocketUnitIMul]>;66def : WriteRes<WriteIMul32, [RocketUnitIMul]>;67}68 69// Integer division70// Worst case latency is used.71def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {72 let Latency = 34;73 let ReleaseAtCycles = [34];74}75def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {76 let Latency = 33;77 let ReleaseAtCycles = [33];78}79 80// Integer remainder81def : WriteRes<WriteIRem32, [RocketUnitIDiv]> {82 let Latency = 34;83 let ReleaseAtCycles = [34];84}85def : WriteRes<WriteIRem, [RocketUnitIDiv]> {86 let Latency = 33;87 let ReleaseAtCycles = [33];88}89 90// Memory91def : WriteRes<WriteSTB, [RocketUnitMem]>;92def : WriteRes<WriteSTH, [RocketUnitMem]>;93def : WriteRes<WriteSTW, [RocketUnitMem]>;94def : WriteRes<WriteSTD, [RocketUnitMem]>;95def : WriteRes<WriteFST32, [RocketUnitMem]>;96def : WriteRes<WriteFST64, [RocketUnitMem]>;97 98let Latency = 3 in {99def : WriteRes<WriteLDB, [RocketUnitMem]>;100def : WriteRes<WriteLDH, [RocketUnitMem]>;101}102 103let Latency = 2 in {104def : WriteRes<WriteLDW, [RocketUnitMem]>;105def : WriteRes<WriteLDD, [RocketUnitMem]>;106def : WriteRes<WriteFLD32, [RocketUnitMem]>;107def : WriteRes<WriteFLD64, [RocketUnitMem]>;108 109// Atomic memory110def : WriteRes<WriteAtomicW, [RocketUnitMem]>;111def : WriteRes<WriteAtomicD, [RocketUnitMem]>;112 113def : WriteRes<WriteAtomicLDW, [RocketUnitMem]>;114def : WriteRes<WriteAtomicLDD, [RocketUnitMem]>;115}116 117def : WriteRes<WriteAtomicSTW, [RocketUnitMem]>;118def : WriteRes<WriteAtomicSTD, [RocketUnitMem]>;119 120// Single precision.121let Latency = 4 in {122def : WriteRes<WriteFAdd32, [RocketUnitFPALU]>;123def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>;124def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>;125}126 127// Double precision128let Latency = 6 in {129def : WriteRes<WriteFAdd64, [RocketUnitFPALU]>;130def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>;131def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>;132}133 134// Conversions135let Latency = 2 in {136def : WriteRes<WriteFCvtI32ToF32, [RocketUnitFPALU]>;137def : WriteRes<WriteFCvtI32ToF64, [RocketUnitFPALU]>;138def : WriteRes<WriteFCvtI64ToF32, [RocketUnitFPALU]>;139def : WriteRes<WriteFCvtI64ToF64, [RocketUnitFPALU]>;140def : WriteRes<WriteFCvtF32ToI32, [RocketUnitFPALU]>;141def : WriteRes<WriteFCvtF32ToI64, [RocketUnitFPALU]>;142def : WriteRes<WriteFCvtF64ToI32, [RocketUnitFPALU]>;143def : WriteRes<WriteFCvtF64ToI64, [RocketUnitFPALU]>;144def : WriteRes<WriteFCvtF32ToF64, [RocketUnitFPALU]>;145def : WriteRes<WriteFCvtF64ToF32, [RocketUnitFPALU]>;146 147def : WriteRes<WriteFClass32, [RocketUnitFPALU]>;148def : WriteRes<WriteFClass64, [RocketUnitFPALU]>;149def : WriteRes<WriteFCmp32, [RocketUnitFPALU]>;150def : WriteRes<WriteFCmp64, [RocketUnitFPALU]>;151def : WriteRes<WriteFMovF32ToI32, [RocketUnitFPALU]>;152def : WriteRes<WriteFMovI32ToF32, [RocketUnitFPALU]>;153def : WriteRes<WriteFMovF64ToI64, [RocketUnitFPALU]>;154def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;155}156 157// FP multiplication158let Latency = 5 in {159def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;160def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;161}162 163let Latency = 7 in {164def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;165def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;166}167 168// FP division169// FP division unit on Rocket is not pipelined, so set resource cycles to latency.170let Latency = 20, ReleaseAtCycles = [20] in {171def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;172def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;173}174 175// FP square root unit on Rocket is not pipelined, so set resource cycles to latency.176def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;177 let ReleaseAtCycles = [20]; }178def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;179 let ReleaseAtCycles = [25]; }180 181// Others182def : WriteRes<WriteCSR, []>;183def : WriteRes<WriteNop, []>;184 185def : InstRW<[WriteIALU], (instrs COPY)>;186 187//===----------------------------------------------------------------------===//188// Bypass and advance189def : ReadAdvance<ReadJmp, 0>;190def : ReadAdvance<ReadJalr, 0>;191def : ReadAdvance<ReadCSR, 0>;192def : ReadAdvance<ReadStoreData, 0>;193def : ReadAdvance<ReadMemBase, 0>;194def : ReadAdvance<ReadIALU, 0>;195def : ReadAdvance<ReadIALU32, 0>;196def : ReadAdvance<ReadShiftImm, 0>;197def : ReadAdvance<ReadShiftImm32, 0>;198def : ReadAdvance<ReadShiftReg, 0>;199def : ReadAdvance<ReadShiftReg32, 0>;200def : ReadAdvance<ReadIDiv, 0>;201def : ReadAdvance<ReadIDiv32, 0>;202def : ReadAdvance<ReadIRem, 0>;203def : ReadAdvance<ReadIRem32, 0>;204def : ReadAdvance<ReadIMul, 0>;205def : ReadAdvance<ReadIMul32, 0>;206def : ReadAdvance<ReadAtomicWA, 0>;207def : ReadAdvance<ReadAtomicWD, 0>;208def : ReadAdvance<ReadAtomicDA, 0>;209def : ReadAdvance<ReadAtomicDD, 0>;210def : ReadAdvance<ReadAtomicLDW, 0>;211def : ReadAdvance<ReadAtomicLDD, 0>;212def : ReadAdvance<ReadAtomicSTW, 0>;213def : ReadAdvance<ReadAtomicSTD, 0>;214def : ReadAdvance<ReadFStoreData, 0>;215def : ReadAdvance<ReadFMemBase, 0>;216def : ReadAdvance<ReadFAdd32, 0>;217def : ReadAdvance<ReadFAdd64, 0>;218def : ReadAdvance<ReadFMul32, 0>;219def : ReadAdvance<ReadFMul64, 0>;220def : ReadAdvance<ReadFMA32, 0>;221def : ReadAdvance<ReadFMA32Addend, 0>;222def : ReadAdvance<ReadFMA64, 0>;223def : ReadAdvance<ReadFMA64Addend, 0>;224def : ReadAdvance<ReadFDiv32, 0>;225def : ReadAdvance<ReadFDiv64, 0>;226def : ReadAdvance<ReadFSqrt32, 0>;227def : ReadAdvance<ReadFSqrt64, 0>;228def : ReadAdvance<ReadFCmp32, 0>;229def : ReadAdvance<ReadFCmp64, 0>;230def : ReadAdvance<ReadFSGNJ32, 0>;231def : ReadAdvance<ReadFSGNJ64, 0>;232def : ReadAdvance<ReadFMinMax32, 0>;233def : ReadAdvance<ReadFMinMax64, 0>;234def : ReadAdvance<ReadFCvtF32ToI32, 0>;235def : ReadAdvance<ReadFCvtF32ToI64, 0>;236def : ReadAdvance<ReadFCvtF64ToI32, 0>;237def : ReadAdvance<ReadFCvtF64ToI64, 0>;238def : ReadAdvance<ReadFCvtI32ToF32, 0>;239def : ReadAdvance<ReadFCvtI32ToF64, 0>;240def : ReadAdvance<ReadFCvtI64ToF32, 0>;241def : ReadAdvance<ReadFCvtI64ToF64, 0>;242def : ReadAdvance<ReadFCvtF32ToF64, 0>;243def : ReadAdvance<ReadFCvtF64ToF32, 0>;244def : ReadAdvance<ReadFMovF32ToI32, 0>;245def : ReadAdvance<ReadFMovI32ToF32, 0>;246def : ReadAdvance<ReadFMovF64ToI64, 0>;247def : ReadAdvance<ReadFMovI64ToF64, 0>;248def : ReadAdvance<ReadFClass32, 0>;249def : ReadAdvance<ReadFClass64, 0>;250 251//===----------------------------------------------------------------------===//252// Unsupported extensions253defm : UnsupportedSchedQ;254defm : UnsupportedSchedV;255defm : UnsupportedSchedZabha;256defm : UnsupportedSchedZba;257defm : UnsupportedSchedZbb;258defm : UnsupportedSchedZbc;259defm : UnsupportedSchedZbs;260defm : UnsupportedSchedZbkb;261defm : UnsupportedSchedZbkx;262defm : UnsupportedSchedZfa;263defm : UnsupportedSchedZfhmin;264defm : UnsupportedSchedSFB;265defm : UnsupportedSchedZvk;266defm : UnsupportedSchedXsf;267}268