1243 lines · plain
1//==- RISCVSchedSiFiveP400.td - SiFiveP400 Scheduling Defs ---*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10 11/// c is true if mx has the worst case behavior compared to LMULs in MxList.12/// On the SiFiveP400, the worst case LMUL is the Largest LMUL13/// and the worst case sew is the smallest SEW for that LMUL.14class SiFiveP400IsWorstCaseMX<string mx, list<string> MxList> {15 string LLMUL = LargestLMUL<MxList>.r;16 bit c = !eq(mx, LLMUL);17}18 19class SiFiveP400IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {20 string LLMUL = LargestLMUL<MxList>.r;21 int SSEW = SmallestSEW<mx, isF>.r;22 bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));23}24 25defvar SiFiveP400VLEN = 128;26 27// 1 Micro-Op per cycle.28class SiFiveP400GetLMulCycles<string mx> {29 int c = !cond(30 !eq(mx, "M1") : 1,31 !eq(mx, "M2") : 2,32 !eq(mx, "M4") : 4,33 !eq(mx, "M8") : 8,34 !eq(mx, "MF2") : 1,35 !eq(mx, "MF4") : 1,36 !eq(mx, "MF8") : 137 );38}39 40class SiFiveP400GetVLMAX<string mx, int sew> {41 defvar LMUL = SiFiveP400GetLMulCycles<mx>.c;42 int val = !cond(43 !eq(mx, "MF2") : !div(!div(SiFiveP400VLEN, 2), sew),44 !eq(mx, "MF4") : !div(!div(SiFiveP400VLEN, 4), sew),45 !eq(mx, "MF8") : !div(!div(SiFiveP400VLEN, 8), sew),46 true: !div(!mul(SiFiveP400VLEN, LMUL), sew)47 );48}49 50class SiFiveP400StridedLdStLatency<string mx, int sew> {51 defvar VL = SiFiveP400GetVLMAX<mx, sew>.val;52 int val = !cond(53 !eq(VL, 2): 13,54 !eq(VL, 4): 18,55 !eq(VL, 8): 22,56 !eq(VL, 16): 30,57 // VL=32,64,12858 true: !sub(VL, 2)59 );60}61 62// Latency for segmented loads and stores are calculated as vl * nf.63class SiFiveP400SegmentedLdStCycles<string mx, int sew, int nf> {64 int c = !mul(SiFiveP400GetVLMAX<mx, sew>.val, nf);65}66 67// Both variants of floating point vector reductions are based on numbers collected68// from llvm-exegesis.69class VFReduceBaseCycles<int sew> {70 // The latency for simple unordered VFReduce is `C + 6 * log2(LMUL)`,71 // and `C * LMUL` for ordered VFReduce. This helper class provides the `C`.72 int val = !cond(!eq(sew, 16): 16,73 !eq(sew, 32): 10,74 !eq(sew, 64): 6);75}76 77class AdvancedVFReduceCycles<int sew, string mx> {78 // SEW = 64 has lower latencies and RThroughputs than other SEWs.79 int latency = !cond(!eq(mx, "M1"): !if(!eq(sew, 64), 4, 6),80 !eq(mx, "M2"): !if(!eq(sew, 64), 6, 8),81 !eq(mx, "M4"): !if(!eq(sew, 64), 8, 10),82 !eq(mx, "M8"): !if(!eq(sew, 64), 11, 13),83 true: !if(!eq(sew, 64), 4, 6));84 int rthroughput = !cond(!eq(mx, "M1"): !if(!eq(sew, 64), 2, 3),85 !eq(mx, "M2"): !if(!eq(sew, 64), 3, 4),86 !eq(mx, "M4"): !if(!eq(sew, 64), 5, 6),87 !eq(mx, "M8"): !if(!eq(sew, 64), 10, 12),88 true: !if(!eq(sew, 64), 2, 3));89}90 91// Both variants of integer vector reductions are based on numbers collected92// from llvm-exegesis.93// TODO: Fractional LMUL's latency and rthroughput.94class SimpleVIReduceCycles<string mx> {95 defvar LMul = SiFiveP400GetLMulCycles<mx>.c;96 int latency = !mul(LMul, 2);97 int rthroughput = !cond(98 !eq(mx, "M1"): 1,99 !eq(mx, "M2"): 2,100 !eq(mx, "M4"): 4,101 !eq(mx, "M8"): 9,102 true: 1);103}104 105class AdvancedVIReduceCycles<int sew, string mx> {106 // `C - 2 * log2(SEW)`, where `C` = 16.1, 18.1, 20.1, and 23.8 for107 // M1/2/4/8, respectively.108 int latency = !cond(!eq(mx, "M1"): !sub(16, !mul(2, !logtwo(sew))),109 !eq(mx, "M2"): !sub(18, !mul(2, !logtwo(sew))),110 !eq(mx, "M4"): !sub(20, !mul(2, !logtwo(sew))),111 !eq(mx, "M8"): !sub(23, !mul(2, !logtwo(sew))),112 true: 4);113 int rthroughput = !cond(114 // `8.3 - 1.02 * log2(SEW)`115 !eq(mx, "M1"): !sub(8, !logtwo(sew)),116 // `10.0 - 1.16 * log2(SEW)`. Note that `9 - log2(SEW)`117 // is closer to the floor value of the original formula.118 !eq(mx, "M2"): !sub(9, !logtwo(sew)),119 // `14.2 - 1.53 * log2(SEW)`120 !eq(mx, "M4"): !div(!sub(1420, !mul(153, !logtwo(sew))), 100),121 // `24.1 - 2.3 * log2(SEW)`122 !eq(mx, "M8"): !div(!sub(241, !mul(23, !logtwo(sew))), 10),123 true: 1);124}125 126class SiFiveP400VSM3CCycles<string mx> {127 // c = ceil(LMUL / 2)128 int c = !cond(!eq(mx, "M2") : 1,129 !eq(mx, "M4") : 2,130 !eq(mx, "M8") : 4,131 true : 1);132}133 134def SiFiveP400Model : SchedMachineModel {135 let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.136 let MicroOpBufferSize = 96; // Max micro-ops that can be buffered.137 let LoadLatency = 4; // Cycles for loads to access the cache.138 let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.139 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,140 HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,141 HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,142 HasStdExtZkr];143 let CompleteModel = false;144}145 146// The SiFiveP400 microarchitecure has 6 pipelines:147// Three pipelines for integer operations.148// One pipeline for FPU operations.149// One pipeline for Load operations.150// One pipeline for Store operations.151let SchedModel = SiFiveP400Model in {152 153def SiFiveP400IEXQ0 : ProcResource<1>;154def SiFiveP400IEXQ1 : ProcResource<1>;155def SiFiveP400IEXQ2 : ProcResource<1>;156def SiFiveP400FEXQ0 : ProcResource<1>;157def SiFiveP400Load : ProcResource<1>;158def SiFiveP400Store : ProcResource<1>;159 160def SiFiveP400IntArith : ProcResGroup<[SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2]>;161defvar SiFiveP400Branch = SiFiveP400IEXQ0;162defvar SiFiveP400SYS = SiFiveP400IEXQ1;163defvar SiFiveP400MulDiv = SiFiveP400IEXQ2;164defvar SiFiveP400I2F = SiFiveP400IEXQ2;165def SiFiveP400Div : ProcResource<1>;166 167defvar SiFiveP400FloatArith = SiFiveP400FEXQ0;168defvar SiFiveP400F2I = SiFiveP400FEXQ0;169def SiFiveP400FloatDiv : ProcResource<1>;170 171// Vector pipeline172def SiFiveP400VEXQ0 : ProcResource<1>;173def SiFiveP400VLD : ProcResource<1>;174def SiFiveP400VST : ProcResource<1>;175def SiFiveP400VDiv : ProcResource<1>;176def SiFiveP400VFloatDiv : ProcResource<1>;177 178let Latency = 1 in {179// Integer arithmetic and logic180def : WriteRes<WriteIALU, [SiFiveP400IntArith]>;181def : WriteRes<WriteIALU32, [SiFiveP400IntArith]>;182def : WriteRes<WriteShiftImm, [SiFiveP400IntArith]>;183def : WriteRes<WriteShiftImm32, [SiFiveP400IntArith]>;184def : WriteRes<WriteShiftReg, [SiFiveP400IntArith]>;185def : WriteRes<WriteShiftReg32, [SiFiveP400IntArith]>;186// Branching187def : WriteRes<WriteJmp, [SiFiveP400Branch]>;188def : WriteRes<WriteJal, [SiFiveP400Branch]>;189def : WriteRes<WriteJalr, [SiFiveP400Branch]>;190}191 192// CMOV193def P400WriteCMOV : SchedWriteRes<[SiFiveP400Branch, SiFiveP400IEXQ1]> {194 let Latency = 2;195 let NumMicroOps = 2;196}197def : InstRW<[P400WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;198 199let Latency = 2 in {200// Integer multiplication201def : WriteRes<WriteIMul, [SiFiveP400MulDiv]>;202def : WriteRes<WriteIMul32, [SiFiveP400MulDiv]>;203// cpop[w] look exactly like multiply.204def : WriteRes<WriteCPOP, [SiFiveP400MulDiv]>;205def : WriteRes<WriteCPOP32, [SiFiveP400MulDiv]>;206}207 208// Integer division209def : WriteRes<WriteIDiv, [SiFiveP400MulDiv, SiFiveP400Div]> {210 let Latency = 35;211 let ReleaseAtCycles = [1, 34];212}213def : WriteRes<WriteIDiv32, [SiFiveP400MulDiv, SiFiveP400Div]> {214 let Latency = 20;215 let ReleaseAtCycles = [1, 19];216}217 218// Integer remainder219def : WriteRes<WriteIRem, [SiFiveP400MulDiv, SiFiveP400Div]> {220 let Latency = 35;221 let ReleaseAtCycles = [1, 34];222}223def : WriteRes<WriteIRem32, [SiFiveP400MulDiv, SiFiveP400Div]> {224 let Latency = 20;225 let ReleaseAtCycles = [1, 19];226}227 228let Latency = 1 in {229// Bitmanip230def : WriteRes<WriteRotateImm, [SiFiveP400IntArith]>;231def : WriteRes<WriteRotateImm32, [SiFiveP400IntArith]>;232def : WriteRes<WriteRotateReg, [SiFiveP400IntArith]>;233def : WriteRes<WriteRotateReg32, [SiFiveP400IntArith]>;234 235def : WriteRes<WriteCLZ, [SiFiveP400IntArith]>;236def : WriteRes<WriteCLZ32, [SiFiveP400IntArith]>;237def : WriteRes<WriteCTZ, [SiFiveP400IntArith]>;238def : WriteRes<WriteCTZ32, [SiFiveP400IntArith]>;239 240def : WriteRes<WriteORCB, [SiFiveP400IntArith]>;241def : WriteRes<WriteIMinMax, [SiFiveP400IntArith]>;242 243def : WriteRes<WriteREV8, [SiFiveP400IntArith]>;244 245def : WriteRes<WriteSHXADD, [SiFiveP400IntArith]>;246def : WriteRes<WriteSHXADD32, [SiFiveP400IntArith]>;247 248def : WriteRes<WriteSingleBit, [SiFiveP400IntArith]>;249def : WriteRes<WriteSingleBitImm, [SiFiveP400IntArith]>;250def : WriteRes<WriteBEXT, [SiFiveP400IntArith]>;251def : WriteRes<WriteBEXTI, [SiFiveP400IntArith]>;252}253 254// Memory255let Latency = 1 in {256def : WriteRes<WriteSTB, [SiFiveP400Store]>;257def : WriteRes<WriteSTH, [SiFiveP400Store]>;258def : WriteRes<WriteSTW, [SiFiveP400Store]>;259def : WriteRes<WriteSTD, [SiFiveP400Store]>;260def : WriteRes<WriteFST16, [SiFiveP400Store]>;261def : WriteRes<WriteFST32, [SiFiveP400Store]>;262def : WriteRes<WriteFST64, [SiFiveP400Store]>;263}264let Latency = 4 in {265def : WriteRes<WriteLDB, [SiFiveP400Load]>;266def : WriteRes<WriteLDH, [SiFiveP400Load]>;267}268let Latency = 4 in {269def : WriteRes<WriteLDW, [SiFiveP400Load]>;270def : WriteRes<WriteLDD, [SiFiveP400Load]>;271}272 273let Latency = 5 in {274def : WriteRes<WriteFLD16, [SiFiveP400Load]>;275def : WriteRes<WriteFLD32, [SiFiveP400Load]>;276def : WriteRes<WriteFLD64, [SiFiveP400Load]>;277}278 279// Atomic memory280let Latency = 3 in {281def : WriteRes<WriteAtomicSTW, [SiFiveP400Store]>;282def : WriteRes<WriteAtomicSTD, [SiFiveP400Store]>;283def : WriteRes<WriteAtomicW, [SiFiveP400Load]>;284def : WriteRes<WriteAtomicD, [SiFiveP400Load]>;285def : WriteRes<WriteAtomicLDW, [SiFiveP400Load]>;286def : WriteRes<WriteAtomicLDD, [SiFiveP400Load]>;287}288 289// Floating point290let Latency = 4 in {291def : WriteRes<WriteFAdd16, [SiFiveP400FloatArith]>;292def : WriteRes<WriteFAdd32, [SiFiveP400FloatArith]>;293def : WriteRes<WriteFAdd64, [SiFiveP400FloatArith]>;294 295def : WriteRes<WriteFMul16, [SiFiveP400FloatArith]>;296def : WriteRes<WriteFMul32, [SiFiveP400FloatArith]>;297def : WriteRes<WriteFMul64, [SiFiveP400FloatArith]>;298 299def : WriteRes<WriteFMA16, [SiFiveP400FloatArith]>;300def : WriteRes<WriteFMA32, [SiFiveP400FloatArith]>;301def : WriteRes<WriteFMA64, [SiFiveP400FloatArith]>;302}303 304let Latency = 2 in {305def : WriteRes<WriteFSGNJ16, [SiFiveP400FloatArith]>;306def : WriteRes<WriteFSGNJ32, [SiFiveP400FloatArith]>;307def : WriteRes<WriteFSGNJ64, [SiFiveP400FloatArith]>;308 309def : WriteRes<WriteFMinMax16, [SiFiveP400FloatArith]>;310def : WriteRes<WriteFMinMax32, [SiFiveP400FloatArith]>;311def : WriteRes<WriteFMinMax64, [SiFiveP400FloatArith]>;312}313 314// Half precision.315def : WriteRes<WriteFDiv16, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {316 let Latency = 19;317 let ReleaseAtCycles = [1, 18];318}319def : WriteRes<WriteFSqrt16, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {320 let Latency = 18;321 let ReleaseAtCycles = [1, 17];322}323 324// Single precision.325def : WriteRes<WriteFDiv32, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {326 let Latency = 19;327 let ReleaseAtCycles = [1, 18];328}329def : WriteRes<WriteFSqrt32, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {330 let Latency = 18;331 let ReleaseAtCycles = [1, 17];332}333 334// Double precision335def : WriteRes<WriteFDiv64, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {336 let Latency = 33;337 let ReleaseAtCycles = [1, 32];338}339def : WriteRes<WriteFSqrt64, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {340 let Latency = 33;341 let ReleaseAtCycles = [1, 32];342}343 344// Conversions345let Latency = 2 in {346def : WriteRes<WriteFCvtI32ToF16, [SiFiveP400I2F]>;347def : WriteRes<WriteFCvtI32ToF32, [SiFiveP400I2F]>;348def : WriteRes<WriteFCvtI32ToF64, [SiFiveP400I2F]>;349def : WriteRes<WriteFCvtI64ToF16, [SiFiveP400I2F]>;350def : WriteRes<WriteFCvtI64ToF32, [SiFiveP400I2F]>;351def : WriteRes<WriteFCvtI64ToF64, [SiFiveP400I2F]>;352def : WriteRes<WriteFCvtF16ToI32, [SiFiveP400F2I]>;353def : WriteRes<WriteFCvtF16ToI64, [SiFiveP400F2I]>;354def : WriteRes<WriteFCvtF16ToF32, [SiFiveP400FloatArith]>;355def : WriteRes<WriteFCvtF16ToF64, [SiFiveP400FloatArith]>;356def : WriteRes<WriteFCvtF32ToI32, [SiFiveP400F2I]>;357def : WriteRes<WriteFCvtF32ToI64, [SiFiveP400F2I]>;358def : WriteRes<WriteFCvtF32ToF16, [SiFiveP400FloatArith]>;359def : WriteRes<WriteFCvtF32ToF64, [SiFiveP400FloatArith]>;360def : WriteRes<WriteFCvtF64ToI32, [SiFiveP400F2I]>;361def : WriteRes<WriteFCvtF64ToI64, [SiFiveP400F2I]>;362def : WriteRes<WriteFCvtF64ToF16, [SiFiveP400FloatArith]>;363def : WriteRes<WriteFCvtF64ToF32, [SiFiveP400FloatArith]>;364 365def : WriteRes<WriteFClass16, [SiFiveP400F2I]>;366def : WriteRes<WriteFClass32, [SiFiveP400F2I]>;367def : WriteRes<WriteFClass64, [SiFiveP400F2I]>;368def : WriteRes<WriteFCmp16, [SiFiveP400F2I]>;369def : WriteRes<WriteFCmp32, [SiFiveP400F2I]>;370def : WriteRes<WriteFCmp64, [SiFiveP400F2I]>;371def : WriteRes<WriteFMovI16ToF16, [SiFiveP400I2F]>;372def : WriteRes<WriteFMovF16ToI16, [SiFiveP400F2I]>;373def : WriteRes<WriteFMovI32ToF32, [SiFiveP400I2F]>;374def : WriteRes<WriteFMovF32ToI32, [SiFiveP400F2I]>;375def : WriteRes<WriteFMovI64ToF64, [SiFiveP400I2F]>;376def : WriteRes<WriteFMovF64ToI64, [SiFiveP400F2I]>;377}378 379// 6. Configuration-Setting Instructions380def : WriteRes<WriteVSETVLI, [SiFiveP400SYS]>;381def : WriteRes<WriteVSETIVLI, [SiFiveP400SYS]>;382def : WriteRes<WriteVSETVL, [SiFiveP400SYS]>;383 384// 7. Vector Loads and Stores385 386// Note that the latency of vector loads are measured by consuming the loaded387// value with vmv.x.s before subtracting the latency of vmv.x.s from the number.388foreach mx = SchedMxList in {389 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;390 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;391 let Latency = 8 in {392 let ReleaseAtCycles = [LMulLat] in {393 defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP400VLD], mx, IsWorstCase>;394 defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP400VLD], mx, IsWorstCase>;395 396 defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>;397 }398 399 // Mask load and store have a maximum EMUL of 1.400 let ReleaseAtCycles = [SiFiveP400GetLMulCycles<"M1">.c] in {401 defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase=!eq(mx, "M1")>;402 defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase=!eq(mx, "M1")>;403 }404 }405 foreach eew = [8, 16, 32, 64] in {406 let Latency = SiFiveP400StridedLdStLatency<mx, eew>.val,407 ReleaseAtCycles = [SiFiveP400GetVLMAX<mx, eew>.val] in {408 defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP400VLD], mx, IsWorstCase>;409 defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP400VLD], mx, IsWorstCase>;410 defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP400VLD], mx, IsWorstCase>;411 412 defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SiFiveP400VST], mx, IsWorstCase>;413 defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SiFiveP400VST], mx, IsWorstCase>;414 defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SiFiveP400VST], mx, IsWorstCase>;415 }416 }417}418 419foreach mx = SchedMxList in {420 foreach nf=2-8 in {421 foreach eew = [8, 16, 32, 64] in {422 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;423 defvar LMulLat = SiFiveP400SegmentedLdStCycles<mx, eew, nf>.c;424 let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {425 defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;426 defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;427 defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;428 defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;429 defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;430 }431 let Latency = !add(1, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {432 defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;433 defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;434 defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;435 defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;436 }437 }438 }439}440 441// Whole register move/load/store442foreach LMul = [1, 2, 4, 8] in {443 let Latency = 8, ReleaseAtCycles = [LMul] in {444 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP400VLD]>;445 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP400VST]>;446 }447 let Latency = 2, ReleaseAtCycles = [LMul] in {448 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP400VEXQ0]>;449 }450}451 452// 11. Vector Integer Arithmetic Instructions453foreach mx = SchedMxList in {454 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;455 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;456 let Latency = 2, ReleaseAtCycles = [LMulLat] in {457 defm "" : LMULWriteResMX<"WriteVIALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;458 defm "" : LMULWriteResMX<"WriteVIALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;459 defm "" : LMULWriteResMX<"WriteVIALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;460 defm "" : LMULWriteResMX<"WriteVExtV", [SiFiveP400VEXQ0], mx, IsWorstCase>;461 defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;462 defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;463 defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;464 defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP400VEXQ0], mx, IsWorstCase>;465 defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP400VEXQ0], mx, IsWorstCase>;466 defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP400VEXQ0], mx, IsWorstCase>;467 defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP400VEXQ0], mx, IsWorstCase>;468 defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;469 defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;470 defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFiveP400VEXQ0], mx, IsWorstCase>;471 defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFiveP400VEXQ0], mx, IsWorstCase>;472 defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFiveP400VEXQ0], mx, IsWorstCase>;473 defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFiveP400VEXQ0], mx, IsWorstCase>;474 defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFiveP400VEXQ0], mx, IsWorstCase>;475 defm "" : LMULWriteResMX<"WriteVIMovV", [SiFiveP400VEXQ0], mx, IsWorstCase>;476 defm "" : LMULWriteResMX<"WriteVIMovX", [SiFiveP400VEXQ0], mx, IsWorstCase>;477 defm "" : LMULWriteResMX<"WriteVIMovI", [SiFiveP400VEXQ0], mx, IsWorstCase>;478 }479 480 let Latency = !if(!lt(LMulLat, 2), 2, LMulLat), ReleaseAtCycles = [LMulLat] in {481 defm "" : LMULWriteResMX<"WriteVShiftV", [SiFiveP400VEXQ0], mx, IsWorstCase>;482 defm "" : LMULWriteResMX<"WriteVShiftX", [SiFiveP400VEXQ0], mx, IsWorstCase>;483 defm "" : LMULWriteResMX<"WriteVShiftI", [SiFiveP400VEXQ0], mx, IsWorstCase>;484 }485 486 let Latency = !if(!eq(mx, "M8"), 9, 6), ReleaseAtCycles = [LMulLat] in {487 defm "" : LMULWriteResMX<"WriteVIMulV", [SiFiveP400VEXQ0], mx, IsWorstCase>;488 defm "" : LMULWriteResMX<"WriteVIMulX", [SiFiveP400VEXQ0], mx, IsWorstCase>;489 defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFiveP400VEXQ0], mx, IsWorstCase>;490 defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFiveP400VEXQ0], mx, IsWorstCase>;491 }492}493// Widening494foreach mx = SchedMxListW in {495 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;496 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListW>.c;497 let Latency = 6, ReleaseAtCycles = [LMulLat] in {498 defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;499 defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;500 defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;501 defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFiveP400VEXQ0], mx, IsWorstCase>;502 defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFiveP400VEXQ0], mx, IsWorstCase>;503 defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFiveP400VEXQ0], mx, IsWorstCase>;504 defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFiveP400VEXQ0], mx, IsWorstCase>;505 }506}507 508// Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.509foreach mx = SchedMxList in {510 foreach sew = SchedSEWSet<mx>.val in {511 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;512 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;513 defvar DivMicroOpLat =514 !cond(!eq(sew, 8): 51, !eq(sew, 16): 45, !eq(sew, 32): 42,515 /* SEW=64 */ true: 72);516 defvar DivLatency = !mul(DivMicroOpLat, LMulLat);517 let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {518 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFiveP400VEXQ0, SiFiveP400VDiv], mx, sew, IsWorstCase>;519 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFiveP400VEXQ0, SiFiveP400VDiv], mx, sew, IsWorstCase>;520 }521 }522}523 524// Narrowing Shift and Clips525foreach mx = SchedMxListW in {526 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;527 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListW>.c;528 let Latency = 2, ReleaseAtCycles = [LMulLat] in {529 defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFiveP400VEXQ0], mx, IsWorstCase>;530 defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFiveP400VEXQ0], mx, IsWorstCase>;531 defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFiveP400VEXQ0], mx, IsWorstCase>;532 defm "" : LMULWriteResMX<"WriteVNClipV", [SiFiveP400VEXQ0], mx, IsWorstCase>;533 defm "" : LMULWriteResMX<"WriteVNClipX", [SiFiveP400VEXQ0], mx, IsWorstCase>;534 defm "" : LMULWriteResMX<"WriteVNClipI", [SiFiveP400VEXQ0], mx, IsWorstCase>;535 }536}537 538// 12. Vector Fixed-Point Arithmetic Instructions539foreach mx = SchedMxList in {540 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;541 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;542 let Latency = 6, ReleaseAtCycles = [LMulLat] in {543 defm "" : LMULWriteResMX<"WriteVSALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;544 defm "" : LMULWriteResMX<"WriteVSALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;545 defm "" : LMULWriteResMX<"WriteVSALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;546 defm "" : LMULWriteResMX<"WriteVAALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;547 defm "" : LMULWriteResMX<"WriteVAALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;548 defm "" : LMULWriteResMX<"WriteVSMulV", [SiFiveP400VEXQ0], mx, IsWorstCase>;549 defm "" : LMULWriteResMX<"WriteVSMulX", [SiFiveP400VEXQ0], mx, IsWorstCase>;550 defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFiveP400VEXQ0], mx, IsWorstCase>;551 defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFiveP400VEXQ0], mx, IsWorstCase>;552 defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFiveP400VEXQ0], mx, IsWorstCase>;553 }554}555 556// 13. Vector Floating-Point Instructions557foreach mx = SchedMxListF in {558 foreach sew = SchedSEWSet<mx, isF=1>.val in {559 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;560 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;561 let Latency = 6, ReleaseAtCycles = [LMulLat] in {562 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;563 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;564 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;565 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;566 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;567 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;568 }569 }570}571foreach mx = SchedMxListF in {572 foreach sew = SchedSEWSet<mx, isF=1>.val in {573 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;574 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;575 let Latency = 2, ReleaseAtCycles = [LMulLat] in {576 defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;577 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;578 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;579 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;580 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;581 }582 let Latency = 3, ReleaseAtCycles = [LMulLat] in583 defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;584 }585}586foreach mx = SchedMxList in {587 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;588 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;589 let Latency = 2, ReleaseAtCycles = [LMulLat] in {590 defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFiveP400VEXQ0], mx, IsWorstCase>;591 defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFiveP400VEXQ0], mx, IsWorstCase>;592 defm "" : LMULWriteResMX<"WriteVFClassV", [SiFiveP400VEXQ0], mx, IsWorstCase>;593 defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFiveP400VEXQ0], mx, IsWorstCase>;594 defm "" : LMULWriteResMX<"WriteVFMovV", [SiFiveP400VEXQ0], mx, IsWorstCase>;595 }596 let Latency = 3, ReleaseAtCycles = [LMulLat] in597 defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP400VEXQ0], mx, IsWorstCase>;598}599 600// Widening601foreach mx = SchedMxListW in {602 foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {603 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;604 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;605 let Latency = 3, ReleaseAtCycles = [LMulLat] in606 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;607 }608}609foreach mx = SchedMxListFW in {610 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;611 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListFW>.c;612 let Latency = 6, ReleaseAtCycles = [LMulLat] in613 defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP400VEXQ0], mx, IsWorstCase>;614}615foreach mx = SchedMxListFW in {616 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {617 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;618 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;619 let Latency = 6, ReleaseAtCycles = [LMulLat] in {620 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;621 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;622 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;623 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;624 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;625 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;626 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;627 }628 }629}630// Narrowing631foreach mx = SchedMxListW in {632 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;633 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListW>.c;634 let Latency = 3, ReleaseAtCycles = [LMulLat] in635 defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFiveP400VEXQ0], mx, IsWorstCase>;636}637foreach mx = SchedMxListFW in {638 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {639 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;640 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;641 let Latency = 3, ReleaseAtCycles = [LMulLat] in {642 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;643 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;644 }645 }646}647 648// Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.649foreach mx = SchedMxListF in {650 foreach sew = SchedSEWSet<mx, 1>.val in {651 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;652 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;653 defvar DivMicroOpLat =654 !cond(!eq(sew, 16): 29, !eq(sew, 32): 25, /* SEW=64 */ true: 37);655 defvar DivLatency = !mul(DivMicroOpLat, LMulLat);656 let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {657 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFiveP400VEXQ0, SiFiveP400VFloatDiv], mx, sew, IsWorstCase>;658 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFiveP400VEXQ0, SiFiveP400VFloatDiv], mx, sew, IsWorstCase>;659 defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFiveP400VEXQ0, SiFiveP400VFloatDiv], mx, sew, IsWorstCase>;660 }661 }662}663 664// 14. Vector Reduction Operations665foreach mx = SchedMxList in {666 foreach sew = SchedSEWSet<mx>.val in {667 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;668 669 // Simple reduction670 defvar SimpleC = SimpleVIReduceCycles<mx>;671 let Latency = SimpleC.latency, ReleaseAtCycles = [SimpleC.rthroughput] in672 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;673 674 // Advanced reduction675 defvar AdvancedC = AdvancedVIReduceCycles<sew, mx>;676 let Latency = AdvancedC.latency, ReleaseAtCycles = [AdvancedC.rthroughput] in677 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFiveP400VEXQ0],678 mx, sew, IsWorstCase>;679 }680}681 682foreach mx = SchedMxListWRed in {683 foreach sew = SchedSEWSet<mx, 0, 1>.val in {684 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;685 defvar SimpleC = SimpleVIReduceCycles<mx>;686 let Latency = SimpleC.latency, ReleaseAtCycles = [SimpleC.rthroughput] in {687 defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFiveP400VEXQ0],688 mx, sew, IsWorstCase>;689 }690 }691}692 693foreach mx = SchedMxListF in {694 foreach sew = SchedSEWSet<mx, 1>.val in {695 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;696 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;697 698 // Simple reduction.699 defvar BaseC = VFReduceBaseCycles<sew>.val;700 let Latency = !add(BaseC, !mul(6, !logtwo(LMulLat))), ReleaseAtCycles = [BaseC] in701 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFiveP400VEXQ0],702 mx, sew, IsWorstCase>;703 704 // Advanced reduction.705 defvar AdvancedC = AdvancedVFReduceCycles<sew, mx>;706 let Latency = AdvancedC.latency, ReleaseAtCycles = [AdvancedC.rthroughput] in707 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From",708 [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;709 710 defvar OrderedRedCycles = !mul(BaseC, LMulLat);711 let Latency = OrderedRedCycles, ReleaseAtCycles = [OrderedRedCycles] in712 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFiveP400VEXQ0],713 mx, sew, IsWorstCase>;714 }715}716 717foreach mx = SchedMxListFWRed in {718 foreach sew = SchedSEWSet<mx, 1, 1>.val in {719 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;720 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;721 let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {722 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFiveP400VEXQ0],723 mx, sew, IsWorstCase>;724 }725 726 defvar OrderedRedCycles = !mul(VFReduceBaseCycles<sew>.val, LMulLat);727 let Latency = OrderedRedCycles, ReleaseAtCycles = [OrderedRedCycles] in728 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFiveP400VEXQ0],729 mx, sew, IsWorstCase>;730 }731}732 733// 15. Vector Mask Instructions734foreach mx = SchedMxList in {735 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;736 let Latency = 2, ReleaseAtCycles = [1] in {737 defm "" : LMULWriteResMX<"WriteVMALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;738 defm "" : LMULWriteResMX<"WriteVMPopV", [SiFiveP400VEXQ0], mx, IsWorstCase>;739 defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFiveP400VEXQ0], mx, IsWorstCase>;740 defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFiveP400VEXQ0], mx, IsWorstCase>;741 }742 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;743 let Latency = 2, ReleaseAtCycles = [LMulLat] in {744 defm "" : LMULWriteResMX<"WriteVIotaV", [SiFiveP400VEXQ0], mx, IsWorstCase>;745 defm "" : LMULWriteResMX<"WriteVIdxV", [SiFiveP400VEXQ0], mx, IsWorstCase>;746 }747}748 749// 16. Vector Permutation Instructions750// Simple Slide751foreach mx = SchedMxList in {752 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;753 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;754 let Latency = 2, ReleaseAtCycles = [LMulLat] in {755 defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP400VEXQ0], mx, IsWorstCase>;756 }757 let Latency = 2, ReleaseAtCycles = [LMulLat] in {758 defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP400VEXQ0], mx, IsWorstCase>;759 defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP400VEXQ0], mx, IsWorstCase>;760 }761}762foreach mx = ["MF8", "MF4", "MF2", "M1"] in {763 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;764 let Latency = 2, ReleaseAtCycles = [1] in {765 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;766 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP400VEXQ0], mx, IsWorstCase>;767 }768}769 770// Complex Slide771foreach mx = ["M2", "M4", "M8"] in {772 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;773 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;774 775 defvar UpLatAndCycles = !add(8, LMulLat);776 let Latency = UpLatAndCycles, ReleaseAtCycles = [UpLatAndCycles] in {777 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;778 }779 defvar DownLatAndCycles = !add(8, !div(!mul(LMulLat, 3), 2));780 let Latency = DownLatAndCycles, ReleaseAtCycles = [DownLatAndCycles] in {781 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP400VEXQ0], mx, IsWorstCase>;782 }783}784 785let Latency = 2, ReleaseAtCycles = [2] in {786 def : WriteRes<WriteVMovXS, [SiFiveP400VEXQ0]>;787 def : WriteRes<WriteVMovSX, [SiFiveP400VEXQ0]>;788}789let Latency = 6, ReleaseAtCycles = [2] in {790 def : WriteRes<WriteVMovFS, [SiFiveP400VEXQ0]>;791 def : WriteRes<WriteVMovSF, [SiFiveP400VEXQ0]>;792}793 794// Simple Gather and Compress795foreach mx = ["MF8", "MF4", "MF2", "M1"] in {796 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;797 let Latency = 3, ReleaseAtCycles = [1] in {798 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP400VEXQ0], mx, IsWorstCase>;799 }800}801 802foreach mx = ["MF8", "MF4", "MF2", "M1"] in {803 foreach sew = SchedSEWSet<mx>.val in {804 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;805 let Latency = 3, ReleaseAtCycles = [1] in {806 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;807 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;808 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;809 }810 }811}812 813// Complex Gather and Compress814foreach mx = ["M2", "M4", "M8"] in {815 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;816 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;817 let Latency = 6, ReleaseAtCycles = [LMulLat] in {818 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP400VEXQ0], mx, IsWorstCase>;819 }820}821 822foreach mx = ["M2", "M4", "M8"] in {823 foreach sew = SchedSEWSet<mx>.val in {824 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;825 defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;826 let Latency = 6, ReleaseAtCycles = [!add(!mul(LMulLat, 2), 8)] in {827 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;828 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;829 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;830 }831 }832}833 834// Simple Vrgather.vi835foreach mx = SchedMxList in {836 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;837 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;838 let Latency = 3, ReleaseAtCycles = [LMulLat] in {839 defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFiveP400VEXQ0], mx, IsWorstCase>;840 }841}842 843// Vector Crypto844foreach mx = SchedMxList in {845 defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;846 defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;847 // Zvbb848 let Latency = 2, ReleaseAtCycles = [LMulLat] in {849 defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP400VEXQ0], mx, IsWorstCase>;850 defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP400VEXQ0], mx, IsWorstCase>;851 defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP400VEXQ0], mx, IsWorstCase>;852 defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP400VEXQ0], mx, IsWorstCase>;853 defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP400VEXQ0], mx, IsWorstCase>;854 defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP400VEXQ0], mx, IsWorstCase>;855 defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP400VEXQ0], mx, IsWorstCase>;856 }857 // Zvbc858 let Latency = 2, ReleaseAtCycles = [LMulLat] in {859 defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP400VEXQ0], mx, IsWorstCase>;860 defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP400VEXQ0], mx, IsWorstCase>;861 }862 // Zvkb863 // VANDN uses WriteVIALU[V|X|I]864 let Latency = 2, ReleaseAtCycles = [LMulLat] in {865 defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP400VEXQ0], mx, IsWorstCase>;866 defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP400VEXQ0], mx, IsWorstCase>;867 defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP400VEXQ0], mx, IsWorstCase>;868 defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP400VEXQ0], mx, IsWorstCase>;869 defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP400VEXQ0], mx, IsWorstCase>;870 }871 // Zvkg872 let Latency = 2, ReleaseAtCycles = [LMulLat] in {873 defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP400VEXQ0], mx, IsWorstCase>;874 defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP400VEXQ0], mx, IsWorstCase>;875 }876 // ZvknhaOrZvknhb877 let Latency = 3, ReleaseAtCycles = [LMulLat] in {878 defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP400VEXQ0], mx, IsWorstCase>;879 defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP400VEXQ0], mx, IsWorstCase>;880 defvar ZvknhSEWs = !listremove(SchedSEWSet<mx>.val, [8, 16]);881 // Largest SEW is the last element, assuming SchedSEWSet is sorted in ascending882 // order.883 defvar LargestZvknhSEW = !foldl(!head(ZvknhSEWs), ZvknhSEWs, last, curr, curr);884 foreach sew = ZvknhSEWs in {885 // The worst case for Zvknh[ab] is designated to the largest SEW and LMUL.886 defvar IsWorstCaseVSHA2MSV = !and(IsWorstCase, !eq(sew, LargestZvknhSEW));887 defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SiFiveP400VEXQ0], mx, sew,888 IsWorstCaseVSHA2MSV>;889 }890 }891 // Zvkned892 let Latency = 2, ReleaseAtCycles = [LMulLat] in {893 defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP400VEXQ0], mx, IsWorstCase>;894 defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP400VEXQ0], mx, IsWorstCase>;895 defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP400VEXQ0], mx, IsWorstCase>;896 defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP400VEXQ0], mx, IsWorstCase>;897 }898 // Zvksed899 let Latency = 3, ReleaseAtCycles = [SiFiveP400VSM3CCycles<mx>.c] in900 defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP400VEXQ0], mx, IsWorstCase>;901 let Latency = 6, ReleaseAtCycles = [LMulLat] in902 defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP400VEXQ0], mx, IsWorstCase>;903 let Latency = 3, ReleaseAtCycles = [LMulLat] in {904 defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP400VEXQ0], mx, IsWorstCase>;905 defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP400VEXQ0], mx, IsWorstCase>;906 }907}908 909// Others910def : WriteRes<WriteCSR, [SiFiveP400SYS]>;911def : WriteRes<WriteNop, []>;912def : WriteRes<WriteRdVLENB, [SiFiveP400SYS]>;913 914 915// FIXME: This could be better modeled by looking at the regclasses of the operands.916def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;917 918//===----------------------------------------------------------------------===//919// Bypass and advance920def : ReadAdvance<ReadJmp, 0>;921def : ReadAdvance<ReadJalr, 0>;922def : ReadAdvance<ReadCSR, 0>;923def : ReadAdvance<ReadStoreData, 0>;924def : ReadAdvance<ReadMemBase, 0>;925def : ReadAdvance<ReadIALU, 0>;926def : ReadAdvance<ReadIALU32, 0>;927def : ReadAdvance<ReadShiftImm, 0>;928def : ReadAdvance<ReadShiftImm32, 0>;929def : ReadAdvance<ReadShiftReg, 0>;930def : ReadAdvance<ReadShiftReg32, 0>;931def : ReadAdvance<ReadIDiv, 0>;932def : ReadAdvance<ReadIDiv32, 0>;933def : ReadAdvance<ReadIRem, 0>;934def : ReadAdvance<ReadIRem32, 0>;935def : ReadAdvance<ReadIMul, 0>;936def : ReadAdvance<ReadIMul32, 0>;937def : ReadAdvance<ReadAtomicWA, 0>;938def : ReadAdvance<ReadAtomicWD, 0>;939def : ReadAdvance<ReadAtomicDA, 0>;940def : ReadAdvance<ReadAtomicDD, 0>;941def : ReadAdvance<ReadAtomicLDW, 0>;942def : ReadAdvance<ReadAtomicLDD, 0>;943def : ReadAdvance<ReadAtomicSTW, 0>;944def : ReadAdvance<ReadAtomicSTD, 0>;945def : ReadAdvance<ReadFStoreData, 0>;946def : ReadAdvance<ReadFMemBase, 0>;947def : ReadAdvance<ReadFAdd16, 0>;948def : ReadAdvance<ReadFAdd32, 0>;949def : ReadAdvance<ReadFAdd64, 0>;950def : ReadAdvance<ReadFMul16, 0>;951def : ReadAdvance<ReadFMA16, 0>;952def : ReadAdvance<ReadFMA16Addend, 0>;953def : ReadAdvance<ReadFMul32, 0>;954def : ReadAdvance<ReadFMA32, 0>;955def : ReadAdvance<ReadFMA32Addend, 0>;956def : ReadAdvance<ReadFMul64, 0>;957def : ReadAdvance<ReadFMA64, 0>;958def : ReadAdvance<ReadFMA64Addend, 0>;959def : ReadAdvance<ReadFDiv16, 0>;960def : ReadAdvance<ReadFDiv32, 0>;961def : ReadAdvance<ReadFDiv64, 0>;962def : ReadAdvance<ReadFSqrt16, 0>;963def : ReadAdvance<ReadFSqrt32, 0>;964def : ReadAdvance<ReadFSqrt64, 0>;965def : ReadAdvance<ReadFCmp16, 0>;966def : ReadAdvance<ReadFCmp32, 0>;967def : ReadAdvance<ReadFCmp64, 0>;968def : ReadAdvance<ReadFSGNJ16, 0>;969def : ReadAdvance<ReadFSGNJ32, 0>;970def : ReadAdvance<ReadFSGNJ64, 0>;971def : ReadAdvance<ReadFMinMax16, 0>;972def : ReadAdvance<ReadFMinMax32, 0>;973def : ReadAdvance<ReadFMinMax64, 0>;974def : ReadAdvance<ReadFCvtF16ToI32, 0>;975def : ReadAdvance<ReadFCvtF16ToI64, 0>;976def : ReadAdvance<ReadFCvtF32ToI32, 0>;977def : ReadAdvance<ReadFCvtF32ToI64, 0>;978def : ReadAdvance<ReadFCvtF64ToI32, 0>;979def : ReadAdvance<ReadFCvtF64ToI64, 0>;980def : ReadAdvance<ReadFCvtI32ToF16, 0>;981def : ReadAdvance<ReadFCvtI32ToF32, 0>;982def : ReadAdvance<ReadFCvtI32ToF64, 0>;983def : ReadAdvance<ReadFCvtI64ToF16, 0>;984def : ReadAdvance<ReadFCvtI64ToF32, 0>;985def : ReadAdvance<ReadFCvtI64ToF64, 0>;986def : ReadAdvance<ReadFCvtF32ToF64, 0>;987def : ReadAdvance<ReadFCvtF64ToF32, 0>;988def : ReadAdvance<ReadFCvtF16ToF32, 0>;989def : ReadAdvance<ReadFCvtF32ToF16, 0>;990def : ReadAdvance<ReadFCvtF16ToF64, 0>;991def : ReadAdvance<ReadFCvtF64ToF16, 0>;992def : ReadAdvance<ReadFMovF16ToI16, 0>;993def : ReadAdvance<ReadFMovI16ToF16, 0>;994def : ReadAdvance<ReadFMovF32ToI32, 0>;995def : ReadAdvance<ReadFMovI32ToF32, 0>;996def : ReadAdvance<ReadFMovF64ToI64, 0>;997def : ReadAdvance<ReadFMovI64ToF64, 0>;998def : ReadAdvance<ReadFClass16, 0>;999def : ReadAdvance<ReadFClass32, 0>;1000def : ReadAdvance<ReadFClass64, 0>;1001 1002// Bitmanip1003def : ReadAdvance<ReadRotateImm, 0>;1004def : ReadAdvance<ReadRotateImm32, 0>;1005def : ReadAdvance<ReadRotateReg, 0>;1006def : ReadAdvance<ReadRotateReg32, 0>;1007def : ReadAdvance<ReadCLZ, 0>;1008def : ReadAdvance<ReadCLZ32, 0>;1009def : ReadAdvance<ReadCTZ, 0>;1010def : ReadAdvance<ReadCTZ32, 0>;1011def : ReadAdvance<ReadCPOP, 0>;1012def : ReadAdvance<ReadCPOP32, 0>;1013def : ReadAdvance<ReadORCB, 0>;1014def : ReadAdvance<ReadIMinMax, 0>;1015def : ReadAdvance<ReadREV8, 0>;1016def : ReadAdvance<ReadSHXADD, 0>;1017def : ReadAdvance<ReadSHXADD32, 0>;1018def : ReadAdvance<ReadSingleBit, 0>;1019def : ReadAdvance<ReadSingleBitImm, 0>;1020 1021// 6. Configuration-Setting Instructions1022def : ReadAdvance<ReadVSETVLI, 0>;1023def : ReadAdvance<ReadVSETVL, 0>;1024 1025// 7. Vector Loads and Stores1026def : ReadAdvance<ReadVLDX, 0>;1027def : ReadAdvance<ReadVSTX, 0>;1028defm "" : LMULReadAdvance<"ReadVSTEV", 0>;1029defm "" : LMULReadAdvance<"ReadVSTM", 0>;1030def : ReadAdvance<ReadVLDSX, 0>;1031def : ReadAdvance<ReadVSTSX, 0>;1032defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;1033defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;1034defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;1035defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;1036defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;1037defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;1038defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;1039defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;1040defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;1041defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;1042defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;1043defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;1044defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;1045defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;1046defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;1047defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;1048defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;1049defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;1050defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;1051defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;1052defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;1053defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;1054defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;1055defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;1056// LMUL Aware1057def : ReadAdvance<ReadVST1R, 0>;1058def : ReadAdvance<ReadVST2R, 0>;1059def : ReadAdvance<ReadVST4R, 0>;1060def : ReadAdvance<ReadVST8R, 0>;1061 1062// 12. Vector Integer Arithmetic Instructions1063defm : LMULReadAdvance<"ReadVIALUV", 0>;1064defm : LMULReadAdvance<"ReadVIALUX", 0>;1065defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;1066defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;1067defm : LMULReadAdvance<"ReadVExtV", 0>;1068defm : LMULReadAdvance<"ReadVICALUV", 0>;1069defm : LMULReadAdvance<"ReadVICALUX", 0>;1070defm : LMULReadAdvance<"ReadVShiftV", 0>;1071defm : LMULReadAdvance<"ReadVShiftX", 0>;1072defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;1073defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;1074defm : LMULReadAdvance<"ReadVICmpV", 0>;1075defm : LMULReadAdvance<"ReadVICmpX", 0>;1076defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;1077defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;1078defm : LMULReadAdvance<"ReadVIMulV", 0>;1079defm : LMULReadAdvance<"ReadVIMulX", 0>;1080defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;1081defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;1082defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;1083defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;1084defm : LMULReadAdvance<"ReadVIMulAddV", 0>;1085defm : LMULReadAdvance<"ReadVIMulAddX", 0>;1086defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;1087defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;1088defm : LMULReadAdvance<"ReadVIMergeV", 0>;1089defm : LMULReadAdvance<"ReadVIMergeX", 0>;1090defm : LMULReadAdvance<"ReadVIMovV", 0>;1091defm : LMULReadAdvance<"ReadVIMovX", 0>;1092 1093// 13. Vector Fixed-Point Arithmetic Instructions1094defm "" : LMULReadAdvance<"ReadVSALUV", 0>;1095defm "" : LMULReadAdvance<"ReadVSALUX", 0>;1096defm "" : LMULReadAdvance<"ReadVAALUV", 0>;1097defm "" : LMULReadAdvance<"ReadVAALUX", 0>;1098defm "" : LMULReadAdvance<"ReadVSMulV", 0>;1099defm "" : LMULReadAdvance<"ReadVSMulX", 0>;1100defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;1101defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;1102defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;1103defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;1104 1105// 14. Vector Floating-Point Instructions1106defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;1107defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;1108defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;1109defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;1110defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;1111defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;1112defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;1113defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;1114defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;1115defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;1116defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;1117defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;1118defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;1119defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;1120defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;1121defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;1122defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;1123defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;1124defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;1125defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;1126defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;1127defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;1128defm "" : LMULReadAdvance<"ReadVFClassV", 0>;1129defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;1130defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;1131defm "" : LMULReadAdvance<"ReadVFMovF", 0>;1132defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;1133defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;1134defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;1135defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;1136defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;1137defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;1138defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;1139defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;1140 1141// 15. Vector Reduction Operations1142def : ReadAdvance<ReadVIRedV, 0>;1143def : ReadAdvance<ReadVIRedV0, 0>;1144def : ReadAdvance<ReadVIWRedV, 0>;1145def : ReadAdvance<ReadVIWRedV0, 0>;1146def : ReadAdvance<ReadVFRedV, 0>;1147def : ReadAdvance<ReadVFRedV0, 0>;1148def : ReadAdvance<ReadVFRedOV, 0>;1149def : ReadAdvance<ReadVFRedOV0, 0>;1150def : ReadAdvance<ReadVFWRedV, 0>;1151def : ReadAdvance<ReadVFWRedV0, 0>;1152def : ReadAdvance<ReadVFWRedOV, 0>;1153def : ReadAdvance<ReadVFWRedOV0, 0>;1154 1155// 16. Vector Mask Instructions1156defm "" : LMULReadAdvance<"ReadVMALUV", 0>;1157defm "" : LMULReadAdvance<"ReadVMPopV", 0>;1158defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;1159defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;1160defm "" : LMULReadAdvance<"ReadVIotaV", 0>;1161 1162// 17. Vector Permutation Instructions1163def : ReadAdvance<ReadVMovXS, 0>;1164def : ReadAdvance<ReadVMovSX_V, 0>;1165def : ReadAdvance<ReadVMovSX_X, 0>;1166def : ReadAdvance<ReadVMovFS, 0>;1167def : ReadAdvance<ReadVMovSF_V, 0>;1168def : ReadAdvance<ReadVMovSF_F, 0>;1169defm "" : LMULReadAdvance<"ReadVISlideV", 0>;1170defm "" : LMULReadAdvance<"ReadVISlideX", 0>;1171defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;1172defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;1173defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;1174defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;1175defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;1176defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;1177defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;1178defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;1179defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;1180defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;1181// LMUL Aware1182def : ReadAdvance<ReadVMov1V, 0>;1183def : ReadAdvance<ReadVMov2V, 0>;1184def : ReadAdvance<ReadVMov4V, 0>;1185def : ReadAdvance<ReadVMov8V, 0>;1186 1187// Others1188def : ReadAdvance<ReadVMask, 0>;1189def : ReadAdvance<ReadVPassthru_WorstCase, 0>;1190foreach mx = SchedMxList in {1191 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;1192 foreach sew = SchedSEWSet<mx>.val in1193 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;1194}1195 1196// Vector Crypto Extensions1197// Zvbb1198defm "" : LMULReadAdvance<"ReadVBREVV", 0>;1199defm "" : LMULReadAdvance<"ReadVCLZV", 0>;1200defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;1201defm "" : LMULReadAdvance<"ReadVCTZV", 0>;1202defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;1203defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;1204// Zvbc1205defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;1206defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;1207// Zvkb1208// VANDN uses ReadVIALU[V|X|I]1209defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;1210defm "" : LMULReadAdvance<"ReadVREV8V", 0>;1211defm "" : LMULReadAdvance<"ReadVRotV", 0>;1212defm "" : LMULReadAdvance<"ReadVRotX", 0>;1213// Zvkg1214defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;1215defm "" : LMULReadAdvance<"ReadVGMULV", 0>;1216// Zvknha or Zvknhb1217defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;1218defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;1219defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>;1220// Zvkned1221defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;1222defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;1223defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;1224defm "" : LMULReadAdvance<"ReadVAESZV", 0>;1225// Zvksed1226defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;1227defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;1228// Zbksh1229defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;1230defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;1231 1232//===----------------------------------------------------------------------===//1233// Unsupported extensions1234defm : UnsupportedSchedQ;1235defm : UnsupportedSchedZabha;1236defm : UnsupportedSchedZbc;1237defm : UnsupportedSchedZbkb;1238defm : UnsupportedSchedZbkx;1239defm : UnsupportedSchedSFB;1240defm : UnsupportedSchedZfa;1241defm : UnsupportedSchedXsf;1242}1243