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1//==- RISCVSchedSiFiveP500.td - SiFiveP500 Scheduling Defs ---*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10 11def SiFiveP500Model : SchedMachineModel {12 let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.13 let MicroOpBufferSize = 96; // Max micro-ops that can be buffered.14 let LoadLatency = 4; // Cycles for loads to access the cache.15 let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.16 let CompleteModel = false;17}18 19// The SiFiveP500 microarchitecure has 7 pipelines:20// Three pipelines for integer operations.21// Two pipelines for FPU operations.22// One pipeline for Load operations.23// One pipeline for Store operations.24let SchedModel = SiFiveP500Model in {25 26def SiFiveP500IEXQ0 : ProcResource<1>;27def SiFiveP500IEXQ1 : ProcResource<1>;28def SiFiveP500IEXQ2 : ProcResource<1>;29def SiFiveP500FEXQ0 : ProcResource<1>;30def SiFiveP500FEXQ1 : ProcResource<1>;31def SiFiveP500Load : ProcResource<1>;32def SiFiveP500Store : ProcResource<1>;33 34def SiFiveP500IntArith : ProcResGroup<[SiFiveP500IEXQ0, SiFiveP500IEXQ1, SiFiveP500IEXQ2]>;35defvar SiFiveP500Branch = SiFiveP500IEXQ0;36defvar SiFiveP500SYS = SiFiveP500IEXQ1;37defvar SiFiveP500CMOV = SiFiveP500IEXQ1;38defvar SiFiveP500MulI2F = SiFiveP500IEXQ2;39def SiFiveP500Div : ProcResource<1>;40 41def SiFiveP500FloatArith : ProcResGroup<[SiFiveP500FEXQ0, SiFiveP500FEXQ1]>;42defvar SiFiveP500F2I = SiFiveP500FEXQ0;43def SiFiveP500FloatDiv : ProcResource<1>;44 45let Latency = 1 in {46// Integer arithmetic and logic47def : WriteRes<WriteIALU, [SiFiveP500IntArith]>;48def : WriteRes<WriteIALU32, [SiFiveP500IntArith]>;49def : WriteRes<WriteShiftImm, [SiFiveP500IntArith]>;50def : WriteRes<WriteShiftImm32, [SiFiveP500IntArith]>;51def : WriteRes<WriteShiftReg, [SiFiveP500IntArith]>;52def : WriteRes<WriteShiftReg32, [SiFiveP500IntArith]>;53// Branching54def : WriteRes<WriteJmp, [SiFiveP500Branch]>;55def : WriteRes<WriteJal, [SiFiveP500Branch]>;56def : WriteRes<WriteJalr, [SiFiveP500Branch]>;57}58 59// CMOV60def P500WriteCMOV : SchedWriteRes<[SiFiveP500Branch, SiFiveP500CMOV]> {61 let Latency = 2;62 let NumMicroOps = 2;63}64def : InstRW<[P500WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;65 66let Latency = 3 in {67// Integer multiplication68def : WriteRes<WriteIMul, [SiFiveP500MulI2F]>;69def : WriteRes<WriteIMul32, [SiFiveP500MulI2F]>;70// cpop[w] look exactly like multiply.71def : WriteRes<WriteCPOP, [SiFiveP500MulI2F]>;72def : WriteRes<WriteCPOP32, [SiFiveP500MulI2F]>;73}74 75// Integer division76def : WriteRes<WriteIDiv, [SiFiveP500MulI2F, SiFiveP500Div]> {77 let Latency = 35;78 let ReleaseAtCycles = [1, 34];79}80def : WriteRes<WriteIDiv32, [SiFiveP500MulI2F, SiFiveP500Div]> {81 let Latency = 20;82 let ReleaseAtCycles = [1, 19];83}84 85// Integer remainder86def : WriteRes<WriteIRem, [SiFiveP500MulI2F, SiFiveP500Div]> {87 let Latency = 35;88 let ReleaseAtCycles = [1, 34];89}90def : WriteRes<WriteIRem32, [SiFiveP500MulI2F, SiFiveP500Div]> {91 let Latency = 20;92 let ReleaseAtCycles = [1, 19];93}94 95let Latency = 1 in {96// Bitmanip97def : WriteRes<WriteRotateImm, [SiFiveP500IntArith]>;98def : WriteRes<WriteRotateImm32, [SiFiveP500IntArith]>;99def : WriteRes<WriteRotateReg, [SiFiveP500IntArith]>;100def : WriteRes<WriteRotateReg32, [SiFiveP500IntArith]>;101 102def : WriteRes<WriteCLZ, [SiFiveP500IntArith]>;103def : WriteRes<WriteCLZ32, [SiFiveP500IntArith]>;104def : WriteRes<WriteCTZ, [SiFiveP500IntArith]>;105def : WriteRes<WriteCTZ32, [SiFiveP500IntArith]>;106 107def : WriteRes<WriteORCB, [SiFiveP500IntArith]>;108def : WriteRes<WriteIMinMax, [SiFiveP500IntArith]>;109 110def : WriteRes<WriteREV8, [SiFiveP500IntArith]>;111 112def : WriteRes<WriteSHXADD, [SiFiveP500IntArith]>;113def : WriteRes<WriteSHXADD32, [SiFiveP500IntArith]>;114}115 116// Memory117let Latency = 1 in {118def : WriteRes<WriteSTB, [SiFiveP500Store]>;119def : WriteRes<WriteSTH, [SiFiveP500Store]>;120def : WriteRes<WriteSTW, [SiFiveP500Store]>;121def : WriteRes<WriteSTD, [SiFiveP500Store]>;122def : WriteRes<WriteFST16, [SiFiveP500Store]>;123def : WriteRes<WriteFST32, [SiFiveP500Store]>;124def : WriteRes<WriteFST64, [SiFiveP500Store]>;125}126let Latency = 4 in {127def : WriteRes<WriteLDB, [SiFiveP500Load]>;128def : WriteRes<WriteLDH, [SiFiveP500Load]>;129}130let Latency = 4 in {131def : WriteRes<WriteLDW, [SiFiveP500Load]>;132def : WriteRes<WriteLDD, [SiFiveP500Load]>;133}134 135let Latency = 5 in {136def : WriteRes<WriteFLD16, [SiFiveP500Load]>;137def : WriteRes<WriteFLD32, [SiFiveP500Load]>;138def : WriteRes<WriteFLD64, [SiFiveP500Load]>;139}140 141// Atomic memory142let Latency = 3 in {143def : WriteRes<WriteAtomicSTW, [SiFiveP500Store]>;144def : WriteRes<WriteAtomicSTD, [SiFiveP500Store]>;145def : WriteRes<WriteAtomicW, [SiFiveP500Load]>;146def : WriteRes<WriteAtomicD, [SiFiveP500Load]>;147def : WriteRes<WriteAtomicLDW, [SiFiveP500Load]>;148def : WriteRes<WriteAtomicLDD, [SiFiveP500Load]>;149}150 151// Floating point152let Latency = 4 in {153def : WriteRes<WriteFAdd16, [SiFiveP500FloatArith]>;154def : WriteRes<WriteFAdd32, [SiFiveP500FloatArith]>;155def : WriteRes<WriteFAdd64, [SiFiveP500FloatArith]>;156 157def : WriteRes<WriteFMul16, [SiFiveP500FloatArith]>;158def : WriteRes<WriteFMul32, [SiFiveP500FloatArith]>;159def : WriteRes<WriteFMul64, [SiFiveP500FloatArith]>;160 161def : WriteRes<WriteFMA16, [SiFiveP500FloatArith]>;162def : WriteRes<WriteFMA32, [SiFiveP500FloatArith]>;163def : WriteRes<WriteFMA64, [SiFiveP500FloatArith]>;164}165 166let Latency = 2 in {167def : WriteRes<WriteFSGNJ16, [SiFiveP500FloatArith]>;168def : WriteRes<WriteFSGNJ32, [SiFiveP500FloatArith]>;169def : WriteRes<WriteFSGNJ64, [SiFiveP500FloatArith]>;170 171def : WriteRes<WriteFMinMax16, [SiFiveP500FloatArith]>;172def : WriteRes<WriteFMinMax32, [SiFiveP500FloatArith]>;173def : WriteRes<WriteFMinMax64, [SiFiveP500FloatArith]>;174}175 176// Half precision.177def : WriteRes<WriteFDiv16, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {178 let Latency = 19;179 let ReleaseAtCycles = [1, 18];180}181def : WriteRes<WriteFSqrt16, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {182 let Latency = 18;183 let ReleaseAtCycles = [1, 17];184}185 186// Single precision.187def : WriteRes<WriteFDiv32, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {188 let Latency = 19;189 let ReleaseAtCycles = [1, 18];190}191def : WriteRes<WriteFSqrt32, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {192 let Latency = 18;193 let ReleaseAtCycles = [1, 17];194}195 196// Double precision197def : WriteRes<WriteFDiv64, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {198 let Latency = 33;199 let ReleaseAtCycles = [1, 32];200}201def : WriteRes<WriteFSqrt64, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {202 let Latency = 33;203 let ReleaseAtCycles = [1, 32];204}205 206// Conversions207let Latency = 2 in {208def : WriteRes<WriteFCvtI32ToF16, [SiFiveP500MulI2F]>;209def : WriteRes<WriteFCvtI32ToF32, [SiFiveP500MulI2F]>;210def : WriteRes<WriteFCvtI32ToF64, [SiFiveP500MulI2F]>;211def : WriteRes<WriteFCvtI64ToF16, [SiFiveP500MulI2F]>;212def : WriteRes<WriteFCvtI64ToF32, [SiFiveP500MulI2F]>;213def : WriteRes<WriteFCvtI64ToF64, [SiFiveP500MulI2F]>;214def : WriteRes<WriteFCvtF16ToI32, [SiFiveP500F2I]>;215def : WriteRes<WriteFCvtF16ToI64, [SiFiveP500F2I]>;216def : WriteRes<WriteFCvtF16ToF32, [SiFiveP500FloatArith]>;217def : WriteRes<WriteFCvtF16ToF64, [SiFiveP500FloatArith]>;218def : WriteRes<WriteFCvtF32ToI32, [SiFiveP500F2I]>;219def : WriteRes<WriteFCvtF32ToI64, [SiFiveP500F2I]>;220def : WriteRes<WriteFCvtF32ToF16, [SiFiveP500FloatArith]>;221def : WriteRes<WriteFCvtF32ToF64, [SiFiveP500FloatArith]>;222def : WriteRes<WriteFCvtF64ToI32, [SiFiveP500F2I]>;223def : WriteRes<WriteFCvtF64ToI64, [SiFiveP500F2I]>;224def : WriteRes<WriteFCvtF64ToF16, [SiFiveP500FloatArith]>;225def : WriteRes<WriteFCvtF64ToF32, [SiFiveP500FloatArith]>;226 227def : WriteRes<WriteFClass16, [SiFiveP500F2I]>;228def : WriteRes<WriteFClass32, [SiFiveP500F2I]>;229def : WriteRes<WriteFClass64, [SiFiveP500F2I]>;230def : WriteRes<WriteFCmp16, [SiFiveP500F2I]>;231def : WriteRes<WriteFCmp32, [SiFiveP500F2I]>;232def : WriteRes<WriteFCmp64, [SiFiveP500F2I]>;233def : WriteRes<WriteFMovI16ToF16, [SiFiveP500MulI2F]>;234def : WriteRes<WriteFMovF16ToI16, [SiFiveP500F2I]>;235def : WriteRes<WriteFMovI32ToF32, [SiFiveP500MulI2F]>;236def : WriteRes<WriteFMovF32ToI32, [SiFiveP500F2I]>;237def : WriteRes<WriteFMovI64ToF64, [SiFiveP500MulI2F]>;238def : WriteRes<WriteFMovF64ToI64, [SiFiveP500F2I]>;239}240 241// Others242def : WriteRes<WriteCSR, [SiFiveP500SYS]>;243def : WriteRes<WriteNop, []>;244 245// FIXME: This could be better modeled by looking at the regclasses of the operands.246def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;247 248//===----------------------------------------------------------------------===//249// Bypass and advance250def : ReadAdvance<ReadJmp, 0>;251def : ReadAdvance<ReadJalr, 0>;252def : ReadAdvance<ReadCSR, 0>;253def : ReadAdvance<ReadStoreData, 0>;254def : ReadAdvance<ReadMemBase, 0>;255def : ReadAdvance<ReadIALU, 0>;256def : ReadAdvance<ReadIALU32, 0>;257def : ReadAdvance<ReadShiftImm, 0>;258def : ReadAdvance<ReadShiftImm32, 0>;259def : ReadAdvance<ReadShiftReg, 0>;260def : ReadAdvance<ReadShiftReg32, 0>;261def : ReadAdvance<ReadIDiv, 0>;262def : ReadAdvance<ReadIDiv32, 0>;263def : ReadAdvance<ReadIRem, 0>;264def : ReadAdvance<ReadIRem32, 0>;265def : ReadAdvance<ReadIMul, 0>;266def : ReadAdvance<ReadIMul32, 0>;267def : ReadAdvance<ReadAtomicWA, 0>;268def : ReadAdvance<ReadAtomicWD, 0>;269def : ReadAdvance<ReadAtomicDA, 0>;270def : ReadAdvance<ReadAtomicDD, 0>;271def : ReadAdvance<ReadAtomicLDW, 0>;272def : ReadAdvance<ReadAtomicLDD, 0>;273def : ReadAdvance<ReadAtomicSTW, 0>;274def : ReadAdvance<ReadAtomicSTD, 0>;275def : ReadAdvance<ReadFStoreData, 0>;276def : ReadAdvance<ReadFMemBase, 0>;277def : ReadAdvance<ReadFAdd16, 0>;278def : ReadAdvance<ReadFAdd32, 0>;279def : ReadAdvance<ReadFAdd64, 0>;280def : ReadAdvance<ReadFMul16, 0>;281def : ReadAdvance<ReadFMA16, 0>;282def : ReadAdvance<ReadFMA16Addend, 0>;283def : ReadAdvance<ReadFMul32, 0>;284def : ReadAdvance<ReadFMA32, 0>;285def : ReadAdvance<ReadFMA32Addend, 0>;286def : ReadAdvance<ReadFMul64, 0>;287def : ReadAdvance<ReadFMA64, 0>;288def : ReadAdvance<ReadFMA64Addend, 0>;289def : ReadAdvance<ReadFDiv16, 0>;290def : ReadAdvance<ReadFDiv32, 0>;291def : ReadAdvance<ReadFDiv64, 0>;292def : ReadAdvance<ReadFSqrt16, 0>;293def : ReadAdvance<ReadFSqrt32, 0>;294def : ReadAdvance<ReadFSqrt64, 0>;295def : ReadAdvance<ReadFCmp16, 0>;296def : ReadAdvance<ReadFCmp32, 0>;297def : ReadAdvance<ReadFCmp64, 0>;298def : ReadAdvance<ReadFSGNJ16, 0>;299def : ReadAdvance<ReadFSGNJ32, 0>;300def : ReadAdvance<ReadFSGNJ64, 0>;301def : ReadAdvance<ReadFMinMax16, 0>;302def : ReadAdvance<ReadFMinMax32, 0>;303def : ReadAdvance<ReadFMinMax64, 0>;304def : ReadAdvance<ReadFCvtF16ToI32, 0>;305def : ReadAdvance<ReadFCvtF16ToI64, 0>;306def : ReadAdvance<ReadFCvtF32ToI32, 0>;307def : ReadAdvance<ReadFCvtF32ToI64, 0>;308def : ReadAdvance<ReadFCvtF64ToI32, 0>;309def : ReadAdvance<ReadFCvtF64ToI64, 0>;310def : ReadAdvance<ReadFCvtI32ToF16, 0>;311def : ReadAdvance<ReadFCvtI32ToF32, 0>;312def : ReadAdvance<ReadFCvtI32ToF64, 0>;313def : ReadAdvance<ReadFCvtI64ToF16, 0>;314def : ReadAdvance<ReadFCvtI64ToF32, 0>;315def : ReadAdvance<ReadFCvtI64ToF64, 0>;316def : ReadAdvance<ReadFCvtF32ToF64, 0>;317def : ReadAdvance<ReadFCvtF64ToF32, 0>;318def : ReadAdvance<ReadFCvtF16ToF32, 0>;319def : ReadAdvance<ReadFCvtF32ToF16, 0>;320def : ReadAdvance<ReadFCvtF16ToF64, 0>;321def : ReadAdvance<ReadFCvtF64ToF16, 0>;322def : ReadAdvance<ReadFMovF16ToI16, 0>;323def : ReadAdvance<ReadFMovI16ToF16, 0>;324def : ReadAdvance<ReadFMovF32ToI32, 0>;325def : ReadAdvance<ReadFMovI32ToF32, 0>;326def : ReadAdvance<ReadFMovF64ToI64, 0>;327def : ReadAdvance<ReadFMovI64ToF64, 0>;328def : ReadAdvance<ReadFClass16, 0>;329def : ReadAdvance<ReadFClass32, 0>;330def : ReadAdvance<ReadFClass64, 0>;331 332// Bitmanip333def : ReadAdvance<ReadRotateImm, 0>;334def : ReadAdvance<ReadRotateImm32, 0>;335def : ReadAdvance<ReadRotateReg, 0>;336def : ReadAdvance<ReadRotateReg32, 0>;337def : ReadAdvance<ReadCLZ, 0>;338def : ReadAdvance<ReadCLZ32, 0>;339def : ReadAdvance<ReadCTZ, 0>;340def : ReadAdvance<ReadCTZ32, 0>;341def : ReadAdvance<ReadCPOP, 0>;342def : ReadAdvance<ReadCPOP32, 0>;343def : ReadAdvance<ReadORCB, 0>;344def : ReadAdvance<ReadIMinMax, 0>;345def : ReadAdvance<ReadREV8, 0>;346def : ReadAdvance<ReadSHXADD, 0>;347def : ReadAdvance<ReadSHXADD32, 0>;348 349//===----------------------------------------------------------------------===//350// Unsupported extensions351defm : UnsupportedSchedQ;352defm : UnsupportedSchedV;353defm : UnsupportedSchedZabha;354defm : UnsupportedSchedZbc;355defm : UnsupportedSchedZbs;356defm : UnsupportedSchedZbkb;357defm : UnsupportedSchedZbkx;358defm : UnsupportedSchedSFB;359defm : UnsupportedSchedZfa;360defm : UnsupportedSchedZvk;361defm : UnsupportedSchedXsf;362}363