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1//==- RISCVSchedSiFiveP600.td - SiFiveP600 Scheduling Defs ---*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10 11/// c is true if mx has the worst case behavior compared to LMULs in MxList.12/// On the SiFiveP600, the worst case LMUL is the Largest LMUL13/// and the worst case sew is the smallest SEW for that LMUL.14class SiFiveP600IsWorstCaseMX<string mx, list<string> MxList> {15 string LLMUL = LargestLMUL<MxList>.r;16 bit c = !eq(mx, LLMUL);17}18 19class SiFiveP600IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {20 string LLMUL = LargestLMUL<MxList>.r;21 int SSEW = SmallestSEW<mx, isF>.r;22 bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));23}24 25defvar SiFiveP600VLEN = 128;26 27// 1 Micro-Op per cycle.28class SiFiveP600GetLMulCycles<string mx> {29 int c = !cond(30 !eq(mx, "M1") : 1,31 !eq(mx, "M2") : 2,32 !eq(mx, "M4") : 4,33 !eq(mx, "M8") : 8,34 !eq(mx, "MF2") : 1,35 !eq(mx, "MF4") : 1,36 !eq(mx, "MF8") : 137 );38}39 40class SiFiveP600GetVLMAX<string mx, int sew> {41 defvar LMUL = SiFiveP600GetLMulCycles<mx>.c;42 int val = !cond(43 !eq(mx, "MF2") : !div(!div(SiFiveP600VLEN, 2), sew),44 !eq(mx, "MF4") : !div(!div(SiFiveP600VLEN, 4), sew),45 !eq(mx, "MF8") : !div(!div(SiFiveP600VLEN, 8), sew),46 true: !div(!mul(SiFiveP600VLEN, LMUL), sew)47 );48}49 50class SiFiveP600StridedLdStLatency<string mx, int sew> {51 defvar VL = SiFiveP400GetVLMAX<mx, sew>.val;52 int val = !cond(53 !eq(VL, 2): 13,54 !eq(VL, 4): 18,55 !eq(VL, 8): 22,56 !eq(VL, 16): 30,57 // VL=32,64,12858 true: !sub(VL, 2)59 );60}61 62// Latency for segmented loads and stores are calculated as vl * nf.63class SiFiveP600SegmentedLdStCycles<string mx, int sew, int nf> {64 int c = !mul(SiFiveP600GetVLMAX<mx, sew>.val, nf);65}66 67class SiFiveP600VSM3CCycles<string mx> {68 // c = ceil(LMUL / 2)69 int c = !cond(!eq(mx, "M2") : 1,70 !eq(mx, "M4") : 2,71 !eq(mx, "M8") : 4,72 true : 1);73}74 75class SiFiveP600RVVMultiplier<string mx> {76 int c = !if(!eq(mx, "M8"), 2, 1);77}78 79// ======================================================================80// The latency and occupancy data in this section are primarily evaluated81// from llvm-exegesis.82// ======================================================================83 84class SiFiveP600VCryptoLatency<string mx> {85 int c = !cond(86 !eq(mx, "M4"): 4,87 !eq(mx, "M8"): 8,88 true: 289 );90}91 92class SiFiveP600VFMinMaxReduction<string mx, int sew> {93 defvar E64Lat = !cond(94 !eq(mx, "M1") : 4,95 !eq(mx, "M2") : 6,96 !eq(mx, "M4") : 8,97 !eq(mx, "M8") : 10,98 true: 299 );100 101 defvar E64Cycles = !cond(102 !eq(mx, "M1") : 3,103 !eq(mx, "M2") : 4,104 !eq(mx, "M4") : 5,105 !eq(mx, "M8") : 6,106 true: 2107 );108 109 int latency = !if(!eq(sew, 64), E64Lat, !add(E64Lat, 2));110 int cycles = !if(!eq(sew, 64), E64Cycles, !add(E64Cycles, 1));111}112 113class SiFiveP600VFUnorderedReduction<string mx, int sew> {114 defvar E64Lat = !cond(115 !eq(mx, "M1") : 6,116 !eq(mx, "M2") : 12,117 !eq(mx, "M4") : 18,118 !eq(mx, "M8") : 24,119 true: 2120 );121 122 defvar E32Cycles = !cond(123 !eq(mx, "M1") : 10,124 !eq(mx, "M2") : 10,125 !eq(mx, "M4") : 11,126 !eq(mx, "M8") : 11,127 true: 6128 );129 130 int latency = !if(!eq(sew, 64), E64Lat, !add(E64Lat, 4));131 int cycles = !if(!eq(sew, 64), 6, E32Cycles);132}133 134class SiFiveP600VFWidenUnorderedReduction<string mx> {135 int latency = !cond(136 !eq(mx, "M1") : 10,137 !eq(mx, "M2") : 18,138 !eq(mx, "M4") : 24,139 !eq(mx, "M8") : 30,140 true: 6141 );142}143 144class SiFiveP600VFOrderedReduction<string mx, int sew> {145 defvar Base = !if(!eq(sew, 64), 6, 10);146 int c = !cond(147 !eq(mx, "M1") : Base,148 !eq(mx, "M2") : !mul(Base, 2),149 !eq(mx, "M4") : !mul(Base, 4),150 !eq(mx, "M8") : !mul(Base, 8),151 true: 6152 );153}154 155class SiFiveP600VIReductionLatency<string mx> {156 int c = !cond(157 !eq(mx, "M2") : 4,158 !eq(mx, "M4") : 8,159 !eq(mx, "M8") : 16,160 // M1 and lower161 true: 2162 );163}164 165class SiFiveP600VIMinMaxReductionLatency<string mx, int sew> {166 // +-----+-----+-----+-----+----+167 // | | E64 | E32 | E16 | E8 |168 // +-----+-----+-----+-----+----+169 // | MF8 | X | X | X | 4 |170 // +-----+-----+-----+-----+----+171 // | MF4 | X | X | 4 | 6 |172 // +-----+-----+-----+-----+----+173 // | MF2 | X | 4 | 6 | 8 |174 // +-----+-----+-----+-----+----+175 // | M1 | 4 | 6 | 8 | 10 |176 // +-----+-----+-----+-----+----+177 // | M2 | 6 | 8 | 10 | 12 |178 // +-----+-----+-----+-----+----+179 // | M4 | 8 | 10 | 12 | 14 |180 // +-----+-----+-----+-----+----+181 // | M8 | 10 | 12 | 14 | 16 |182 // +-----+-----+-----+-----+----+183 defvar BaseIndex = !cond(184 !eq(sew, 64): 0,185 !eq(sew, 32): 1,186 !eq(sew, 16): 2,187 !eq(sew, 8): 3188 );189 190 defvar Latencies = [4, 6, 8, 10, 12, 14, 16];191 192 int c = !cond(193 !eq(mx, "M1") : Latencies[BaseIndex],194 !eq(mx, "M2") : Latencies[!add(BaseIndex, 1)],195 !eq(mx, "M4") : Latencies[!add(BaseIndex, 2)],196 !eq(mx, "M8") : Latencies[!add(BaseIndex, 3)],197 // Fractional198 !eq(mx, "MF2"): Latencies[!sub(BaseIndex, 1)],199 !eq(mx, "MF4"): Latencies[!sub(BaseIndex, 2)],200 !eq(mx, "MF8"): Latencies[!sub(BaseIndex, 3)],201 );202}203 204class SiFiveP600VIMinMaxReductionCycles<string mx, int sew> {205 // +-----+-----+-----+-----+----+206 // | | E64 | E32 | E16 | E8 |207 // +-----+-----+-----+-----+----+208 // | MF8 | X | X | X | 3 |209 // +-----+-----+-----+-----+----+210 // | MF4 | X | X | 3 | 5 |211 // +-----+-----+-----+-----+----+212 // | MF2 | X | 3 | 5 | 6 |213 // +-----+-----+-----+-----+----+214 // | M1 | 3 | 4 | 6 | 8 |215 // +-----+-----+-----+-----+----+216 // | M2 | 4 | 5 | 8 | 9 |217 // +-----+-----+-----+-----+----+218 // | M4 | 5 | 6 | 10 | 11 |219 // +-----+-----+-----+-----+----+220 // | M8 | 7 | 8 | 9 | 11 |221 // +-----+-----+-----+-----+----+222 defvar Index = !cond(223 !eq(sew, 64): 0,224 !eq(sew, 32): 1,225 !eq(sew, 16): 2,226 !eq(sew, 8): 3227 );228 229 defvar Cycles = [230 [0, 0, 0, 3],231 [0, 0, 3, 5],232 [0, 3, 5, 6],233 [3, 4, 6, 8],234 [4, 5, 8, 9],235 [5, 6, 10, 11],236 [7, 8, 9, 11]237 ];238 239 int c = !cond(240 !eq(mx, "MF8"): Cycles[0][Index],241 !eq(mx, "MF4"): Cycles[1][Index],242 !eq(mx, "MF2"): Cycles[2][Index],243 !eq(mx, "M1"): Cycles[3][Index],244 !eq(mx, "M2"): Cycles[4][Index],245 !eq(mx, "M4"): Cycles[5][Index],246 !eq(mx, "M8"): Cycles[6][Index],247 );248}249 250class SiFiveP600VSlide1<string mx> {251 int c = !cond(252 !eq(mx, "M2") : 3,253 !eq(mx, "M4") : 4,254 !eq(mx, "M8") : 8,255 // M1 and lower256 true: 2257 );258}259 260class SiFiveP600VSlideI<string mx> {261 int c = !cond(262 !eq(mx, "M2") : 4,263 !eq(mx, "M4") : 6,264 !eq(mx, "M8") : 8,265 // M1 and lower266 true: 2267 );268}269 270class SiFiveP600VSlideXComplex<string mx, bit isUp = false> {271 int latency = !cond(272 !eq(mx, "M2") : 11,273 !eq(mx, "M4") : 14,274 !eq(mx, "M8") : 20275 );276 277 int cycles = !cond(278 !eq(mx, "M2") : !if(isUp, 10, 11),279 !eq(mx, "M4") : !if(isUp, 12, 14),280 !eq(mx, "M8") : !if(isUp, 16, 20)281 );282}283 284class SiFiveP600VPermutationComplex<string mx> {285 int c = !cond(286 !eq(mx, "M2") : 12,287 !eq(mx, "M4") : 16,288 !eq(mx, "M8") : 24289 );290}291 292class SiFiveP600VSHA2MSCycles<string mx, int sew> {293 int c = !cond(294 !eq(mx, "M2") : !if(!eq(sew, 32), 2, 3),295 !eq(mx, "M4") : !if(!eq(sew, 32), 4, 6),296 !eq(mx, "M8") : !if(!eq(sew, 32), 8, 12),297 true: 1298 );299}300 301// SiFiveP600 machine model for scheduling and other instruction cost heuristics.302def SiFiveP600Model : SchedMachineModel {303 let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.304 let MicroOpBufferSize = 192; // Max micro-ops that can be buffered.305 let LoadLatency = 4; // Cycles for loads to access the cache.306 let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.307 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,308 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,309 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,310 HasVendorXSfvqmaccqoq];311 let CompleteModel = false;312}313 314let SchedModel = SiFiveP600Model in {315 316def SiFiveP600IEXQ0 : ProcResource<1>;317def SiFiveP600IEXQ1 : ProcResource<1>;318def SiFiveP600IEXQ2 : ProcResource<1>;319def SiFiveP600IEXQ3 : ProcResource<1>;320def SiFiveP600FEXQ0 : ProcResource<1>;321def SiFiveP600FEXQ1 : ProcResource<1>;322 323// Two Load/Store ports that can issue either two loads, two stores, or one load324// and one store (P550 has one load and one separate store pipe).325def SiFiveP600LDST : ProcResource<2>;326 327// 4-wide pipeline with 4 ALU pipes.328def SiFiveP600IntArith : ProcResGroup<[SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3]>;329defvar SiFiveP600SYS = SiFiveP600IEXQ0;330defvar SiFiveP600CMOV = SiFiveP600IEXQ0;331defvar SiFiveP600MulI2F = SiFiveP600IEXQ1;332def SiFiveP600Branch : ProcResGroup<[SiFiveP600IEXQ2, SiFiveP600IEXQ3]>;333def SiFiveP600Div : ProcResource<1>;334 335def SiFiveP600FloatArith : ProcResGroup<[SiFiveP600FEXQ0, SiFiveP600FEXQ1]>;336defvar SiFiveP600F2I = SiFiveP600FEXQ0;337def SiFiveP600FloatDiv : ProcResource<1>;338 339// Vector pipeline340// VEXQ0 handle Mask, Simple Slide instructions,341// VEXQ1 handle Complex Slide, Permutation, Reductions, Divide instructions.342// Other vector instructions can be done in VEXQ0 and VEXQ1.343def SiFiveP600VEXQ0 : ProcResource<1>;344def SiFiveP600VEXQ1 : ProcResource<1>;345def SiFiveP600VectorArith : ProcResGroup<[SiFiveP600VEXQ0, SiFiveP600VEXQ1]>;346 347// Only VEXQ0 has mask unit.348defvar SiFiveP600VectorMask = SiFiveP600VEXQ0;349// Only VEXQ0 has vector crypto.350defvar SiFiveP600VectorCrypto = SiFiveP600VEXQ0;351 352def SiFiveP600VLD : ProcResource<1>;353def SiFiveP600VST : ProcResource<1>;354def SiFiveP600VDiv : ProcResource<1>;355def SiFiveP600VFloatDiv : ProcResource<1>;356 357// Integer arithmetic and logic358def : WriteRes<WriteIALU, [SiFiveP600IntArith]>;359def : WriteRes<WriteIALU32, [SiFiveP600IntArith]>;360def : WriteRes<WriteShiftImm, [SiFiveP600IntArith]>;361def : WriteRes<WriteShiftImm32, [SiFiveP600IntArith]>;362def : WriteRes<WriteShiftReg, [SiFiveP600IntArith]>;363def : WriteRes<WriteShiftReg32, [SiFiveP600IntArith]>;364// Branching365def : WriteRes<WriteJmp, [SiFiveP600Branch]>;366def : WriteRes<WriteJal, [SiFiveP600Branch]>;367def : WriteRes<WriteJalr, [SiFiveP600Branch]>;368 369// CMOV370def P600WriteCMOV : SchedWriteRes<[SiFiveP600Branch, SiFiveP600CMOV]> {371 let Latency = 2;372 let NumMicroOps = 2;373}374def : InstRW<[P600WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;375 376let Latency = 2 in {377// Integer multiplication378def : WriteRes<WriteIMul, [SiFiveP600MulI2F]>;379def : WriteRes<WriteIMul32, [SiFiveP600MulI2F]>;380// cpop[w] look exactly like multiply.381def : WriteRes<WriteCPOP, [SiFiveP600MulI2F]>;382def : WriteRes<WriteCPOP32, [SiFiveP600MulI2F]>;383}384 385// Integer division386def : WriteRes<WriteIDiv, [SiFiveP600MulI2F, SiFiveP600Div]> {387 let Latency = 35;388 let ReleaseAtCycles = [1, 34];389}390def : WriteRes<WriteIDiv32, [SiFiveP600MulI2F, SiFiveP600Div]> {391 let Latency = 20;392 let ReleaseAtCycles = [1, 19];393}394 395// Integer remainder396def : WriteRes<WriteIRem, [SiFiveP600MulI2F, SiFiveP600Div]> {397 let Latency = 35;398 let ReleaseAtCycles = [1, 34];399}400def : WriteRes<WriteIRem32, [SiFiveP600MulI2F, SiFiveP600Div]> {401 let Latency = 20;402 let ReleaseAtCycles = [1, 19];403}404 405// Bitmanip406def : WriteRes<WriteRotateImm, [SiFiveP600IntArith]>;407def : WriteRes<WriteRotateImm32, [SiFiveP600IntArith]>;408def : WriteRes<WriteRotateReg, [SiFiveP600IntArith]>;409def : WriteRes<WriteRotateReg32, [SiFiveP600IntArith]>;410 411def : WriteRes<WriteCLZ, [SiFiveP600IntArith]>;412def : WriteRes<WriteCLZ32, [SiFiveP600IntArith]>;413def : WriteRes<WriteCTZ, [SiFiveP600IntArith]>;414def : WriteRes<WriteCTZ32, [SiFiveP600IntArith]>;415 416def : WriteRes<WriteORCB, [SiFiveP600IntArith]>;417def : WriteRes<WriteIMinMax, [SiFiveP600IntArith]>;418 419def : WriteRes<WriteREV8, [SiFiveP600IntArith]>;420 421def : WriteRes<WriteSHXADD, [SiFiveP600IntArith]>;422def : WriteRes<WriteSHXADD32, [SiFiveP600IntArith]>;423 424def : WriteRes<WriteSingleBit, [SiFiveP600IntArith]>;425def : WriteRes<WriteSingleBitImm, [SiFiveP600IntArith]>;426def : WriteRes<WriteBEXT, [SiFiveP600IntArith]>;427def : WriteRes<WriteBEXTI, [SiFiveP600IntArith]>;428 429// Memory430def : WriteRes<WriteSTB, [SiFiveP600LDST]>;431def : WriteRes<WriteSTH, [SiFiveP600LDST]>;432def : WriteRes<WriteSTW, [SiFiveP600LDST]>;433def : WriteRes<WriteSTD, [SiFiveP600LDST]>;434def : WriteRes<WriteFST16, [SiFiveP600LDST]>;435def : WriteRes<WriteFST32, [SiFiveP600LDST]>;436def : WriteRes<WriteFST64, [SiFiveP600LDST]>;437 438let Latency = 4 in {439def : WriteRes<WriteLDB, [SiFiveP600LDST]>;440def : WriteRes<WriteLDH, [SiFiveP600LDST]>;441}442let Latency = 4 in {443def : WriteRes<WriteLDW, [SiFiveP600LDST]>;444def : WriteRes<WriteLDD, [SiFiveP600LDST]>;445}446 447let Latency = 5 in {448def : WriteRes<WriteFLD16, [SiFiveP600LDST]>;449def : WriteRes<WriteFLD32, [SiFiveP600LDST]>;450def : WriteRes<WriteFLD64, [SiFiveP600LDST]>;451}452 453// Atomic memory454let Latency = 3 in {455def : WriteRes<WriteAtomicSTW, [SiFiveP600LDST]>;456def : WriteRes<WriteAtomicSTD, [SiFiveP600LDST]>;457def : WriteRes<WriteAtomicW, [SiFiveP600LDST]>;458def : WriteRes<WriteAtomicD, [SiFiveP600LDST]>;459def : WriteRes<WriteAtomicLDW, [SiFiveP600LDST]>;460def : WriteRes<WriteAtomicLDD, [SiFiveP600LDST]>;461}462 463// Floating point464let Latency = 2 in {465def : WriteRes<WriteFAdd16, [SiFiveP600FloatArith]>;466def : WriteRes<WriteFAdd32, [SiFiveP600FloatArith]>;467def : WriteRes<WriteFAdd64, [SiFiveP600FloatArith]>;468}469let Latency = 3 in {470def : WriteRes<WriteFMul16, [SiFiveP600FloatArith]>;471def : WriteRes<WriteFMul32, [SiFiveP600FloatArith]>;472def : WriteRes<WriteFMul64, [SiFiveP600FloatArith]>;473}474let Latency = 4 in {475def : WriteRes<WriteFMA16, [SiFiveP600FloatArith]>;476def : WriteRes<WriteFMA32, [SiFiveP600FloatArith]>;477def : WriteRes<WriteFMA64, [SiFiveP600FloatArith]>;478}479 480let Latency = 2 in {481def : WriteRes<WriteFSGNJ16, [SiFiveP600FloatArith]>;482def : WriteRes<WriteFSGNJ32, [SiFiveP600FloatArith]>;483def : WriteRes<WriteFSGNJ64, [SiFiveP600FloatArith]>;484 485def : WriteRes<WriteFMinMax16, [SiFiveP600FloatArith]>;486def : WriteRes<WriteFMinMax32, [SiFiveP600FloatArith]>;487def : WriteRes<WriteFMinMax64, [SiFiveP600FloatArith]>;488}489 490// Half precision.491def : WriteRes<WriteFDiv16, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {492 let Latency = 4;493 let ReleaseAtCycles = [1, 4];494}495def : WriteRes<WriteFSqrt16, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {496 let Latency = 18;497 let ReleaseAtCycles = [1, 17];498}499 500// Single precision.501def : WriteRes<WriteFDiv32, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {502 let Latency = 6;503 let ReleaseAtCycles = [1, 6];504}505def : WriteRes<WriteFSqrt32, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {506 let Latency = 18;507 let ReleaseAtCycles = [1, 17];508}509 510// Double precision511def : WriteRes<WriteFDiv64, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {512 let Latency = 11;513 let ReleaseAtCycles = [1, 11];514}515def : WriteRes<WriteFSqrt64, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {516 let Latency = 33;517 let ReleaseAtCycles = [1, 32];518}519 520// Conversions521let Latency = 2 in {522def : WriteRes<WriteFCvtI32ToF16, [SiFiveP600MulI2F]>;523def : WriteRes<WriteFCvtI32ToF32, [SiFiveP600MulI2F]>;524def : WriteRes<WriteFCvtI32ToF64, [SiFiveP600MulI2F]>;525def : WriteRes<WriteFCvtI64ToF16, [SiFiveP600MulI2F]>;526def : WriteRes<WriteFCvtI64ToF32, [SiFiveP600MulI2F]>;527def : WriteRes<WriteFCvtI64ToF64, [SiFiveP600MulI2F]>;528def : WriteRes<WriteFCvtF16ToI32, [SiFiveP600F2I]>;529def : WriteRes<WriteFCvtF16ToI64, [SiFiveP600F2I]>;530def : WriteRes<WriteFCvtF16ToF32, [SiFiveP600FloatArith]>;531def : WriteRes<WriteFCvtF16ToF64, [SiFiveP600FloatArith]>;532def : WriteRes<WriteFCvtF32ToI32, [SiFiveP600F2I]>;533def : WriteRes<WriteFCvtF32ToI64, [SiFiveP600F2I]>;534def : WriteRes<WriteFCvtF32ToF16, [SiFiveP600FloatArith]>;535def : WriteRes<WriteFCvtF32ToF64, [SiFiveP600FloatArith]>;536def : WriteRes<WriteFCvtF64ToI32, [SiFiveP600F2I]>;537def : WriteRes<WriteFCvtF64ToI64, [SiFiveP600F2I]>;538def : WriteRes<WriteFCvtF64ToF16, [SiFiveP600FloatArith]>;539def : WriteRes<WriteFCvtF64ToF32, [SiFiveP600FloatArith]>;540 541def : WriteRes<WriteFClass16, [SiFiveP600F2I]>;542def : WriteRes<WriteFClass32, [SiFiveP600F2I]>;543def : WriteRes<WriteFClass64, [SiFiveP600F2I]>;544def : WriteRes<WriteFCmp16, [SiFiveP600F2I]>;545def : WriteRes<WriteFCmp32, [SiFiveP600F2I]>;546def : WriteRes<WriteFCmp64, [SiFiveP600F2I]>;547def : WriteRes<WriteFMovI16ToF16, [SiFiveP600MulI2F]>;548def : WriteRes<WriteFMovF16ToI16, [SiFiveP600F2I]>;549def : WriteRes<WriteFMovI32ToF32, [SiFiveP600MulI2F]>;550def : WriteRes<WriteFMovF32ToI32, [SiFiveP600F2I]>;551def : WriteRes<WriteFMovI64ToF64, [SiFiveP600MulI2F]>;552def : WriteRes<WriteFMovF64ToI64, [SiFiveP600F2I]>;553}554 555// 6. Configuration-Setting Instructions556def : WriteRes<WriteVSETVLI, [SiFiveP600SYS]>;557def : WriteRes<WriteVSETIVLI, [SiFiveP600SYS]>;558def : WriteRes<WriteVSETVL, [SiFiveP600SYS]>;559 560// 7. Vector Loads and Stores561 562// Note that the latency of vector loads are measured by consuming the loaded563// value with vmv.x.s before subtracting the latency of vmv.x.s from the number.564foreach mx = SchedMxList in {565 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;566 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;567 let Latency = 8 in {568 let ReleaseAtCycles = [LMulLat] in {569 defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP600VLD], mx, IsWorstCase>;570 defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP600VLD], mx, IsWorstCase>;571 572 defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP600VST], mx, IsWorstCase>;573 }574 575 // Mask load and store have a maximum EMUL of 1.576 let ReleaseAtCycles = [SiFiveP600GetLMulCycles<"M1">.c] in {577 defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP600VLD], mx, IsWorstCase=!eq(mx,"M1")>;578 defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP600VST], mx, IsWorstCase=!eq(mx,"M1")>;579 }580 }581 foreach eew = [8, 16, 32, 64] in {582 let Latency = SiFiveP600StridedLdStLatency<mx, eew>.val,583 ReleaseAtCycles = [SiFiveP600GetVLMAX<mx, eew>.val] in {584 defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP600VLD], mx, IsWorstCase>;585 defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP600VLD], mx, IsWorstCase>;586 defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP600VLD], mx, IsWorstCase>;587 588 defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SiFiveP600VST], mx, IsWorstCase>;589 defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SiFiveP600VST], mx, IsWorstCase>;590 defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SiFiveP600VST], mx, IsWorstCase>;591 }592 }593}594 595foreach mx = SchedMxList in {596 foreach nf=2-8 in {597 foreach eew = [8, 16, 32, 64] in {598 defvar LMulLat = SiFiveP600SegmentedLdStCycles<mx, eew, nf>.c;599 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;600 let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {601 defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;602 defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;603 defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;604 defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;605 defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;606 }607 let Latency = !add(1, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {608 defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFiveP600VST], mx, IsWorstCase>;609 defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFiveP600VST], mx, IsWorstCase>;610 defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFiveP600VST], mx, IsWorstCase>;611 defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFiveP600VST], mx, IsWorstCase>;612 }613 }614 }615}616 617// Whole register move/load/store618foreach LMul = [1, 2, 4, 8] in {619 let Latency = 8, ReleaseAtCycles = [LMul] in {620 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP600VLD]>;621 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP600VST]>;622 }623 let Latency = 2, ReleaseAtCycles = [LMul] in {624 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP600VectorArith]>;625 }626}627 628// 11. Vector Integer Arithmetic Instructions629foreach mx = SchedMxList in {630 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;631 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;632 let Latency = 2, ReleaseAtCycles = [LMulLat] in {633 defm "" : LMULWriteResMX<"WriteVExtV", [SiFiveP600VectorArith], mx, IsWorstCase>;634 defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP600VectorMask], mx, IsWorstCase>;635 defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP600VectorMask], mx, IsWorstCase>;636 defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP600VectorMask], mx, IsWorstCase>;637 }638 let ReleaseAtCycles = [LMulLat] in {639 let Latency = 6 in {640 defm "" : LMULWriteResMX<"WriteVIMulV", [SiFiveP600VectorArith], mx, IsWorstCase>;641 defm "" : LMULWriteResMX<"WriteVIMulX", [SiFiveP600VectorArith], mx, IsWorstCase>;642 defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFiveP600VectorArith], mx, IsWorstCase>;643 defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFiveP600VectorArith], mx, IsWorstCase>;644 }645 646 let Latency = !mul(2, SiFiveP600RVVMultiplier<mx>.c) in {647 defm "" : LMULWriteResMX<"WriteVIALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;648 defm "" : LMULWriteResMX<"WriteVIALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;649 defm "" : LMULWriteResMX<"WriteVIALUI", [SiFiveP600VectorArith], mx, IsWorstCase>;650 defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;651 defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;652 defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP600VectorArith], mx, IsWorstCase>;653 defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP600VectorMask], mx, IsWorstCase>;654 defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP600VectorMask], mx, IsWorstCase>;655 defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP600VectorMask], mx, IsWorstCase>;656 defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFiveP600VectorArith], mx, IsWorstCase>;657 defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFiveP600VectorArith], mx, IsWorstCase>;658 defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFiveP600VectorArith], mx, IsWorstCase>;659 defm "" : LMULWriteResMX<"WriteVIMovX", [SiFiveP600VectorArith], mx, IsWorstCase>;660 defm "" : LMULWriteResMX<"WriteVIMovI", [SiFiveP600VectorArith], mx, IsWorstCase>;661 defm "" : LMULWriteResMX<"WriteVShiftI", [SiFiveP600VectorArith], mx, IsWorstCase>;662 defm "" : LMULWriteResMX<"WriteVShiftV", [SiFiveP600VectorArith], mx, IsWorstCase>;663 defm "" : LMULWriteResMX<"WriteVShiftX", [SiFiveP600VectorArith], mx, IsWorstCase>;664 defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFiveP600VectorArith], mx, IsWorstCase>;665 defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFiveP600VectorArith], mx, IsWorstCase>;666 defm "" : LMULWriteResMX<"WriteVIMovV", [SiFiveP600VectorArith], mx, IsWorstCase>;667 }668 }669}670// Widening671foreach mx = SchedMxListW in {672 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;673 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListW>.c;674 let Latency = 6, ReleaseAtCycles = [LMulLat] in {675 defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;676 defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;677 defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFiveP600VectorArith], mx, IsWorstCase>;678 defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFiveP600VectorArith], mx, IsWorstCase>;679 defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFiveP600VectorArith], mx, IsWorstCase>;680 defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFiveP600VectorArith], mx, IsWorstCase>;681 defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFiveP600VectorArith], mx, IsWorstCase>;682 683 // Special case for variants with widen operands.684 let ReleaseAtCycles = [!mul(LMulLat, 2)] in685 def P600WriteVIWALUWidenOp_ # mx : SchedWriteRes<[SiFiveP600VectorArith]>;686 }687 688 defvar P600VIWALUBaseSchedRW = [!cast<SchedWrite>("P600WriteVIWALUWidenOp_" # mx),689 !cast<SchedRead>("ReadVPassthru_" # mx),690 !cast<SchedRead>("ReadVIALUV_" # mx),691 !cast<SchedRead>("ReadVIALUV_" # mx)];692 693 def : InstRW<P600VIWALUBaseSchedRW,694 (instregex "^PseudoVW(ADD|SUB)[U]?_W(V|X)_" # mx # "$")>;695 def : InstRW<P600VIWALUBaseSchedRW[0,2,3],696 (instregex "^PseudoVW(ADD|SUB)[U]?_WV_" # mx # "_TIED$")>;697 698 def : InstRW<!listconcat(P600VIWALUBaseSchedRW, [!cast<SchedRead>("ReadVMask")]),699 (instregex "^PseudoVW(ADD|SUB)[U]?_W(V|X)_" # mx # "_MASK$")>;700 def : InstRW<!listconcat(P600VIWALUBaseSchedRW[0,1,3], [!cast<SchedRead>("ReadVMask")]),701 (instregex "^PseudoVW(ADD|SUB)[U]?_WV_" # mx # "_MASK_TIED$")>;702}703 704// Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.705foreach mx = SchedMxList in {706 foreach sew = SchedSEWSet<mx>.val in {707 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;708 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;709 defvar DivMicroOpLat =710 !cond(!eq(sew, 8): 51, !eq(sew, 16): 45, !eq(sew, 32): 42,711 /* SEW=64 */ true: 72);712 defvar DivLatency = !mul(DivMicroOpLat, LMulLat);713 let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {714 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFiveP600VEXQ1, SiFiveP600VDiv], mx, sew, IsWorstCase>;715 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFiveP600VEXQ1, SiFiveP600VDiv], mx, sew, IsWorstCase>;716 }717 }718}719 720// Narrowing Shift and Clips721foreach mx = SchedMxListW in {722 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;723 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListW>.c;724 let Latency = 2, ReleaseAtCycles = [LMulLat] in {725 defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFiveP600VectorArith], mx, IsWorstCase>;726 defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFiveP600VectorArith], mx, IsWorstCase>;727 defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFiveP600VectorArith], mx, IsWorstCase>;728 defm "" : LMULWriteResMX<"WriteVNClipV", [SiFiveP600VectorArith], mx, IsWorstCase>;729 defm "" : LMULWriteResMX<"WriteVNClipX", [SiFiveP600VectorArith], mx, IsWorstCase>;730 defm "" : LMULWriteResMX<"WriteVNClipI", [SiFiveP600VectorArith], mx, IsWorstCase>;731 }732}733 734// 12. Vector Fixed-Point Arithmetic Instructions735foreach mx = SchedMxList in {736 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;737 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;738 let Latency = 6, ReleaseAtCycles = [LMulLat] in {739 defm "" : LMULWriteResMX<"WriteVSALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;740 defm "" : LMULWriteResMX<"WriteVSALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;741 defm "" : LMULWriteResMX<"WriteVSALUI", [SiFiveP600VectorArith], mx, IsWorstCase>;742 defm "" : LMULWriteResMX<"WriteVAALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;743 defm "" : LMULWriteResMX<"WriteVAALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;744 defm "" : LMULWriteResMX<"WriteVSMulV", [SiFiveP600VectorArith], mx, IsWorstCase>;745 defm "" : LMULWriteResMX<"WriteVSMulX", [SiFiveP600VectorArith], mx, IsWorstCase>;746 defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFiveP600VectorArith], mx, IsWorstCase>;747 defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFiveP600VectorArith], mx, IsWorstCase>;748 defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFiveP600VectorArith], mx, IsWorstCase>;749 }750}751 752// 13. Vector Floating-Point Instructions753foreach mx = SchedMxListF in {754 foreach sew = SchedSEWSet<mx, isF=1>.val in {755 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;756 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;757 let Latency = 6, ReleaseAtCycles = [LMulLat] in {758 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;759 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;760 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;761 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;762 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;763 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;764 }765 }766}767foreach mx = SchedMxListF in {768 foreach sew = SchedSEWSet<mx, isF=1>.val in {769 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;770 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;771 let Latency = !mul(2, SiFiveP600RVVMultiplier<mx>.c), ReleaseAtCycles = [LMulLat] in {772 defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;773 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;774 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;775 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;776 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;777 }778 let Latency = !if(!eq(mx, "M8"), 4, 3), ReleaseAtCycles = [!if(!eq(LMulLat, 1), 2, LMulLat)] in779 defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;780 }781}782foreach mx = SchedMxList in {783 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;784 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;785 let Latency = !if(!eq(mx, "M8"), 4, 3), ReleaseAtCycles = [!if(!eq(LMulLat, 1), 2, LMulLat)] in786 defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;787 let Latency = 2, ReleaseAtCycles = [LMulLat] in {788 defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFiveP600VectorMask], mx, IsWorstCase>;789 defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFiveP600VectorMask], mx, IsWorstCase>;790 }791 let Latency = !mul(2, SiFiveP600RVVMultiplier<mx>.c),792 ReleaseAtCycles = [!if(!eq(LMulLat, 1), 2, LMulLat)] in {793 defm "" : LMULWriteResMX<"WriteVFClassV", [SiFiveP600VectorArith], mx, IsWorstCase>;794 defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFiveP600VectorArith], mx, IsWorstCase>;795 defm "" : LMULWriteResMX<"WriteVFMovV", [SiFiveP600VectorArith], mx, IsWorstCase>;796 }797}798 799// Widening800foreach mx = SchedMxListW in {801 foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {802 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;803 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;804 let Latency = 3, ReleaseAtCycles = [LMulLat] in805 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;806 }807}808foreach mx = SchedMxListFW in {809 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;810 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListFW>.c;811 let Latency = 6, ReleaseAtCycles = [LMulLat] in812 defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;813}814foreach mx = SchedMxListFW in {815 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {816 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;817 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;818 let Latency = 6, ReleaseAtCycles = [LMulLat] in {819 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;820 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;821 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;822 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;823 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;824 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;825 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;826 827 // Special case for variants with widen operands.828 let ReleaseAtCycles = [!mul(LMulLat, 2)] in829 def P600WriteVFWALUWidenOp_ # mx # _E # sew : SchedWriteRes<[SiFiveP600VectorArith]>;830 }831 832 defvar P600VFWALUBaseSchedRW = [!cast<SchedWrite>("P600WriteVFWALUWidenOp_" # mx # "_E" # sew),833 !cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew),834 !cast<SchedRead>("ReadVFWALUV_" # mx # "_E" # sew)];835 836 def : InstRW<!listconcat(P600VFWALUBaseSchedRW, [!cast<SchedRead>("ReadVFWALUV_" # mx # "_E" # sew)]),837 (instregex "^PseudoVFW(ADD|SUB)_WV_" # mx # "_E" # sew # "$")>;838 def : InstRW<[P600VFWALUBaseSchedRW[0], P600VFWALUBaseSchedRW[2], !cast<SchedRead>("ReadVFWALUV_" # mx # "_E" # sew)],839 (instregex "^PseudoVFW(ADD|SUB)_WV_" # mx # "_E" # sew # "_TIED$")>;840 841 def : InstRW<!listconcat(P600VFWALUBaseSchedRW, [!cast<SchedRead>("ReadVFWALUF_" # mx # "_E" # sew)]),842 (instregex "^PseudoVFW(ADD|SUB)_WFPR" # sew # "_" # mx # "_E" # sew # "$")>;843 844 def : InstRW<!listconcat(P600VFWALUBaseSchedRW, [!cast<SchedRead>("ReadVFWALUV_" # mx # "_E" # sew), !cast<SchedRead>("ReadVMask")]),845 (instregex "^PseudoVFW(ADD|SUB)_WV_" # mx # "_E" # sew # "_MASK$")>;846 def : InstRW<[P600VFWALUBaseSchedRW[0], P600VFWALUBaseSchedRW[1], !cast<SchedRead>("ReadVFWALUV_" # mx # "_E" # sew), !cast<SchedRead>("ReadVMask")],847 (instregex "^PseudoVFW(ADD|SUB)_WV_" # mx # "_E" # sew # "_MASK_TIED$")>;848 849 def : InstRW<!listconcat(P600VFWALUBaseSchedRW, [!cast<SchedRead>("ReadVFWALUF_" # mx # "_E" # sew), !cast<SchedRead>("ReadVMask")]),850 (instregex "^PseudoVFW(ADD|SUB)_WFPR" # sew # "_" # mx # "_E" # sew # "_MASK$")>;851 }852}853// Narrowing854foreach mx = SchedMxListW in {855 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;856 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListW>.c;857 let Latency = 3, ReleaseAtCycles = [LMulLat] in {858 defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;859 }860}861foreach mx = SchedMxListFW in {862 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {863 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;864 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;865 let Latency = 3, ReleaseAtCycles = [!if(!eq(LMulLat, 1), 2, LMulLat)] in {866 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;867 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;868 }869 }870}871 872// Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.873foreach mx = SchedMxListF in {874 foreach sew = SchedSEWSet<mx, 1>.val in {875 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;876 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;877 defvar DivMicroOpLat =878 !cond(!eq(sew, 16): 29, !eq(sew, 32): 25, /* SEW=64 */ true: 37);879 defvar DivLatency = !mul(DivMicroOpLat, LMulLat);880 let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {881 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFiveP600VEXQ1, SiFiveP600VFloatDiv], mx, sew, IsWorstCase>;882 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFiveP600VEXQ1, SiFiveP600VFloatDiv], mx, sew, IsWorstCase>;883 defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFiveP600VEXQ1, SiFiveP600VFloatDiv], mx, sew, IsWorstCase>;884 }885 }886}887 888// 14. Vector Reduction Operations889foreach mx = SchedMxList in {890 foreach sew = SchedSEWSet<mx>.val in {891 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;892 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;893 894 let ReleaseAtCycles = [LMulLat] in {895 let Latency = SiFiveP600VIReductionLatency<mx>.c in896 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFiveP600VEXQ1],897 mx, sew, IsWorstCase>;898 899 let Latency = SiFiveP600VIMinMaxReductionLatency<mx, sew>.c,900 ReleaseAtCycles = [SiFiveP600VIMinMaxReductionCycles<mx, sew>.c] in901 defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFiveP600VEXQ1],902 mx, sew, IsWorstCase>;903 }904 }905}906 907foreach mx = SchedMxListWRed in {908 foreach sew = SchedSEWSet<mx, 0, 1>.val in {909 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;910 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;911 let Latency = SiFiveP600VIReductionLatency<mx>.c, ReleaseAtCycles = [LMulLat] in {912 defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFiveP600VEXQ1],913 mx, sew, IsWorstCase>;914 }915 }916}917 918foreach mx = SchedMxListF in {919 foreach sew = SchedSEWSet<mx, 1>.val in {920 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;921 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;922 let Latency = SiFiveP600VFMinMaxReduction<mx, sew>.latency,923 ReleaseAtCycles = [SiFiveP600VFMinMaxReduction<mx, sew>.cycles] in924 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From",925 [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;926 927 let Latency = SiFiveP600VFUnorderedReduction<mx, sew>.latency,928 ReleaseAtCycles = [SiFiveP600VFUnorderedReduction<mx, sew>.cycles] in929 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFiveP600VEXQ1],930 mx, sew, IsWorstCase>;931 932 let Latency = SiFiveP600VFOrderedReduction<mx, sew>.c,933 ReleaseAtCycles = [SiFiveP600VFOrderedReduction<mx, sew>.c] in934 defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFiveP600VEXQ1],935 mx, sew, IsWorstCase>;936 }937}938 939foreach mx = SchedMxListFWRed in {940 foreach sew = SchedSEWSet<mx, 1, 1>.val in {941 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;942 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;943 let Latency = SiFiveP600VFWidenUnorderedReduction<mx>.latency,944 ReleaseAtCycles = [6] in945 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFiveP600VEXQ1],946 mx, sew, IsWorstCase>;947 948 let Latency = SiFiveP600VFOrderedReduction<mx, sew>.c,949 ReleaseAtCycles = [SiFiveP600VFOrderedReduction<mx, sew>.c] in950 defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFiveP600VEXQ1],951 mx, sew, IsWorstCase>;952 }953}954 955// 15. Vector Mask Instructions956foreach mx = SchedMxList in {957 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;958 let Latency = 2 in {959 defm "" : LMULWriteResMX<"WriteVMALUV", [SiFiveP600VectorMask], mx, IsWorstCase>;960 defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFiveP600VectorMask], mx, IsWorstCase>;961 962 let ReleaseAtCycles = [2] in {963 defm "" : LMULWriteResMX<"WriteVMPopV", [SiFiveP600VectorMask], mx, IsWorstCase>;964 defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFiveP600VectorMask], mx, IsWorstCase>;965 }966 }967 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;968 let ReleaseAtCycles = [LMulLat] in {969 let Latency = 2 in970 defm "" : LMULWriteResMX<"WriteVIotaV", [SiFiveP600VectorMask], mx, IsWorstCase>;971 972 // vid.v isn't executed by the mask unit.973 let Latency = !if(!eq(mx, "M8"), 4, !if(!eq(mx, "M4"), 2, 1)) in974 defm "" : LMULWriteResMX<"WriteVIdxV", [SiFiveP600VectorArith], mx, IsWorstCase>;975 }976}977 978// 16. Vector Permutation Instructions979// Simple Slide980foreach mx = SchedMxList in {981 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;982 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;983 let ReleaseAtCycles = [LMulLat] in {984 let Latency = SiFiveP600VSlideI<mx>.c in985 defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;986 987 let Latency = SiFiveP600VSlide1<mx>.c in {988 defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP600VEXQ0], mx, IsWorstCase>;989 defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP600VEXQ0], mx, IsWorstCase>;990 }991 }992}993foreach mx = ["MF8", "MF4", "MF2", "M1"] in {994 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;995 let Latency = 2, ReleaseAtCycles = [1] in {996 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP600VEXQ0], mx, IsWorstCase>;997 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP600VEXQ0], mx, IsWorstCase>;998 }999}1000 1001// Complex Slide1002foreach mx = ["M8", "M4", "M2"] in {1003 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;1004 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;1005 let Latency = SiFiveP600VSlideXComplex<mx>.latency in {1006 let ReleaseAtCycles = [SiFiveP600VSlideXComplex<mx, /*isUp=*/true>.cycles] in1007 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP600VEXQ1], mx, IsWorstCase>;1008 let ReleaseAtCycles = [SiFiveP600VSlideXComplex<mx, /*isUp=*/false>.cycles] in1009 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP600VEXQ1], mx, IsWorstCase>;1010 }1011}1012 1013let Latency = 2, ReleaseAtCycles = [2] in {1014 def : WriteRes<WriteVMovXS, [SiFiveP600VectorArith]>;1015 def : WriteRes<WriteVMovSX, [SiFiveP600VectorArith]>;1016 def : WriteRes<WriteVMovFS, [SiFiveP600VectorArith]>;1017 def : WriteRes<WriteVMovSF, [SiFiveP600VectorArith]>;1018}1019 1020// Simple Gather and Compress1021foreach mx = ["MF8", "MF4", "MF2", "M1"] in {1022 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;1023 let Latency = 3, ReleaseAtCycles = [1] in {1024 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP600VEXQ1], mx, IsWorstCase>;1025 }1026}1027 1028foreach mx = ["MF8", "MF4", "MF2", "M1"] in {1029 foreach sew = SchedSEWSet<mx>.val in {1030 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;1031 let Latency = 3, ReleaseAtCycles = [1] in {1032 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;1033 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;1034 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;1035 }1036 }1037}1038 1039// Complex Gather and Compress1040foreach mx = ["M2", "M4", "M8"] in {1041 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;1042 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;1043 let Latency = 6, ReleaseAtCycles = [SiFiveP600VPermutationComplex<mx>.c] in {1044 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP600VEXQ1], mx, IsWorstCase>;1045 }1046}1047 1048foreach mx = ["M2", "M4", "M8"] in {1049 foreach sew = SchedSEWSet<mx>.val in {1050 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;1051 defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;1052 let Latency = 6 in {1053 let ReleaseAtCycles = [SiFiveP600VPermutationComplex<mx>.c] in {1054 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;1055 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;1056 }1057 1058 let ReleaseAtCycles = [!add(SiFiveP600VPermutationComplex<mx>.c, 1)] in1059 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;1060 }1061 }1062}1063 1064// Simple Vrgather.vi1065foreach mx = SchedMxList in {1066 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;1067 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;1068 let Latency = 3, ReleaseAtCycles = [LMulLat] in {1069 defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFiveP600VEXQ1], mx, IsWorstCase>;1070 }1071}1072 1073// Vector Crypto1074foreach mx = SchedMxList in {1075 defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;1076 defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;1077 // Zvbb1078 let ReleaseAtCycles = [LMulLat] in {1079 let Latency = 2 in {1080 // FIXME: Exegesis was not able to measure the latency of these instructions.1081 // We probably should update them at some point.1082 defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1083 defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1084 defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1085 defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1086 }1087 1088 let Latency = SiFiveP600VCryptoLatency<mx>.c in {1089 defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1090 defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1091 defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1092 1093 def P600WriteVANDN_ # mx : SchedWriteRes<[SiFiveP600VectorCrypto]>;1094 }1095 }1096 1097 // Special case for VANDN -- we execute it on vector crypto unit.1098 defvar P600VANDNBaseSchedRW = [!cast<SchedWrite>("P600WriteVANDN_" # mx),1099 // VANDN always merge read operand.1100 !cast<SchedRead>("ReadVPassthru_" # mx),1101 !cast<SchedRead>("ReadVIALUV_" # mx),1102 !cast<SchedRead>("ReadVIALUV_" # mx)];1103 def : InstRW<P600VANDNBaseSchedRW,1104 (instregex "^PseudoVANDN_V(V|X)_" # mx # "$")>;1105 def : InstRW<!listconcat(P600VANDNBaseSchedRW, [!cast<SchedRead>("ReadVMask")]),1106 (instregex "^PseudoVANDN_V(V|X)_" # mx # "_MASK$")>;1107 1108 // Zvbc1109 let Latency = SiFiveP600VCryptoLatency<mx>.c, ReleaseAtCycles = [LMulLat] in {1110 defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1111 defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1112 }1113 // Zvkb1114 // VANDN uses WriteVIALU[V|X|I]1115 let Latency = SiFiveP600VCryptoLatency<mx>.c, ReleaseAtCycles = [LMulLat] in {1116 defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1117 defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1118 defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1119 defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1120 defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1121 }1122 // Zvkg1123 let Latency = SiFiveP600VCryptoLatency<mx>.c, ReleaseAtCycles = [LMulLat] in {1124 defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1125 defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1126 }1127 // ZvknhaOrZvknhb1128 // FIXME: The latency is probably wrong.1129 let Latency = 3, ReleaseAtCycles = [LMulLat] in {1130 defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1131 defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1132 defvar ZvknhSEWs = !listremove(SchedSEWSet<mx>.val, [8, 16]);1133 // Largest SEW is the last element, assuming SchedSEWSet is sorted in ascending1134 // order.1135 defvar LargestZvknhSEW = !foldl(!head(ZvknhSEWs), ZvknhSEWs, last, curr, curr);1136 foreach sew = ZvknhSEWs in {1137 // The worst case for Zvknh[ab] is designated to the largest SEW and LMUL.1138 defvar IsWorstCaseVSHA2MSV = !and(IsWorstCase, !eq(sew, LargestZvknhSEW));1139 let ReleaseAtCycles = [SiFiveP600VSHA2MSCycles<mx, sew>.c] in1140 defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SiFiveP600VectorCrypto], mx, sew,1141 IsWorstCaseVSHA2MSV>;1142 }1143 }1144 // Zvkned1145 let Latency = 2 in {1146 let ReleaseAtCycles = [LMulLat] in {1147 defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1148 defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1149 defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1150 }1151 1152 let ReleaseAtCycles = [!if(!lt(LMulLat, 2), LMulLat, !div(LMulLat, 2))] in1153 defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1154 }1155 // Zvksed1156 let Latency = 3, ReleaseAtCycles = [SiFiveP600VSM3CCycles<mx>.c] in1157 defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1158 let Latency = 6, ReleaseAtCycles = [LMulLat] in1159 defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1160 let Latency = 3, ReleaseAtCycles = [LMulLat] in {1161 defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1162 defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP600VectorCrypto], mx, IsWorstCase>;1163 }1164}1165 1166// Others1167def : WriteRes<WriteCSR, [SiFiveP600SYS]>;1168def : WriteRes<WriteNop, []>;1169def : WriteRes<WriteRdVLENB, [SiFiveP600SYS]>;1170 1171// FIXME: This could be better modeled by looking at the regclasses of the operands.1172def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;1173 1174//===----------------------------------------------------------------------===//1175// Bypass and advance1176def : ReadAdvance<ReadJmp, 0>;1177def : ReadAdvance<ReadJalr, 0>;1178def : ReadAdvance<ReadCSR, 0>;1179def : ReadAdvance<ReadStoreData, 0>;1180def : ReadAdvance<ReadMemBase, 0>;1181def : ReadAdvance<ReadIALU, 0>;1182def : ReadAdvance<ReadIALU32, 0>;1183def : ReadAdvance<ReadShiftImm, 0>;1184def : ReadAdvance<ReadShiftImm32, 0>;1185def : ReadAdvance<ReadShiftReg, 0>;1186def : ReadAdvance<ReadShiftReg32, 0>;1187def : ReadAdvance<ReadIDiv, 0>;1188def : ReadAdvance<ReadIDiv32, 0>;1189def : ReadAdvance<ReadIRem, 0>;1190def : ReadAdvance<ReadIRem32, 0>;1191def : ReadAdvance<ReadIMul, 0>;1192def : ReadAdvance<ReadIMul32, 0>;1193def : ReadAdvance<ReadAtomicWA, 0>;1194def : ReadAdvance<ReadAtomicWD, 0>;1195def : ReadAdvance<ReadAtomicDA, 0>;1196def : ReadAdvance<ReadAtomicDD, 0>;1197def : ReadAdvance<ReadAtomicLDW, 0>;1198def : ReadAdvance<ReadAtomicLDD, 0>;1199def : ReadAdvance<ReadAtomicSTW, 0>;1200def : ReadAdvance<ReadAtomicSTD, 0>;1201def : ReadAdvance<ReadFStoreData, 0>;1202def : ReadAdvance<ReadFMemBase, 0>;1203def : ReadAdvance<ReadFAdd16, 0>;1204def : ReadAdvance<ReadFAdd32, 0>;1205def : ReadAdvance<ReadFAdd64, 0>;1206def : ReadAdvance<ReadFMul16, 0>;1207def : ReadAdvance<ReadFMA16, 0>;1208def : ReadAdvance<ReadFMA16Addend, 0>;1209def : ReadAdvance<ReadFMul32, 0>;1210def : ReadAdvance<ReadFMA32, 0>;1211def : ReadAdvance<ReadFMA32Addend, 0>;1212def : ReadAdvance<ReadFMul64, 0>;1213def : ReadAdvance<ReadFMA64, 0>;1214def : ReadAdvance<ReadFMA64Addend, 0>;1215def : ReadAdvance<ReadFDiv16, 0>;1216def : ReadAdvance<ReadFDiv32, 0>;1217def : ReadAdvance<ReadFDiv64, 0>;1218def : ReadAdvance<ReadFSqrt16, 0>;1219def : ReadAdvance<ReadFSqrt32, 0>;1220def : ReadAdvance<ReadFSqrt64, 0>;1221def : ReadAdvance<ReadFCmp16, 0>;1222def : ReadAdvance<ReadFCmp32, 0>;1223def : ReadAdvance<ReadFCmp64, 0>;1224def : ReadAdvance<ReadFSGNJ16, 0>;1225def : ReadAdvance<ReadFSGNJ32, 0>;1226def : ReadAdvance<ReadFSGNJ64, 0>;1227def : ReadAdvance<ReadFMinMax16, 0>;1228def : ReadAdvance<ReadFMinMax32, 0>;1229def : ReadAdvance<ReadFMinMax64, 0>;1230def : ReadAdvance<ReadFCvtF16ToI32, 0>;1231def : ReadAdvance<ReadFCvtF16ToI64, 0>;1232def : ReadAdvance<ReadFCvtF32ToI32, 0>;1233def : ReadAdvance<ReadFCvtF32ToI64, 0>;1234def : ReadAdvance<ReadFCvtF64ToI32, 0>;1235def : ReadAdvance<ReadFCvtF64ToI64, 0>;1236def : ReadAdvance<ReadFCvtI32ToF16, 0>;1237def : ReadAdvance<ReadFCvtI32ToF32, 0>;1238def : ReadAdvance<ReadFCvtI32ToF64, 0>;1239def : ReadAdvance<ReadFCvtI64ToF16, 0>;1240def : ReadAdvance<ReadFCvtI64ToF32, 0>;1241def : ReadAdvance<ReadFCvtI64ToF64, 0>;1242def : ReadAdvance<ReadFCvtF32ToF64, 0>;1243def : ReadAdvance<ReadFCvtF64ToF32, 0>;1244def : ReadAdvance<ReadFCvtF16ToF32, 0>;1245def : ReadAdvance<ReadFCvtF32ToF16, 0>;1246def : ReadAdvance<ReadFCvtF16ToF64, 0>;1247def : ReadAdvance<ReadFCvtF64ToF16, 0>;1248def : ReadAdvance<ReadFMovF16ToI16, 0>;1249def : ReadAdvance<ReadFMovI16ToF16, 0>;1250def : ReadAdvance<ReadFMovF32ToI32, 0>;1251def : ReadAdvance<ReadFMovI32ToF32, 0>;1252def : ReadAdvance<ReadFMovF64ToI64, 0>;1253def : ReadAdvance<ReadFMovI64ToF64, 0>;1254def : ReadAdvance<ReadFClass16, 0>;1255def : ReadAdvance<ReadFClass32, 0>;1256def : ReadAdvance<ReadFClass64, 0>;1257 1258// Bitmanip1259def : ReadAdvance<ReadRotateImm, 0>;1260def : ReadAdvance<ReadRotateImm32, 0>;1261def : ReadAdvance<ReadRotateReg, 0>;1262def : ReadAdvance<ReadRotateReg32, 0>;1263def : ReadAdvance<ReadCLZ, 0>;1264def : ReadAdvance<ReadCLZ32, 0>;1265def : ReadAdvance<ReadCTZ, 0>;1266def : ReadAdvance<ReadCTZ32, 0>;1267def : ReadAdvance<ReadCPOP, 0>;1268def : ReadAdvance<ReadCPOP32, 0>;1269def : ReadAdvance<ReadORCB, 0>;1270def : ReadAdvance<ReadIMinMax, 0>;1271def : ReadAdvance<ReadREV8, 0>;1272def : ReadAdvance<ReadSHXADD, 0>;1273def : ReadAdvance<ReadSHXADD32, 0>;1274def : ReadAdvance<ReadSingleBit, 0>;1275def : ReadAdvance<ReadSingleBitImm, 0>;1276 1277// 6. Configuration-Setting Instructions1278def : ReadAdvance<ReadVSETVLI, 0>;1279def : ReadAdvance<ReadVSETVL, 0>;1280 1281// 7. Vector Loads and Stores1282def : ReadAdvance<ReadVLDX, 0>;1283def : ReadAdvance<ReadVSTX, 0>;1284defm "" : LMULReadAdvance<"ReadVSTEV", 0>;1285defm "" : LMULReadAdvance<"ReadVSTM", 0>;1286def : ReadAdvance<ReadVLDSX, 0>;1287def : ReadAdvance<ReadVSTSX, 0>;1288defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;1289defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;1290defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;1291defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;1292defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;1293defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;1294defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;1295defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;1296defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;1297defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;1298defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;1299defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;1300defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;1301defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;1302defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;1303defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;1304defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;1305defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;1306defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;1307defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;1308defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;1309defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;1310defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;1311defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;1312// LMUL Aware1313def : ReadAdvance<ReadVST1R, 0>;1314def : ReadAdvance<ReadVST2R, 0>;1315def : ReadAdvance<ReadVST4R, 0>;1316def : ReadAdvance<ReadVST8R, 0>;1317 1318// 12. Vector Integer Arithmetic Instructions1319defm : LMULReadAdvance<"ReadVIALUV", 0>;1320defm : LMULReadAdvance<"ReadVIALUX", 0>;1321defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;1322defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;1323defm : LMULReadAdvance<"ReadVExtV", 0>;1324defm : LMULReadAdvance<"ReadVICALUV", 0>;1325defm : LMULReadAdvance<"ReadVICALUX", 0>;1326defm : LMULReadAdvance<"ReadVShiftV", 0>;1327defm : LMULReadAdvance<"ReadVShiftX", 0>;1328defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;1329defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;1330defm : LMULReadAdvance<"ReadVICmpV", 0>;1331defm : LMULReadAdvance<"ReadVICmpX", 0>;1332defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;1333defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;1334defm : LMULReadAdvance<"ReadVIMulV", 0>;1335defm : LMULReadAdvance<"ReadVIMulX", 0>;1336defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;1337defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;1338defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;1339defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;1340defm : LMULReadAdvance<"ReadVIMulAddV", 0>;1341defm : LMULReadAdvance<"ReadVIMulAddX", 0>;1342defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;1343defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;1344defm : LMULReadAdvance<"ReadVIMergeV", 0>;1345defm : LMULReadAdvance<"ReadVIMergeX", 0>;1346defm : LMULReadAdvance<"ReadVIMovV", 0>;1347defm : LMULReadAdvance<"ReadVIMovX", 0>;1348 1349// 13. Vector Fixed-Point Arithmetic Instructions1350defm "" : LMULReadAdvance<"ReadVSALUV", 0>;1351defm "" : LMULReadAdvance<"ReadVSALUX", 0>;1352defm "" : LMULReadAdvance<"ReadVAALUV", 0>;1353defm "" : LMULReadAdvance<"ReadVAALUX", 0>;1354defm "" : LMULReadAdvance<"ReadVSMulV", 0>;1355defm "" : LMULReadAdvance<"ReadVSMulX", 0>;1356defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;1357defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;1358defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;1359defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;1360 1361// 14. Vector Floating-Point Instructions1362defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;1363defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;1364defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;1365defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;1366defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;1367defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;1368defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;1369defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;1370defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;1371defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;1372defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;1373defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;1374defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;1375defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;1376defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;1377defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;1378defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;1379defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;1380defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;1381defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;1382defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;1383defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;1384defm "" : LMULReadAdvance<"ReadVFClassV", 0>;1385defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;1386defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;1387defm "" : LMULReadAdvance<"ReadVFMovF", 0>;1388defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;1389defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;1390defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;1391defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;1392defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;1393defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;1394defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;1395defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;1396 1397// 15. Vector Reduction Operations1398def : ReadAdvance<ReadVIRedV, 0>;1399def : ReadAdvance<ReadVIRedV0, 0>;1400def : ReadAdvance<ReadVIWRedV, 0>;1401def : ReadAdvance<ReadVIWRedV0, 0>;1402def : ReadAdvance<ReadVFRedV, 0>;1403def : ReadAdvance<ReadVFRedV0, 0>;1404def : ReadAdvance<ReadVFRedOV, 0>;1405def : ReadAdvance<ReadVFRedOV0, 0>;1406def : ReadAdvance<ReadVFWRedV, 0>;1407def : ReadAdvance<ReadVFWRedV0, 0>;1408def : ReadAdvance<ReadVFWRedOV, 0>;1409def : ReadAdvance<ReadVFWRedOV0, 0>;1410 1411// 16. Vector Mask Instructions1412defm "" : LMULReadAdvance<"ReadVMALUV", 0>;1413defm "" : LMULReadAdvance<"ReadVMPopV", 0>;1414defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;1415defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;1416defm "" : LMULReadAdvance<"ReadVIotaV", 0>;1417 1418// 17. Vector Permutation Instructions1419def : ReadAdvance<ReadVMovXS, 0>;1420def : ReadAdvance<ReadVMovSX_V, 0>;1421def : ReadAdvance<ReadVMovSX_X, 0>;1422def : ReadAdvance<ReadVMovFS, 0>;1423def : ReadAdvance<ReadVMovSF_V, 0>;1424def : ReadAdvance<ReadVMovSF_F, 0>;1425defm "" : LMULReadAdvance<"ReadVISlideV", 0>;1426defm "" : LMULReadAdvance<"ReadVISlideX", 0>;1427defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;1428defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;1429defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;1430defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;1431defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;1432defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;1433defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;1434defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;1435defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;1436defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;1437// LMUL Aware1438def : ReadAdvance<ReadVMov1V, 0>;1439def : ReadAdvance<ReadVMov2V, 0>;1440def : ReadAdvance<ReadVMov4V, 0>;1441def : ReadAdvance<ReadVMov8V, 0>;1442 1443// Others1444def : ReadAdvance<ReadVMask, 0>;1445def : ReadAdvance<ReadVPassthru_WorstCase, 0>;1446foreach mx = SchedMxList in {1447 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;1448 foreach sew = SchedSEWSet<mx>.val in1449 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;1450}1451 1452// Vector Crypto Extensions1453// Zvbb1454defm "" : LMULReadAdvance<"ReadVBREVV", 0>;1455defm "" : LMULReadAdvance<"ReadVCLZV", 0>;1456defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;1457defm "" : LMULReadAdvance<"ReadVCTZV", 0>;1458defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;1459defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;1460// Zvbc1461defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;1462defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;1463// Zvkb1464// VANDN uses ReadVIALU[V|X|I]1465defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;1466defm "" : LMULReadAdvance<"ReadVREV8V", 0>;1467defm "" : LMULReadAdvance<"ReadVRotV", 0>;1468defm "" : LMULReadAdvance<"ReadVRotX", 0>;1469// Zvkg1470defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;1471defm "" : LMULReadAdvance<"ReadVGMULV", 0>;1472// Zvknha or Zvknhb1473defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;1474defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;1475defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>;1476// Zvkned1477defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;1478defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;1479defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;1480defm "" : LMULReadAdvance<"ReadVAESZV", 0>;1481// Zvksed1482defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;1483defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;1484// Zbksh1485defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;1486defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;1487 1488//===----------------------------------------------------------------------===//1489// Unsupported extensions1490defm : UnsupportedSchedQ;1491defm : UnsupportedSchedZabha;1492defm : UnsupportedSchedZbc;1493defm : UnsupportedSchedZbkb;1494defm : UnsupportedSchedZbkx;1495defm : UnsupportedSchedSFB;1496defm : UnsupportedSchedZfa;1497defm : UnsupportedSchedXsf;1498}1499